Freescale MCIMX357DVM5B 90 nm Multimedia Application Processor
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1 Freescale MCIMX357DVM5B 90 nm Multimedia Application Processor ESD Protection Device Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:
2 ESD Protection Device Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 2 Device Identification 2.1 Package 2.2 Die 3 ESD Circuit Analysis 3.1 ESD Protection Circuit 3.2 Plan-View Images of ggpmos 1 and ggpmos Plan-View Images of ggnmos 1, ggnmos 3, and ggnmos Plan-View Images of ggnmos 6, ggpmos 6, and Resistor Plan-View Images of Trigger Circuit of Type 2 I/O Cell 3.6 Plan-View Images of Clamp Transistor Plan-View Images of ggnmos 2, ggpmos 3, and Resistor Plan-View Images of Trigger Circuit at Ground Pad Cell 3.9 Trigger Circuit at VDD Pad Cell Plan View 4 Cross-Sectional FESEM and SCM Analyses 4.1 FESEM and SCM Analyses of ggpmos 1 and ggpmos FESEM and SCM Analyses of ggnmos FESEM and SCM Analyses of ggnmos 3 and ggnmos FESEM and SCM Analyses of ggpmos FESEM and SCM Analyses of ggnmos FESEM Analysis of Resistor 4.7 FESEM and SCM Analyses of Clamp Transistor 5 References 6 Statement of Measurement Uncertainty and Scope Variation About Chipworks
3 Overview Overview 1.1 List of Figures 2 Device Identification Package Top Package Bottom Package Ball Map of the MCIMX357DVM5B Plan-View Package X-Ray Die Photograph Die Markings Bond Pads Die Corner (A) Die Corner (B) Die Corner (C) Die Corner (D) Die Edge Die Seal I/O Bonding Pad Cross Section General Device Structure of the Die Minimum Contacted Gate Pitch 3 ESD Circuit Analysis Die Photograph with Analyzed Area Pin Out of I/O Cells of Interest Poly Delayered Type 1 I/O Cell Plan View ESD Circuit of Type 1 I/O Cell Poly Delayered Type 2 I/O Cell Plan View ESD Circuit Type 2 I/O Cell Poly Delayered Type 3 I/O Cell Plan View ESD Circuit Type 3 I/O Cell Poly Delayered Type 4 I/O Cell Plan View Poly Delayered Type 6 Ground Power Cell Plan View Poly Delayered Type 6 Ground Power Cell Plan View ESD Protection Circuit ggpmos 1 and ggpmos 2 Substrate Plan View ggpmos 1 and ggpmos 2 Poly Plan View ggpmos 1 and ggpmos 2 Detail Plan View ggpmos 1 and ggpmos 2 Metal 1 Plan View ggpmos 1 and ggpmos 2 Metal 2 Plan View ggpmos 1 and ggpmos 2 Metal 3 Plan View ggnmos 1, ggnmos 3, and ggnmos 4 Substrate Plan View ggnmos 1, ggnmos 3, and ggnmos 4 Poly Plan View ggnmos 1, ggnmos 3, and ggnmos 4 Detail Plan View ggnmos 1, ggnmos 3, and ggnmos 4 Metal 1 Plan View ggnmos 1, ggnmos 3, and ggnmos 4 Metal 2 Plan View ggnmos 1, ggnmos 3, and ggnmos 4 Metal 3 Plan View
4 Overview ggnmos 6, ggpmos 6, and Resistor 2 Substrate ggnmos 6, ggpmos 6, and Resistor 2 Poly ggnmos 6, ggpmos 6, and Resistor 2 Metal ggnmos 6, ggpmos 6, and Resistor 2 Metal ggnmos 6, ggpmos 6, and Resistor 2 Metal Trigger Circuit of the Type 2 I/O Cell Poly Delayered Trigger Circuit Plan View Clamp Transistor 1 Substrate Plan View Clamp Transistor 1 Poly Plan View Clamp Transistor 1 Detail Plan View Clamp Transistor 1 Metal 1 Plan View Clamp Transistor 1 Metal 2 Plan View Clamp Transistor 1 Metal 3 Plan View ggnmos 2, ggpmos 3, and Resistor 1 Substrate Plan View ggnmos 2, ggpmos 3, and Resistor 1 Poly Plan View ggpmos 3 Detail Plan View ggnmos 2 Detail Plan View Resistor 1 Detail Plan View ggnmos 2, ggpmos 3, and Resistor 1 Metal 1 Plan View ggnmos 2, ggpmos 3, and Resistor 1 Metal 2 Plan View ggnmos 2, ggpmos 3, and Resistor 1 Metal 3 Plan View Trigger Circuit of Type 6 Ground Cell Poly Delayered Trigger Circuit at Ground Cell Plan View Trigger Circuit of Type 6 VDD Cell Poly Delayered Trigger Circuit at Power Cell Plan View 4 Cross-Sectional FESEM and SCM Analyses ggpmos 1 and ggpmos 2 Cross Section FESEM ggpmos 1 Transistor Detail FESEM ggpmos 1 and ggpmos 2 Cross Section SCM ggnmos 1 Cross Section FESEM ggnmos 1 Detail FESEM ggnmos 1 Cross Section SCM ggnmos 1 Detail SCM Left Boundary of ggnmos 1 FESEM Right Boundary of ggnmos 1 FESEM ggnmos 3 and ggnmos 4 Cross Section FESEM Left Boundary of ggnmos 3 FESEM Boundary Between ggnmos 3 and ggnmos 4 FESEM Right Boundary of ggnmos 4 FESEM ggnmos 3 and ggnmos 4 Cross Section SCM Boundary Between ggnmos 3 and ggnmos 4 Detail SCM ggpmos 3 Cross Section FESEM ggpmos 3 Detail FESEM ggpmos 3 Detail SCM ggnmos 2 Cross Section FESEM
5 Overview ggnmos 2 Detail FESEM ggnmos 2 Cross Section SCM ggnmos 2 Detail SCM Resistor Cross Section FESEM Resistor Detail FESEM NMOS Clamp Transistor Cross Section FESEM NMOS Clamp Transistor Detail FESEM NMOS Clamp Transistor Cross Section SCM NMOS Clamp Transistor Detail SCM 1.2 List of Tables 1 Overview Device summary 3 ESD Circuit Analysis Transistor Dimensions in ggpmos 1 and ggpmos Transistor Dimensions in ggnmos 1, ggnmos 3, and ggnmos Trigger Circuit Transistor Sizes Trigger Circuit Transistor Sizes Trigger Circuit Transistor Sizes
6 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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