Low Power, 350 MHz Voltage Feedback Amplifiers AD8038/AD8039

Transcription

1 Low Power, MHz Voltage Feedback Amplifiers AD88/AD89 FEATURES Low power: ma supply current/amp High speed MHz, db bandwidth (G = +) V/μs slew rate Low cost Low noise 8 nv/ khz fa/ khz Low input bias current: na maximum Low distortion 9 db MHz db MHz Wide supply range: V to V Small packaging: 8-lead SOT-, -lead SC, and 8-lead SOIC APPLICATIONS Battery-powered instrumentation Filters A/D drivers Level shifting Buffering Photo multipliers GENERAL DESCRIPTION The AD88 (single) and AD89 (dual) amplifiers are high speed ( MHz) voltage feedback amplifiers with an exceptionally low quiescent current of. ma/amplifier typical (. ma maximum). The AD88 single amplifier in the 8-lead SOIC package has a disable feature. Despite being low power and low cost, the amplifier provides excellent overall performance. Additionally, it offers a high slew rate of V/μs and a low input offset voltage of mv maximum. The Analog Devices, Inc., proprietary XFCB process allows low noise operation (8 nv/ Hz and fa/ Hz) at extremely low quiescent currents. Given a wide supply voltage range ( V to V), wide bandwidth, and small packaging, the AD88 and AD89 amplifiers are designed to work in a variety of applications where power and space are at a premium. The AD88 and AD89 amplifiers have a wide input commonmode range of V from either rail and swing to within V of each rail on the output. These amplifiers are optimized for driving capacitive loads up to pf. If driving larger capacitive loads, a small series resistor is needed to avoid excessive peaking or overshoot. FUNCTIONAL BLOCK DIAGRAM NC IN +IN V S AD88 8 DISABLE +V S V OUT NC NC = NO CONNECT Figure. 8-lead SOIC (R) V OUT V S +IN V OUT AD88 +V S IN Figure. -Lead SC (KS) IN +IN V S AD89 +V S NC = NO CONNECT Figure. 8-Lead SOIC (R) and 8-Lead SOT- (RJ) 8 V OUT IN +IN The AD89 amplifier is available in a 8-lead SOT- package, and the single AD88 is available in both an 8-lead SOIC and a -lead SC package. These amplifiers are rated to work over the industrial temperature range of C to +8 C. 8 9 G = + G = + G = + G = +. Figure. Small Signal Frequency Response for Various Gains, VOUT = mv p-p, VS = ± V Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD88/AD89 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... Absolute Maximum Ratings... Maximum Power Dissipation... Output Short Circuit... ESD Caution... Typical Performance Characteristics... Layout, Grounding, and Bypassing Considerations... Disable... Power Supply Bypassing... Grounding... Input Capacitance... Output Capacitance... Input-to-Output Coupling... Applications Information... Low Power ADC Driver... Low Power Active Video Filter... Outline Dimensions... Ordering Guide... REVISION HISTORY 8/9 Rev. F to Rev. G Changes to Applications Section and General Description Section... Changes to Disable Section and Grounding Section... Changes to Low Power ADC Driver Section and Low Power Active Video Filter Section... Updated Outline Dimensions... Changes to Ordering Guide... 8/ Rev. E to Rev. F Changes to Figure... 8/ Rev. D to Rev. E Change to TPC... 8 / Rev. C to Rev. D Changes to Ordering Guide... Updated TPC Caption... 8 / Rev. B to Rev. C Updated Connection Diagrams... Updated Ordering Guide... Updated Outline Dimensions... / Rev. A to Rev. B Add Part Number AD88... Universal Changes to Product Title... Changes to Features... Changes to Product Description... Changes to Connection Diagram... Update to Specifications... Update to Maximum Power Dissipation... Update to Output Short Circuit... Update to Ordering Guide... Change to Figure... Change to TPC... Change to TPC 8... Change to TPC... Change to TPC Change to TPC... 8 Change to TPC... 8 Added TPC... 8 Added TPC... 9 Edits to Low Power Active Video Filter... Change to Figure... / Rev. to Rev. A Changes to Features... Update Specifications..., Edits to TPC 9... Rev. G Page of

3 AD88/AD89 SPECIFICATIONS TA = C, VS = ± V, RL = kω, Gain = +, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth G = +, VO =. V p-p MHz G = +, VO =. V p-p MHz G = +, VO = V p-p MHz Bandwidth for. db Flatness G = +, VO =. V p-p MHz Slew Rate G = +, VO = V step, RL = kω V/μs Overdrive Recovery Time G = +, V overdrive ns Settling Time to.% G = +, VO = V step 8 ns NOISE/HARMONIC PERFORMANCE SFDR Second Harmonic fc = MHz, VO = V p-p, RL = kω 9 dbc Third Harmonic fc = MHz, VO = V p-p, RL = kω 9 dbc Second Harmonic fc = MHz, VO = V p-p, RL = kω dbc Third Harmonic fc = MHz, VO = V p-p, RL = kω dbc Crosstalk, Output-to-Output (AD89) f = MHz, G = + db Input Voltage Noise f = khz 8 nv/ Hz Input Current Noise f = khz fa/ Hz DC PERFORMANCE Input Offset Voltage. mv Input Offset Voltage Drift. μv/ C Input Bias Current na Input Bias Current Drift na/ C Input Offset Current ± na Open-Loop Gain VO = ±. V db INPUT CHARACTERISTICS Input Resistance MΩ Input Capacitance pf Input Common-Mode Voltage Range RL = kω ± V Common-Mode Rejection Ratio VCM = ±. V db OUTPUT CHARACTERISTICS DC Output Voltage Swing RL = kω, saturated output ± V Capacitive Load Drive % overshoot, G = + pf POWER SUPPLY Operating Range. V Quiescent Current per Amplifier.. ma Power Supply Rejection Ratio Supply db +Supply db POWER-DOWN DISABLE Turn-On Time 8 ns Turn-Off Time ns Disable Voltage Part is Off +VS. V Disable Voltage Part is On +VS. V Disabled Quiescent Current. ma Disabled In/Out Isolation f = MHz db Only available in AD88 8-lead SOIC package. Rev. G Page of

4 AD88/AD89 TA = C, VS = V, RL = kω to VS/, Gain = +, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth G = +, VO =. V p-p MHz G = +, VO =. V p-p MHz G = +, VO = V p-p MHz Bandwidth for. db Flatness G = +, VO =. V p-p MHz Slew Rate G = +, VO = V step, RL = kω V/μs Overdrive Recovery Time G = +, V overdrive ns Settling Time to.% G = +, VO = V step 8 ns NOISE/HARMONIC PERFORMANCE SFDR Second Harmonic fc = MHz, VO = V p-p, RL = kω 8 dbc Third Harmonic fc = MHz, VO = V p-p, RL = kω 9 dbc Second Harmonic fc = MHz, VO = V p-p, RL = kω dbc Third Harmonic fc = MHz, VO = V p-p, RL = kω dbc Crosstalk, Output-to-Output f = MHz, G = + db Input Voltage Noise f = khz 8 nv/ Hz Input Current Noise f = khz fa/ Hz DC PERFORMANCE Input Offset Voltage.8 mv Input Offset Voltage Drift μv/ C Input Bias Current na Input Bias Current Drift na/ C Input Offset Current ± na Open-Loop Gain VO = ±. V db INPUT CHARACTERISTICS Input Resistance MΩ Input Capacitance pf Input Common-Mode Voltage Range RL = kω.. V Common-Mode Rejection Ratio VCM = ± V 9 db OUTPUT CHARACTERISTICS DC Output Voltage Swing RL = kω, saturated output.9. V Capacitive Load Drive % overshoot pf POWER SUPPLY Operating Range V Quiescent Current per Amplifier.9. ma Power Supply Rejection Ratio db POWER-DOWN DISABLE Turn-On Time ns Turn-Off Time ns Disable Voltage Part is Off +VS. V Disable Voltage Part is On +VS. V Disabled Quiescent Current. ma Disabled In/Out Isolation f = MHz db Only available in AD88 8-lead SOIC package. Rev. G Page of

5 AD88/AD89 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage. V Power Dissipation See Figure Common-Mode Input Voltage ±VS Differential Input Voltage ± V Storage Temperature Range C to + C Operating Temperature Range C to +8 C Lead Temperature (Soldering, sec) C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD88/AD89 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD88/AD89. Exceeding a junction temperature of C for an extended time can result in changes in the silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (θja), ambient temperature (TA), and total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as TJ = TA + (PD θja) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) multiplied by the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS/ IOUT, some of which is dissipated in the package and some in the load (VOUT IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = quiescent power + (total drive power load power) PD = [VS IS] + [(VS/) (VOUT/RL)] [VOUT /RL] MAXIMUM POWER DISSIPATION (W).... SOIC-8 SOT--8 SC- 9 AMBIENT TEMPERATURE ( C) Figure. Maximum Power Dissipation vs. Temperature for a -Layer Board RMS output voltages should be considered. If RL is referenced to VS, as in single-supply operation, then the total drive power is VS IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS / for RL to midsupply PD = (VS IS) + (VS/) /RL In single-supply operation with RL referenced to VS, worst case is VOUT = VS /. Airflow increases heat dissipation, effectively reducing θja. In addition, more metal directly in contact with the package leads from metal traces, throughholes, ground, and power planes reduce the θja. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the Layout, Grounding, and Bypassing Considerations section. Figure shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC ( C/W), -lead SC ( C/W), and 8-lead SOT- ( C/W) packages on a JEDEC standard -layer board. θja values are approximations. OUTPUT SHORT CIRCUIT Shorting the output to ground or drawing excessive current from the AD88/AD89 will likely cause a catastrophic failure. ESD CAUTION 9- Rev. G Page of

6 AD88/AD89 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: ± V, CL = pf, G = +, RG = RF = kω, RL = kω, VO = V p-p, Frequency = MHz, TA = C. 8 G = + R L = kω 9 G = + G = + R L = Ω G = + R L = kω. Figure. Small Signal Frequency Response for Various Gains, VOUT = mv p-p 9-. Figure 9. Small Signal Frequency Response for Various RL, VS = V, VOUT = mv p-p 9-9 V S = ±.V V S = ±.V 8 R L = kω V S = ±V R L = Ω R L = kω. Figure. Small Signal Frequency Response for Various Supplies, VOUT = mv p-p 9-. Figure. Large Signal Frequency Response for Various RL, VOUT = V p-p, VS = V 9-8 R L = kω R L = kω R L = Ω R L = kω R L = Ω R L = kω. Figure 8. Small Signal Frequency Response for Various RL, VS = ± V, VOUT = mv p-p 9-8. Figure. Large Signal Frequency Response for Various RL, VOUT = V p-p, VS = ± V 9- Rev. G Page of

7 AD88/AD89 C L = pf 8 8 C L = pf C L = pf OPEN-LOOP GAIN PHASE 9 PHASE (Degrees) Figure. Small Signal Frequency Response for Various CL, VOUT = mv p-p, VS = ± V, G = Figure. Open-Loop Gain and Phase, VS = ± V 9-9 C L = pf C L = pf C + C C L = pf +8 C Figure. Small Signal Frequency Response for Various CL, VOUT = mv p-p, VS = V, G = Figure. Frequency Response vs. Temperature, Gain = +, VS = ± V, VOUT = V p-p 9- V OUT = mv V OUT = V V OUT = mv V OUT = V HARMONIC DISTORTION (dbc) 8 R L = Ω HD R L = Ω HD R L = kω HD R L = kω HD 8. Figure. Frequency Response for Various Output Voltage Levels Figure. Harmonic Distortion vs. Frequency for Various Loads, VS = ± V, VOUT = V p-p, G = + 9- Rev. G Page of

8 AD88/AD89 HARMONIC DISTORTION (dbc) 8 8 R L = Ω HD R L = Ω HD R L = kω HD R L = kω HD HARMONIC DISTORTION (dbc) 8 9 MHz HD MHz HD MHz HD MHz HD MHz HD MHz HD Figure 8. Harmonic Distortion vs. Frequency for Various Loads, VS = V, VOUT = V p-p, G = AMPLITUDE (V p-p) Figure. Harmonic Distortion vs. VOUT Amplitude for Various Frequencies, VS = ± V, G = + 9- MHz HD HARMONIC DISTORTION (dbc) 8 9 G = + HD G = + HD G = + HD G = + HD HARMONIC DISTORTION (dbc) 8 MHz HD MHz HD MHz HD MHz HD MHz HD 8 9 Figure 9. Harmonic Distortion vs. Frequency for Various Gains, VS = ± V, VOUT = V p-p AMPLITUDE (V p-p) Figure. Harmonic Distortion vs. Amplitude for Various Frequencies, VS = V, G = + 9- HARMONIC DISTORTION (dbc) 8 9 G = + HD G = + HD G = + HD G = + HD VOLTAGE NOISE (nv/ Hz) 8 9 Figure. Harmonic Distortion vs. Frequency for Various Gains, VS = V, VOUT = V p-p 9- k k k M M M FREQUENCY (Hz) Figure. Input Voltage Noise vs. Frequency 9- Rev. G Page 8 of

9 AD88/AD89 k NOISE (fa/ Hz) k k C L = pf WITH R SNUB = 9.Ω C L = pf C L = pf k k k M FREQUENCY (Hz) Figure. Input Current Noise vs. Frequency 9- mv/div ns/div Figure. Small Signal Transient Response for Various CL, VS = V 9- R L = Ω R L = kω C L = pf WITH R SNUB = 9.Ω C L = pf C L = pf mv/div ns/div Figure. Small Signal Transient Response for Various RL, VS = V 9- mv/div ns/div Figure 8. Small Signal Transient Response for Various CL, VS = ± V 9-8 R L = Ω R L = kω R L = Ω R L = kω.v mv/div ns/div Figure. Small Signal Transient Response for Various RL, VS = ± V 9- mv/div ns/div Figure 9. Large Signal Transient Response for Various RL, VS = V 9-9 Rev. G Page 9 of

10 AD88/AD89 R L = kω IN R L = Ω OUT V/DIV ns/div Figure. Large Signal Transient Response for Various RL, VS = ± V 9- V/DIV ns/div Figure. Input Overdrive Recovery, Gain = + 9- C L = pf IN OUT.V C L = pf mv/div ns/div Figure. Large Signal Transient Response for Various CL, VS = V 9- INPUT V/DIV OUTPUT V/DIV ns/div Figure. Output Overdrive Recovery, Gain = + 9- C L = pf C L = pf mv/div V S = ±V G = + V OUT = V p-p +.% ERROR VOLTAGE.% t = V IN mv/div ns/div Figure. Large Signal Transient Response for Various CL, VS = ± V 9-.V/DIV ns/div Figure..% Settling Time VOUT = V p-p 9- Rev. G Page of

11 AD88/AD89 CROSSTALK (db) 8 SIDE B SIDE A PSRR (db) PSRR +PSRR 9 8. Figure. AD89 Crosstalk, VIN = V p-p, Gain = Figure 9. PSRR vs. Frequency V S = ±V CMRR (db) V S = +V V S = ±V V OUT (p-p) V S = +V 8 Figure. CMRR vs. Frequency, VIN = V p-p 9- R LOAD (Ω) Figure. Output Swing vs. Load Resistance 9-. IMPEDANCE Ω) V S = ±V SUPPLY CURRENT (ma).... V S = +V... Figure 8. Output Impedance vs. Frequency SUPPLY VOLTAGE (V) Figure. AD88 Supply Current vs. Supply Voltage 9- Rev. G Page of

12 AD88/AD89 ISOLATION (db) 8 9. Figure. AD88 Input-Output Isolation (G = +, RL = kω, VS = ± V) 9- Rev. G Page of

13 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS DISABLE The AD88 in the 8-lead SOIC package provides a disable feature. This feature disables the input from the output (see Figure for input-output isolation) and reduces the quiescent current from typically ma to. ma. When the DISABLE node is pulled below. V from the positive supply rail, the part becomes disabled. To enable the part, the DISABLE node needs to be pulled to greater than (VS.). POWER SUPPLY BYPASSING Power supply pins are actually inputs, and care must be taken so that a noise-free stable dc voltage is applied. The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering a majority of the noise. Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. The. μf or. μf (XR or NPO) chip capacitors are critical and should be placed as close as possible to the amplifier package. Larger chip capacitors, such as. μf capacitors, can be shared among a few closely spaced active components in the same signal path. A μf tantalum capacitor is less critical for high frequency bypassing and, in most cases, only one per board is needed at the supply inputs. GROUNDING A ground plane layer is important in densely packed PC boards to spread the current minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the high frequency impedance of the path. High speed currents in an inductive ground return create an unwanted voltage noise. The length of the high frequency bypass capacitor leads is most critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. AD88/AD89 INPUT CAPACITANCE Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few picofarads of capacitance reduces the input impedance at high frequencies, in turn increasing the gain of the amplifiers, causing peaking of the frequency response, or even oscillations if severe enough. It is recommended that the external passive components that are connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a distance of at least. mm from the input pins on all layers of the board. OUTPUT CAPACITANCE To a lesser extent, parasitic capacitances on the output can cause peaking of the frequency response. Two methods to minimize this effect include the following: Put a small value resistor in series with the output to isolate the load capacitor from the output stage of the amplifier, see Figure, Figure, Figure, and Figure 8. Increase the phase margin with higher noise gains or add a pole with a parallel resistor and capacitor from IN to the output. INPUT-TO-OUTPUT COUPLING The input and output signal traces should not be parallel to minimize capacitive coupling between the inputs and outputs, avoiding any positive feedback. Rev. G Page of

14 AD88/AD89 APPLICATIONS INFORMATION LOW POWER ADC DRIVER V V IN kω kω kω kω +V 8 V kω kω.µf µf kω AD89.µF µf kω.µf µf Ω Ω.V VINP VINN Figure. Schematic to Drive AD9 with the AD89 REF V AD9 The AD9 is a low power ( mw on a V supply), MSPS -bit converter. As such, the low power, high performance AD89 is an appropriate amplifier choice to drive it. In low supply voltage applications, differential analog inputs are needed to increase the dynamic range of the ADC inputs. Differential driving can also reduce second and other even-order distortion products. The AD89 can be used to make a dccoupled, single-ended-to-differential driver for driving these ADCs. Figure is a schematic of such a circuit for driving the AD9, -bit, MSPS ADC. The AD9 works best when the common-mode voltage at the input is at the midsupply or. V. The output stage design of the AD89 makes it ideal for driving these types of ADCs. In this circuit, one of the op amps is configured in the inverting mode, and the other is in the noninverting mode. However, to provide better bandwidth matching, each op amp is configured for a noise gain of +. The inverting op amp is configured for a gain of, and the noninverting op amp is configured for a gain of +. Each has a very similar ac response. The input signal to the noninverting op amp is divided by to normalize its voltage level and make it equal to the inverting output. The outputs of the op amps are centered at. V, which is the midsupply level of the ADC. This is accomplished by first taking the. V reference output of the ADC and dividing it by with a pair of kω resistors. The resulting. V is applied to the positive input of each op amp. This voltage is then multiplied by the gain of the op amps to provide a. V level at each output. 9- LOW POWER ACTIVE VIDEO FILTER Some composite video signals derived from a digital source contain clock feedthrough that can limit picture quality. Active filters made from op amps can be used in this application, but they consume mw to mw for each channel. In powersensitive applications, this can be too much, requiring the use of passive filters that can create impedance matching problems when driving any significant load. The AD88 can be used to make an effective low-pass active filter that consumes one-fifth of the power consumed by an active filter made from an op amp. Figure shows a circuit that uses a AD88 with ±. V supplies to create a three-pole Sallen-Key filter. This circuit uses a single RC pole in front of a standard -pole active section. V IN R Ω R 9.9Ω R 99Ω C pf R 9.9Ω 8pF C pf +.V AD88.V R F Ω.µF µf.µf µf Figure. Low-Pass Filter for Video R Ω V OUT Figure shows the frequency response of this filter. The response is down db at MHz; therefore, it passes the video band with little attenuation. The rejection at MHz is db, which provides more than a factor of in suppression of the clock components at this frequency.. Figure. Video Filter Response 9-9- Rev. G Page of

15 AD88/AD89 OUTLINE DIMENSIONS. (.98).8 (.89). (.).8 (.9) 8. (.).8 (.8). (.98). (.) COPLANARITY. SEATING PLANE. (.) BSC. (.88). (.). (.). (.) 8. (.98). (.). (.9). (.99). (.). (.) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) -A PIN. BSC MAX... COPLANARITY SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO--AA Figure. -Lead Thin Shrink Small Outline Transistor Package [SC] (KS-) Dimensions shown in millimeters Rev. G Page of

16 AD88/AD PIN INDICATOR.9 BSC. BSC...9. MAX. MIN.8 MAX. MIN. MAX.9 MIN SEATING PLANE. MAX.8 MIN 8. BSC... COMPLIANT TO JEDEC STANDARDS MO-8-BA Figure 8. 8-Lead Small Outline Transistor Package [SOT-] (RJ-8) Dimensions shown in millimeters 8-A ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD88AR C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD88AR-REEL C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD88AR-REEL C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD88ARZ C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD88ARZ-REEL C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD88ARZ-REEL C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD88AKSZ-R C to +8 C -Lead Thin Shrink Small Outline Transistor Package [SC] KS- HC AD88AKSZ-REEL C to +8 C -Lead Thin Shrink Small Outline Transistor Package [SC] KS- HC AD88AKSZ-REEL C to +8 C -Lead Thin Shrink Small Outline Transistor Package [SC] KS- HC AD89AR C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD89AR-REEL C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD89AR-REEL C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD89ARZ C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD89ARZ-REEL C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD89ARZ-REEL C to +8 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD89ART-R C to +8 C 8-Lead Small Outline Transistor Package [SOT-] RJ-8 HYA AD89ART-REEL C to +8 C 8-Lead Small Outline Transistor Package [SOT-] RJ-8 HYA AD89ART-REEL C to +8 C 8-Lead Small Outline Transistor Package [SOT-] RJ-8 HYA AD89ARTZ-R C to +8 C 8-Lead Small Outline Transistor Package [SOT-] RJ-8 HYA# AD89ARTZ-REEL C to +8 C 8-Lead Small Outline Transistor Package [SOT-] RJ-8 HYA# AD89ARTZ-REEL C to +8 C 8-Lead Small Outline Transistor Package [SOT-] RJ-8 HYA# Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.. 9 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D9--8/9(G) Rev. G Page of