High CMR Intelligent Power Module and Gate Drive Interface Optocoupler. Features. Specifications. Applications

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ACPL-P80 and ACPL-W80 High CMR Intelligent Power Module and Gate Drive Interface Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a

1 ACPL-P80 and ACPL-W80 High CMR Intelligent Power Module and Gate Drive Interface Optocoupler Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The ACPL-P80 and ACPL-W80 fast speed optocouplers contain a GaAsP LED and photo detector with built-in Schmitt trigger to provide logic-compatible waveforms, eliminating the need for additional wave shaping. The totem pole output eliminates the need for a pull up resistor and allows for direct drive Intelligent Power Module or gate drive. Minimized propagation delay difference between devices make these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. Functional Diagrams ACPL-P80 ANODE N.C. CATHODE ANODE N.C. CATHODE Note: A 0. μf bypass capacitor must be connected between pins and. Truth Table (Positive Logic) LED ON OFF VO HIGH LOW SHIELD ACPL-W80 SHIELD V CC V O Ground V CC V O Ground Features Performance Specified for Common IPM Applications Over Industrial Temperature Range. Short Maximum Propagation Delays Minimized Pulse Width Distortion (PWD) Very High Common Mode Rejection (CMR) Hysteresis Totem Pole Output (No Pull-up Resistor Required) Available in Stretched SO- package. Safety Approval: UL Recognized with 70 V rms for minute (000 Vrms for minute for all ACPL-W80 devices and Option 00 device for ACPL-P80) per UL77. CSA Approved. IEC/EN/DIN EN Approved: V IORM = 89 V peak for option 00 of ACPL-P80, and V IORM = 0 V peak for ACPL-W80. Specifications Wide operating temperature range: 0 C to 00 C. Maximum propagation delay t PHL / t PLH = 0 ns Maximum Pulse Width Distortion (PWD) = 0 ns. Propagation Delay Difference: Min. 00 ns, Max. 0 ns Wide Operating V CC Range:. to 0 Volts 0 kv/μs minimum common mode rejection (CMR) at V CM = 000 V. Applications IPM Interface Isolation Isolated IGBT/MOSFET Gate Drive AC and Brushless DC Motor Drives Industrial Inverters General Digital Isolation CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Ordering Information ACPL-P80 is UL Recognized (ACPL-W80 pending) with 70 Vrms for minute per UL77 and is approved under CSA Component Accep tance Notice #, File CA 88. Part number ACPL-P80 Option RoHS Compliant Package Surface Mount Tape & Reel UL VRMS / Minute Rating IEC/EN/DIN EN Quantity -000E X 00 per tube -00E X X 000 per reel -00E 7mm X X 00 per reel Stretched -0E SO- X X X 000 per reel -00E X X 00 per tube -0E X X X 000 per reel -000E X X 00 per tube ACPL-W80^ -00E 8mm X X X 000 per reel Stretched -00E SO- X X X 00 per tube -0E X X X X 000 per reel ^ Advance information, subject to changes. To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-P80-0E to order product of Stretched SO- package in Tape and Reel packaging with IEC/EN/DIN EN Safety Approval in RoHS compliant. Example : ACPL-P80-000E to order product of Stretched SO- package in tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

3 Package Outline Drawings ACPL-P80 Stretched SO- Package, 7 mm clearance 0.8 ± ± BSG ± ± ± ± ± ±0.00 ± ±0.00 NOM. 9.7 ± ± ± ±0.00 Floating Lead Protusions max. 0. [0.0] Dimensions in Millimeters [ Inches ] Lead Coplanarity= 0.mm [0.00 Inches ] ACPL-W80 Stretched SO- Package, 8 mm clearance 0.8 ± ± BSG [0.00] ± ± ± ± ± ± ±0.0 [0.09 ±0.00] NOM..00 ±0. 0. ± ± ±0.00 Floating Lead protusion max. 0.[0.0] Dimensions in millimeters [Inches] Lead Coplanarity=0.mm [0.00 Inches]

4 Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-00 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-P80 is approved (ACPL-W80 pending) by the following organizations: IEC/EN/DIN EN (Option 00 only) Approval under: IEC :997 + A:00 EN 077--:00 + A:00 DIN EN (VDE 088 Teil ):00-0 CSA Approval under CSA Component Acceptance Notice #, File CA 88. UL ACPL-P80: Approval under UL 77, component recognition program up to V ISO = 70 V RMS. File E. ACPL-W80: Approval pending under UL 77, component recognition program up to V ISO = 000 V RMS. File E. Table. IEC/EN/DIN EN Insulation Characteristics* (ACPL-P80 Option 00) Description Installation classification per DIN VDE 00/.89, Table for rated mains voltage 00 Vrms for rated mains voltage 0 Vrms for rated mains voltage 00 Vrms Symbol ACPL-P80 Characteristic I - IV I - III I - III ACPL-W80 Climatic Classification /00/ Pollution Degree (DIN VDE 00/.89) Maximum Working Insulation Voltage V IORM 89 0 Vpeak Input to Output Test Voltage, Method b* V IORM x.87 = V PR, 00% Production Test with tm = sec, Partial discharge < pc V PR 70 7 Vpeak Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and Sample Test with tm = 0 sec, Partial discharge < pc Unit V PR 8 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 0 sec) V IOTM Vpeak Safety-limiting values - maximum values allowed in the event of a failure. Case Temperature Input Current Output Power T S I S,INPUT P S,OUTPUT Insulation Pesistance at TS, VIO = 00 V RS >0 9 * Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/EN/ DIN EN 077--) for a detailed description of Method a and Method b partial discharge test profiles C ma mw

5 Table. Insulation and Safety Related Specifications Parameter Symbol ACPL-P80 ACPL-W80 Units Conditions Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Minimum Internal Tracking (Internal Creepage) Tracking Resistance (Comparative Tracking Index) L(0) mm Measured from input terminals to output terminals shortest distance through air. L(0) mm Measured from input terminals to output terminals shortest distance path along body mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. NA mm Measured from input terminals to output tereminals, along internal cavity. CTI >7 V DIN IEC /VDE 00 Part Isolation Group IIIa Material Group (DIN VDE 00, /89, Table ) Table. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A C Average Input Current I F(avg) 0 ma Peak Transient Input Current (< μs pulse width, 00 pps) (<00 μs pulse width, < % duty cycle) I F(tran).0 0 Reverse Input Voltage V R V Average Output Current I O ma Supply Voltage V CC 0 Output Voltage V O -0. Total Package Power Dissipation P T 0 mw Solder Reflow Temperature Profile See Reflow Thermal Profile. A ma Table. Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Power Supply Voltage V CC. 0 V Forward Input Current (ON) I F(ON) 0 ma Forward Input Voltage (OFF) V F(OFF) V Operating Temperature T A C Notes:. Derate total package power dissipation, P T, linearly above 70 C free-air temperature at a rate of. mw/ C.

6 Table. Electrical Specifications Over recommended operating conditions T A = -0 C to 00 C, V CC = +. V to 0 V, I F(ON) = ma to 0 ma, V F(OFF) = 0 V to 0.8 V, unless otherwise specified. All typicals at T A = C. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Logic Low Output Voltage V OL 0. V I OL =. ma,, 9, 0 Logic High Output Voltage ACPL-P80 ACPL-W80 Threshold Input Current Low to High Output Leakage Current (V O = V CC +0.V) V OH..7.7 V CC -. V I OH = -. ma I OH = -0. ma I OH = -. ma I FLH.. ma I OHH 00 μa V CC = V, I F = 0mA 00 μa V CC = 0 V, I F = 0mA Logic Low Supply Current I CCL.9.0 ma V CC =. V, V F = 0 V, I O = Open.0.0 ma V CC = 0 V, V F = 0 V, I O = Open,, 7, 9, 0 Logic High Supply Current I CCH.. ma V CC =. V, I F = 0 ma, I O = Open.. ma V CC = 0 V, IF = 0 ma I O = Open Logic Low Short Circuit I OSL ma V O = V CC =. V, V F =0V Output Current 0 ma V O = V CC = 0 V, V F =0V Logic High Short Circuit I OSH - ma V CC =. V, I F =ma, V O =GND Output Current -0 ma V CC = 0 V, I F =ma, V O =GND Input Forward Voltage V F..7 V T A = C, I F =ma.8 V I F =ma Input Reverse Breakdown Voltage BV R V I R = 0 μa Input Diode Temperature V F / T A.7 mv/ C I F = ma Coefficient Input Capacitance C IN 0 pf f = MHz, V F = 0 V Notes:. Duration of output short circuit time should not exceed 0 ms.. Input capacitance is measured between pin and pin.

7 Table. Switching Specifications Over recommended operating conditions T A = -0 C to 00 C, V CC = +. V to 0 V, I F(ON) = ma to 0 ma, V F(OFF) = 0 V to 0.8 V, unless otherwise specified. All typicals at T A = C. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to Logic Low Output Level Propagation Delay Time to Logic High Output Level t PHL 0 0 ns With Peaking Capacitor t PLH 0 0 ns With Peaking Capacitor,, Pulse Width Distortion t PHL - t PLH 0 ns = PWD Propagation Delay Difference Between Any Parts PDD ns Output Rise Time (0-90%) t r ns, 8 Output Fall Time (90-0%) t f 0 ns, 8 Logic High Common Mode Transient Immunity Logic Low Common Mode Transient Immunity CM H 0 kv/μs V CM = 000 V, I F =.0 ma, V CC = V, T A = C CM L 0 kv/μs V CM = 000 V, V F = 0 V, V CC = V, T A = C Table 7. Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary V ISO 70** V rms RH < 0%, t = min., Withstand Voltage* 000*** T A = C Input-Output Resistance R I-O 0 V I-O = 00 Vdc Input-Output Capacitance C I-O 0. f = MHz, V I-O = 0 Vdc * The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN Insulation Characteristics Table (if applicable). ** For all ACPL-P80 devices except Option 00 *** For ACPL-W80 and Option 00 of ACPL-P80) Notes:. The t PLH propagation delay is measured from the 0% point on the leading edge of the input pulse to the. V point on the leading edge of the output pulse. The t PHL propagation delay is measured from the 0% point on the trailing edge of the input pulse to the. V point on the trailing edge of the output pulse.. Pulse Width Distortion (PWD) is defined as t PHL - t PLH for any given device.. The difference between t PLH and t PHL between any two devices under the same test condition.. CM H is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V O >.0 V. CM L is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V O < 0.8 V.. Device considered a two-terminal device: pins, and shorted together and pins, and shorted together.. In accordance with UL 77, each optocoupler is proof tested by applying an insulation test voltage 00 V RMS for one second (leakage detection current limit, I I-O μa). ; each optocoupler with option 00 is proof tested by applying an insulation test voltage 000 V RMS for second (leakage detection current limit, I I-O μa). This test is performed before the 00% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN Insulation Characteristics Table, if applicable. 7

8 VOL - LOW LEVEL OUTPUT VOLTAGE - V V CC =./0V V F = 0V I O =.ma V CC =.V V CC = 0V T A - TEMPERATURE - C Figure. Typical Logic Low Output Voltage vs. Temperature IOH - HIGH LEVEL OUTPUT CURRENT - ma V O =.7V V O =.V V CC =.V I F = ma T A - TEMPERATURE - C Figure. Typical Logic High Output Current vs. Temperature Vo - OUTPUT VOLTAGE - V I O =.ma I O = -.ma T A = C V CC =.V 0 I F - INPUT CURRENT - ma I F - FORWARD CURRENT - ma V F - I F... V F - FORWARD VOLTAGE - V T A = C. Figure. Typical Output Voltage vs. Forward Input Current Figure. Typical Input Diode Forward Characteristic PULSE GEN. t r = t f = ns f = 00 khz 0 % DUTY CYCLE V O = V Z O = 0 INPUT MONITORING NODE R C = 0 pf SHIELD V CC OUTPUT VO MONITORING NODE * D C = pf kw V 9 W D D D THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C AND C. R IF(ON) INPUT I F OUTPUT V O 80 W ma 0 W 0 ma ALL DIODES ARE N9 OR N0. I F (ON) 0 % I F (ON) 0 ma t PLH t PHL V OH. V VOL * 0. mf BYPASS - SEE NOTE 9 Figure. Circuit for t PLH, t PHL, t r, t f 8

9 Tp - PROPAGATION DELAY - ns t PHL t PLH T A - TEMPERATURE - C Figure. Typical Propagation Delays vs. Temperature. V CC = 0V I F = 0mA Vo - OUTPUT VOLTAGE - V TA = o C IO = -.ma VCC - SUPPLY VOLTAGE - V Figure 7. Typical Logic High Output Voltage vs. Supply Voltage TP - PROPAGTION DELAY - ns tphl tplh TA = o C VCC - SUPPLY VOLTAGE - V Figure 8. Typical Propagation Delay vs. Supply Voltage IF (ma) 0 IF (ma) 0 Voh - HIGH OUTPUT VOLTAGE -V Vcc=.V IF=mA 00 C C -0 C Vol - LOW OUTPUT VOLTAGE - V C C -0 C Ioh - HIGH OUTPUT CURRENT - ma Figure 9. Voh vs Ioh Across Temperatures Iol - LOW OUTPUT CURRENT - ma Figure 0. Vol vs Iol Across Temperatures 9

10 R IN A V CC V FF + - B 0. mf SHIELD OUTPUT V O MONITORING NODE + V CM - V CM 0 V V OH OUTPUT V O V CM (PEAK) SWITCH AT A: I F = ma V O (MIN.) SWITCH AT B: V F = 0 V V O (MAX.) V OL Figure. Test Circuit for Common Mode Transient Immunity and Typical Waveforms For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright Avago Technologies Limited. All rights reserved. Obsoletes AV0-0EN AV0-0EN - July 0, 00

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