NTD80N02T4G. Power MOSFET 80 Amps, 24 Volts. N Channel DPAK
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1 NTD8N2 Power MOSFET 8 Amps, 2 Volts NChannel Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. Features PbFree Package May be Available. The GSuffix Denotes a PbFree Lead Finish Typical Applications Power Supplies Converters Power Motor Controls Bridge Circuits MAXIMUM RATINGS ( unless otherwise noted) Rating Symbol Value Unit DraintoSource Voltage VDSS 2 Vdc GatetoSource Voltage Continuous VGS ±2 Vdc Drain Current TC = 25 C ID 8* Adc Drain Current Single Pulse (tp = µs) IDM 2 Total Power TC = 25 C PD 75 Watts Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting (VDD = 2 Vdc, VGS = Vdc, IL = 7 Apk, L = 5. mh, RG = 25 Ω) Thermal Resistance JunctiontoCase JunctiontoAmbient (Note ) JunctiontoAmbient (Note 2) Maximum Lead Temperature for Soldering Purposes, /8 from case for seconds TJ, Tstg 55 to 5 C EAS 733 mj RθJC RθJA RθJA C/W TL 26 C. When surface mounted to an FR board using pad size, (Cu Area.27 in2). 2. When surface mounted to an FR board using the minimum recommended pad size, (Cu Area.2 in2). *Chip current capability limited by package. G NChannel D S Gate 2 3 CASE 369AA (Bend Lead) STYLE 2 Drain YWW 8 N2 2 Drain Y WW 8N2 V(BR)DSS RDS(on) TYP 2 V 5. m MARKING DIAGRAMS & PIN ASSIGNMENTS 3 Source Gate = Year = Work Week = Device Code 2 3 Drain 2 Drain CASE 369D (Straight Lead) STYLE 2 YWW 8 N2 ORDERING INFORMATION ID MAX 8 A 3 Source Device Package Shipping NTD8N2 75 Units/Rail NTD8N2T 25 / Tape & Reel NTD8N2TG NTD8N2 PbFree Straight Lead 25 / Tape & Reel 75 Units/Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. Semiconductor Components Industries, LLC, 23 December, 23 Rev. 2 Publication Order Number: NTD8N2/D
2 NTD8N2 ELECTRICAL CHARACTERISTICS ( unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 3) (VGS = Vdc, ID = 25 µadc) Positive Temperature Coefficient Zero Gate Voltage Drain Current (VGS = Vdc, VDS = 2 Vdc) (VGS = Vdc, VDS = 2 Vdc, ) V(BR)DSS GateBody Leakage Current (VGS = ±2 Vdc, VDS = Vdc) IGSS ± nadc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 25 µadc) Negative Threshold Temperature Coefficient Static DraintoSource OnResistance (Note 3) (VGS = Vdc, ID = 8 Adc) (VGS =.5 Vdc, ID = Adc) (VGS = Vdc, ID = 2 Adc) (VGS =.5 Vdc, ID = 2 Adc) IDSS VGS(th) RDS(on) Forward Transconductance (VDS = 5 Vdc, ID = Adc) (Note 3) gfs 2 Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note ) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate GaeCharge age SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 2 Adc, VGS = Vdc) (Note 3) (IS = Adc, VGS = Vdc) (IS = 2 Adc, VGS = Vdc, TJ = 5 C) Reverse e Recovery e Time (IS = 2 Adc, VGS = Vdc, dis/dt = A/µs) (Note 3) Vdc mv/ C µadc Vdc mv/ C mω Ciss 225 pf (VDS = 2 Vdc, VGS = V, Coss 9 f =. MHz) Crss =5Vdc td(on) 7 ns (VGS.5 Vdc, tr 67 VDD = 2 Vdc, ID = 2 Adc, td(off) 28 RG = 2.5 Ω) tf QT 3 nc (VGS =.5 Vdc, ID = 2 Adc, Q 7. VDS = 2 Vdc) (Note 3) Q2 8 VSD Vdc trr 38 ns ta 2 tb 8 Reverse Recovery Stored Charge Qrr.36 µc 3. Pulse Test: Pulse Width 3 µs, Duty Cycle 2%.. Switching characteristics are independent of operating junction temperatures. 2
3 NTD8N2 ID, DRAIN CURRENT (AMPS) V 8 V 6.5 V. V.6 V.8 V 5 V 5.2 V 6 V VDS, DRAINTOSOURCE VOLTAGE (V) Figure. OnRegion Characteristics.2 V V 3.8 V 3.6 V 3. V 3.2 V VGS = 3. V ID, DRAIN CURRENT (AMPS) 6 5 VDS 2 V TJ = 55 C VGS, GATETOSOURCE VOLTAGE (V) Figure 2. Transfer Characteristics RDS(on), DRAINTOSOURCE RESISTANCE (Ω) ID = A VGS, GATETOSOURCE VOLTAGE (V) RDS(on), DRAINTOSOURCE RESISTANCE (Ω) VGS =.5 V VGS = V ID, DRAIN CURRENT (A) Figure 3. OnResistance versus GateToSource Voltage Figure. OnResistance versus Drain Current and Gate Voltage RDS(on), DRAINTOSOURCE RESISTANCE TJ, JUNCTION TEMPERATURE ( C) ID = 8 A VDS =.5 V ID = 8 A VDS = V IDSS, LEAKAGE (na).. VGS = V TJ = C VDS, DRAINTOSOURCE VOLTAGE (V) Figure 5. OnResistance Variation with Temperature Figure 6. DrainToSource Leakage Current versus Voltage 3
4 NTD8N2 C, CAPACITANCE (pf) Ciss Coss Crss VGS = V VGS VDS GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (V) Figure 7. Capacitance Variation VGS, GATETOSOURCE VOLTAGE (V) 8 6 VD Q Q2 QT VGS 8 2 ID =. A Qg, TOTAL GATE CHARGE (nc) Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge VDS, DRAINTOSOURCE VOLTAGE (V) t, TIME (ns) VDD = 2 V ID = 2 A VGS = V tr tf td(off) td(on) IS, SOURCE CURRENT (AMPS) VGS = V RG, GATE RESISTANCE (Ω) Figure 9. Resistive Switching Time Variation versus Gate Resistance VSD, SOURCETODRAIN VOLTAGE (V) Figure. Diode Forward Voltage versus Current
5 NTD8N2 ID, DRAIN CURRENT (AMPS). VGS = V SINGLE PULSE TC = 25 C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT VDS, DRAINTOSOURCE VOLTAGE (VOLTS) s ms ms dc IS tp di/dt ta trr tb.25 IS IS TIME Figure. Maximum Rated Forward Biased Safe Operating Area Figure 2. Diode Reverse Recovery Waveform Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE. DUTY CYCLE D =.5 MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT P(pk) t t 2 DUTY CYCLE, D = t/t2 Figure 3. Thermal Response Various Duty Cycles RθJA(t) = r(t) RθJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t TJ(pk) TA = P(pk) RθJA(t) SINGLE PULSE. E5 E E3 E2 E E+ E+ E+2 E+3 t, TIME (seconds) 5
6 NTD8N2 PACKAGE DIMENSIONS CASE 369AA ISSUE O V S F B R 2 3 L A J C D 2 PL.3 (.5) M T T SEATING PLANE E U Z NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D E F J L.9 BSC 2.29 BSC R S U.2.5 V Z STYLE 2: PIN. GATE 2. DRAIN 3. SOURCE. DRAIN SOLDERING FOOTPRINT* SCALE 3: mm inches Figure. *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6
7 NTD8N2 CASE 369D ISSUE B V B R C E NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, CONTROLLING DIMENSION: INCH. S T SEATING PLANE F 2 3 G A K D 3 PL J.3 (.5) M T H Z INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D E F G.9 BSC 2.29 BSC H J K R S V Z STYLE 2: PIN. GATE 2. DRAIN 3. SOURCE. DRAIN 7
8 NTD8N2 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 827 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 29 Kamimeguro, Meguroku, Tokyo, Japan 535 Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. NTD8N2/D
N Channel Enhancement Mode Silicon Gate
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