Digital Dual Mixer Time Difference: Phase noise & stability

Transcription

1 1 Author: Mattia Rizzi 03/02/2017 Digital Dual Mixer Time Difference: Phase noise & stability Abstract: The scope of the following document is to evaluate the phase noise and stability floor of the Digital Dual Mixer Time Difference (DDMTD) phase detector in the WR PLL architecture. The measurement has been done on the WR Switch (Virtex-6) The effect of the DDMTD common clock noise on the phase noise floor is modelled mathematically and verified experimentally. The experimental results show a phase noise floor of -108 dbc/hz (10MHz carrier) combined with a flicker noise (1/f noise) of -100dBc/Hz at 1Hz (flicker corner frequency at 5Hz). The flicker noise has been traced to the LVDS input clock buffer of the FPGA. The DDMTD is able to provide 4 ps single-shot precision (1 σ) with a measurement rate up to 3.8 khz The stability of the DDMTD has been characterized with Modified Allan Deviation (MDEV) and Allan Deviation (ADEV). The results are: MDEV 4E-13 at Tau=1s for Equivalent Noise BW of 50Hz, ADEV, is depending on the Equivalent Noise Bandwidth, o 4E-13 at Tau=1s for Equivalent Noise BW of 0.5Hz and o 1E-12 at Tau=1s for Equivalent Noise BW of 50Hz.

2 2 Contents 1. Introduction: the DMTD DDMTD DDMTD in the WR PLL architecture Noise floor of the (D)DMTD Stability of the counter used in the WR PLL Noise of the common clock...8 DMTD common clock noise model Experimental setup Input clock quality (phase noise and stability) Software modifications Experimental workflow Experiments list Experiment results Beat frequency khz (N=14), internal DDMTD common clock Comments on the results Beat frequency khz (N=16), internal DDMTD common clock Comments on the results Beat frequency khz (N=14), external DDMTD common clock Comments on the results Beat frequency khz (N=14), internal DDMTD common clock, single clock Comments on the results Beat frequency khz (N=14), internal DDMTD common clock, 16*2pi delay Comments on the results Final remarks Improvements tried Suggestions References... 38

3 3 1. Introduction: the DMTD The Digital Dual Mixer Time Difference (DDMTD) is the digital version of the Dual Mixer Time Difference (DMTD), invented by D. Allan in the late 70s [1]. The DMTD is very useful to characterize clock stability of two clock signals (clk 1 and clk 2 ) having (almost) the same nominal frequency v 0. Using a common offset clock clk c, the DMTD performs an analog mixing to down convert the two input clocks to an intermediate frequency (heterodyne demodulation). After low-pass filtering, the resulting signals can be used to estimate the phase difference between the two clock signals. clk 1 = sin clk C = sin clk 2 = sin 1 (t)) C (t)) 2 (t)) X X Low Pass Filter Low Pass Filter clk 1 DMTD = sin Time Interval Counter clk 2 DMTD = sin 1 DMTD (t)) 2 DMTD (t)) Figure 1 DMTD scheme Let s assume that the two input clocks signals, clk 1 and clk 2, have the following phase functions 1 (t) = 2πv 0 t (1.1) 2 (t) = 2πv 0 t offset (1.2) where v 0 is the nominal frequency (respect to a frequency standard) and offset is the phase offset (in radians) of clk2 with respect to clk1 (i.e. it is positive when the edge of clk2 succeeds that o clk1). The time difference between the two clocks can be calculated as follows t = offset (1.3) 2πv 0 If the common clock clk C has the following phase function C (t) = 2π(v 0 v b )t where v b is defined as the beating frequency, then after the mixing and low-pass filtering, the output clocks clk 1 DMTD and clk 2 DMTD have the following phase functions 1 DMTD (t) = 1 (t) C (t) = 2πv b t (1.4) 2 DMTD (t) = 2 (t) C (t) = 2πv b t offset (1.5) The two input clocks signals, defined in formula (1.1) and (1.2), are translated into clock signals of lower frequency while preserving their phase offset offset expressed in radians, as shown in (1.4) and (1.5) The counter can be used to measure the time difference between the edges of clk 1 DMTD and clk 2 DMTD. This results in measuring the phase offset between the two output clocks, clk 1 DMTD and clk 2 DMTD, expressed in time, time-delay t DMTD.

4 4 t DMTD = offset 2πv b (1.6) Since the phase offset in radians is preserved, the time-difference measured between the output clock signals (i.e. after the DMTD, t DMTD ) can be translated to the time-difference between the input clock signals (i.e. before the DMTD, t). It can be observed that the term offset is present in both formulas (1.3) and (1.6), thus: offset = 2πv 0 t = t DMTD 2πv b = offset t = t DMTD v b v 0 (1.7) Formula (1.7) converts the measured output phase offset t DMTD into the phase offset at the input of the DMTD. The v 0 v b is the zooming factor of the DMTD. 1.1 DDMTD The DDMTD uses digital mixing to produce output clock signals of lower frequency than that of the input clock signals. The operation of DDMTD is explained in Figure 2. n-1 n n+1 x in clk 1 PLL clk D Q 1 clk DDMTD DMTD x out m n n+1 n+2 clk 2 D Q clk 2 DMTD m m+1 Counter N N+1 N+2 N+3 N+4 N+5 tag tag Figure 2 DDMTD scheme The input clock signals are sampled with D-type flip-flops that are clocked with an offset clock signal, clk DDMTD, generated from one of the inputs. The frequency of the offset clock signal, f DDMTD, is very close to that of the input clock signals, f IN, and is specified as follows: f DDMTD = 2N 2 N + 1 f IN where N is an implementation-specific value that is 14 in the WR Switch. The sampling operation performed by the flip-flops is similar to analog mixing and low-pass filtering. Thus, the output clock signals, clk 1 DMTD and clk 2 DMTD, are of a frequency that is proportional to the frequency of the input clock signals. The phase, expressed in radians, between the input signals is equal to that between the output signals. Therefore, the time difference between the edges of the input and output clock signals is proportional and can be expressed using formula (1.7). A detailed description of the DDMTD architecture can be found in [2].

5 5 2. DDMTD in the WR PLL architecture SoftPLL is a software implementation of the WR PLL that is executed in an embedded CPU and uses the DDMTD. The architecture of the SoftPLL is depicted in Figure 3. It uses a DDMTD implemented in a Field Programmable Gate Array (FPGA) to compare the local PTP clock signal to an input clock signal that can be either: the L1 rx clock signal recovered at the slave port, or the clock signal coming from an external reference. The outputs of the DDMTD are lower-frequency clock signals, as explained before. The rising edges of these signals are timestamped using a time counter incremented by the DDMTD clock signal, clk DDMTD. This counter is free-running and has no epoch. The timestamps provided by this counter are called phase-tags. They are fed into the Soft PLL that is a software implementation of a Proportional-Integral (PI) controller running in an embedded CPU inside the FPGA. The controller steers two Voltage-Controlled Crystal Oscillators (VCXO): 1. FRETHE025 generates the DDMTD clock signal, 2. VM53S3 generates local PTP clock signal. Figure 3 depicts a simplified block diagram of the WR PLL, which actually consists of two PLLs: Helper and Main. Figure 3 WR PLL scheme The Helper PLL controls the DDMTD clock signal. This PLL works by comparing the difference between subsequent phase-tags to the ideal period of the DDMTD clock signal. The Main PLL controls the local PTP clock signal that is a copy of the L1 rx clock signal (or the ext. ref clock signal in GrandMaster mode), phase shifted by a programmable setpoint that is provided by the WR PTP. This

6 6 PLL works by comparing the phase-tags of the L1 rx clock signal (or the ext. ref clock signal in GrandMaster mode) to the phase-tags of the local PTP clock signal, corrected for the setpoint. Any change of the setpoint value is applied with an LSB-step increment. The WR switches use a 62.5MHz clock signal that determines a number of characteristics of the SoftPLL. The SoftPLL that receives a 62.5MHz input signal produces a DDMTD clock signal of MHz. The downconverted clock signals produced by the DDMTD have a frequency of 3.814kHz. Since each rising edge of these clock signals is timestamped, the phase-tags are provided to the SoftPLL at the DDMTD frequency. This is indeed the sample rate of the SoftPLL and so its Nyquist frequency is 1.9kHz. With the default parameters of the SoftPLL (WR Switch v4.2, WRPC v3.0), the resolution of its phase-tags is 976 fs and its bandwidth is 30Hz for both helper PLL and Main PLL. The SoftPLL determines the characteristics of the frequency transfer through a WR switch. In fact, the implementation of the WR PLL inside the WR Switch uses a DDMTD offset frequency that is not 3.814kHz below the 62.5MHz carrier, but above it, i.e MHz. Moreover, the clk DDMTD is sampled by clk_1 and clk_2, which is opposite to the architecture presented in Fig 2. The reason of this choice lies in the routing of the WRS FPGA design. It has no effect on the theoretical analysis and does not change the experimental results. For the sake of clarity, the DDMTD is modelled as shown in Figure 2, since it s the actual implementation on a WR End Node (e.g. SPEC).

7 7 3 Noise floor of the (D)DMTD The noise floor of an analog DMTD depends on a number of factors, e.g.: Noise of the input stages (amplifiers) Noise of the analog multipliers and mixers Noise of common clock Stability of the counter The DDMTD has the same kind of noise sources, translated into the digital electronics: Noise of the LVDS clock input stages Noise of the D-type Flip Flop (meta-stability window, thermal noise, ) Noise of common clock Stability of the counter 3.1 Stability of the counter used in the WR PLL The counter is incremented by the DMTD common clock. The maximum time-difference measured by the counter depends on the maximum setpoint value provided to the Main PLL by the PTP daemon (PPSi). The maximum value of the setpoint is equal to one period of the 62.5MHz clock input (16 ns). The maximum timedifference measured by the counter is 262 µs as a result of the zooming effect of the DDMTD (formula 1.7). The zooming effect of the DDMTD translates a 16 ns time-difference into a 262 us time-difference (1/3.814kHz). If the clock signal that drives the counter has a frequency transient error of 0.1 ppm during the measurement time of 262 µs, a very high frequency change (the Allan Deviation at 1ms is ppm, as shown in Figure 4), the worst-case measurement error is equal to 16ns*0.1ppm; it is far below the DDMTD resolution. The longterm accuracy is preserved since the counter clock is phase-locked to the L1 rx clock/ext ref. clock signal. Figure 4 Allan Deviation of the DDMTD common clock

8 8 3.2 Noise of the common clock The original paper of Allan describing the DMTD provides an estimation of the ADEV of the DMTD output due to the common clock stability [1]. This estimate is made without a proof. The author of [3] evaluated the influence of the common clock [3] by providing an estimation of the Allan Deviation (ADEV) due to the common clock instability. However, we re interested in the phase noise rather than the effect on the measured ADEV. For this reason, a noise model has been realized and proven. Since we re interested on the additive phase noise of the common clock on the DDMTD phase measurement, we need to model the DMTD as a phase detector. The characterization of the additive noise of a phase detector can be done using two copies of the same clock signal, delayed from zero to up to one clock period with respect to each other. The following chapter analyzes the phase noise floor of the DMTD due to the common clock phase noise. DMTD common clock noise model We can model the input clock signals clk1 and clk2 using 1 (t) and 2 (t ), which are the phase functions of these clock signals (as shown in Figure 1), defined as 1 (t) = 2πv 0 t + φ 1 (t) 2 (t) = 1 (t t) = 2πv 0 t + φ 1 (t t) offset (3.1) where v 0 is the nominal frequency (with respect to a frequency standard) and φ 1 (t) is the zero-mean phase fluctuation (phase noise) of the input clock signal with respect to a frequency standard. The power spectrum density (PSD) of φ 1 (t) is defined as S φ1 (f), which is the one-sided PSD of the φ 1 (t) stochastic process. The offset parameter is the phase offset of clk1 with respect to clk2, which we can choose arbitrary. The relation between offset and t is defined by where offset can be from 0 rad up to 2π rad. The DMTD common clock has a phase function C (t) defined as t = offset 2πv 0 (3.2) C (t) = 2π(v 0 v b )t + φ C (t) (3.3) where v b is the beating rate and φ C (t) is the phase fluctuation of the common clock (with respect to a frequency standard), having zero-mean and S φc (f) as the one-sided PSD of the φ C (t) stochastic process. The heterodyne demodulation of the mixers translates the two input clock signals into a down converted clock signals, as follows: 1 DMTD (t) = 1 (t) C (t) = 2πv b t + φ 1 (t) φ C (t) (3.4) 2 DMTD (t) = 2 (t) C (t) = 2πv b t + φ 1 (t t) offset φ C (t) (3.5)

9 9 The counter measures the phase time-difference between the two clock signals, 1 DMTD (t) and 2 DMTD (t), computing the phase time-difference signal D (t), as follows D (t) = 1 DMTD (t) 2 DMTD (t) = offset + (φ 1 (t) φ 1 (t t)) + (φ C (t) φ C (t)) (3.6) The formula (3.6) may suggest that the effect of the common clock phase errorφ C (t) is cancelled for any offset, however a careful reader would notice that this is not true. The underlining assumption of the formula (3.6) is that we can measure, with the counter, the instantaneous phase error in any time t. A digital counter can measure the phase functions 1 DMTD and 2 DMTD only when the functions are crossing a multiple of 2π. If a offset (equal to a phase time-difference of t) is applied in one of the two input clocks, it takes a time delay of t DMTD to see the transition of both signal. Most notably the time delay is equal to the delay t with the zooming effect of the DMTD, i.e.: t DMTD = v 0 v b t = offset 2πv b (3.7) Let s say that 1 DMTD cross a multiple of 2π in the time instant t = t, as shown in formula (3.8). We would expect that 2 DMTD transitions at time t = t + t DMTD due to the input clock phase offset offset (see formula (3.7)). If we apply t = t + t DMTD to the formula (3.5) the result is formula (3.9) 1 DMTD (t ) = 2πv b t + φ 1 (t ) φ C (t ) = k 2π k N (3.8) 2 DMTD (t + t DMTD ) = 2πv b (t + t DMTD ) + φ 1 (t + t DMTD t) offset φ C (t + t DMTD ) = 2πv b t + offset + φ 1 (t + t DMTD t) offset φ C (t + t DMTD ) = 2πv b t + φ 1 (t + t DMTD t) φ C (t + t DMTD ) (3.9) Formula (3.9) shows that the counter measures the correct amount of time t DMTD (that can be translated into the offset using (3.7)) if and only if φ 1 (t + t DMTD t) φ C (t + t DMTD ) = φ 1 (t ) φ C (t ). Since the common clock phase fluctuation φ C may vary between t and t + t DMTD, the 2 DMTD function transitions in a slightly different time t DMTD. We can derive the t DMTD using formula (3.10), as follows After some trivial substitutions we can rewrite formula (3.10) as follows DMTD 2 (t + t DMTD ) = DMTD 1 (t ) (3.10) t DMTD = t DMTD + (φ 1(t + t DMTD t) φ 1 (t )) + (φ C (t + t DMTD t) φ C (t )) (3.11) 2πv b The formula (3.11) gives us the true time-difference measured by the counter due to the phase fluctuation of φ 1 and φ C. The last step is to convert the time-difference measured by the counter into the input timedifference (i.e. the phase between the input clocks), using formula (1.7). t = t + (φ 1(t + t DMTD t) φ 1 (t )) + (φ C (t + t DMTD t) φ C (t )) = t + x 2πv e (3.12) 0 Formula (3.12) is the estimation of the time-difference measurement performed by the DMTD, where x e is the time error (measured in seconds) of the DMTD estimation.

10 10 The x e term is a realization of a more generic function that represents the measurement error of DDMTD and can be treated as a time-continuous function being sampled by the measurement system (DMTD + counter). x e (t, t, t DMTD ) = (φ 1(t + t DMTD t) φ 1 (t)) + (φ C (t + t DMTD t) φ C (t)) (3.13) 2πv 0 Formula (3.13) is a time error function which depends on the stochastic process φ 1 and, φ C. Unfortunately, Formula (3.13) is not a in a closed form expression, since t DMTD is in both sides of Formula (3.11). Knowing that t = t + x e ( ) and E[x e ( )] = 0, if t VAR[x e ( )] ] then t DMTD t DMTD therefore process x e can be estimated as x e (t, t, t DMTD ) x e (t, t, t DMTD ) = (φ 1(t + t DMTD t) φ 1 (t)) + (φ C (t + t DMTD t) φ C (t)) 2πv 0 x e ( ) can also be converted, without loss of generality, to a phase noise function of a generic carrier frequency v, which can be different from v 0 For sake of clarity, from now on, we set v v 0 φ e (t, t, t DMTD ) = x e (t, t, t DMTD ) 2πv (3.14) φ e (t, t, t DMTD ) = (φ 1 (t + t DMTD t) φ 1 (t )) + (φ C (t + t DMTD t) φ C (t)) = φ 1DIFF (t, t, t DMTD ) + φ CDIFF (t, t, t DMTD ) (3.15) In order to get the phase noise floor of the DMTD, the last step is to convert (3.15) into its PSD function. Both φ 1DIFF and φ CDIFF stochastic processes are the result of a Linear Time Invariant (LTI) system having an impulse response function h(t) as follows: The PSDs of both processes are φ CDIFF (t, t, t DMTD ) = φ C (t) h(t) φ 1DIFF (t, t, t DMTD ) = φ 1 (t) h(t) h(t) = δ(t + t DMTD t) δ(t) S 1 DIFF = S 1(f) H(f) 2 S C DIFF = S C(f) H(f) 2 H(f) 2 = e i2πf( tdmtd t) 1 2 = 4 sin 2 (πf( t DMTD t)) If φ 1 and φ C are uncorrelated stochastic processes, then also φ 1DIFF and φ CDIFF are uncorrelated and thus the final PSD of φ e is

11 11 S e = S 1 (f) 4 sin 2 (πf( t DMTD t)) + S C (f) 4 sin 2 (πf( t DMTD t)) (3.16) Formula (3.16) is the estimation of DMTD noise floor due to the noise contribution of the common clock signal noise and of the noise of the input clock signals. In order to be used in a real scenario, some simplifications can be applied. The first term of the (3.16) refers to the input clock signal noise, which is typically better than the common clock noise, so it can be neglected. The t DMTD t term can be approximated as t DMTD t t DMTD, since t is very small compared to t DMTD (see (1.7)). Formula (3.16) is derived under the t VAR[x e ( )] assumption. The approximation is valid in White Rabbit in certain scenarios. Following the example given in paragraph 3.2, if the common clock has a frequency transient change of 0.1ppm during the measurement time of 262us (the beating rate), then x e can vary as much as 26 ps. For values of t above several nanoseconds the approximation is legit. The simplifications adopted lead to the final formula (3.17) e 2 DMTD C 4 S f S f sin f t (3.17) Formula (3.17) is valid only when φ 1 and φ C are uncorrelated, however C is typically derived from 1 using a PLL (as in WR). We can rewrite φ C as the combination of both: the phase noise φ 1 copied to the output by the PLL (scaled by the zooming factor), and the uncorrelated noise φ PLL generated by the PLL itself. The result of the calculations, after the simplifications, is still the formula (3.17). L e (f) = 10 log 10 S e (f) 2 (3.18) Formula (3.18) is the phase noise floor of the DMTD in accordance with IEEE standard 1139 about phase noise measurements. It s worth saying that, since x e ( ) is being sampled by the DMTD with Nyquist frequency v b /2, the phase noise spectrum of the common clock signal that exceeds v b /2 is folding into the Nyquist bandwidth of the DMTD.

12 12 4 Experimental setup We measure the noise introduced by the DDMTD-based phase detector using the following experimental setup (depicted in Figure 5): Symmetricom Cs time reference Microsemi 3120A - phase noise analyzer and stability analyzer, with Cs4000 as the time reference. It is used to measure the phase noise/stability of the CLK2 output (10MHz) of the WR Switch E5052B - phase noise analyzer, with Cs4000 as the time reference (narrow loop bandwidth). It is used to measure the DDMTD clock offset phase noise AD Evaluation Kit [4] - it is used to synthetize a clean 62.5MHz clock, WR SMA board [5] - it provides 4 LVDS clock input/output to the WRS PCB v3.4 WR switch PCB v3.4 E5052B Microsemi 3120A Symmetricom Cs4000 CLK2 DMTD offset clk WR Switch PCB v3.4 WRS SMA board AD PCBZ Eval Kit Figure 5 Experimental setup The characterization of the noise introduced by the DDMTD is done by post-processing the phase-tags collected when the DDMTD is measuring the phase of two copy of the same clock. If the supplied clocks have low phase noise, the resulting noise from post-processing is the noise introduced by the DDMTD, its noise floor. The connections used to provide the two 62.5MHz clocks to the WR PCB [6] are the following: Pin 21 and 23 of the J3 connector (LVDS connection), using WR SMA board (CLK_IN1) Pin 13 and 15 of the J3 connector (LVDS connection), using WR SMA board (CLK_IN3) Additionally, an output clock is used to characterize the clock quality connection, using Pin 1 and 3 of the J3 connector (LVDS connection), using WR SMA board (CLK_OUT)

13 Input clock quality (phase noise and stability) The clock connections of the experimental setup depicted in Figure 5 need to be characterized in order to exclude any coupling issue from the experimental data. The clock connection quality has been characterized using the following setups:. Setup 1. Setup 2. Characterization of the AD Evaluation kit board, and Characterization of the clock connection to the FPGA (running a full design). A low-noise clock distribution board (based on the LTC6954 clock distribution chip) is used to characterize the clock quality connection. The additive phase noise of LTC6954 was measured and proven negligible with respect to the clock quality of AD Microsemi 3120A Symmetricom Cs4000 AD PCBZ Eval Kit LVDS 62.5MHz LTC6954 LVPECL E5052B Figure 6 Experimental clock characterization of AD phase noise (Setup 1) Figure 6 shows the experimental setup to characterize the phase noise of the AD Evaluation board. The experimental results are depicted in Figure 8Figure 8 and Table 1. The phase noise measured constitutes the noise floor of the experimental setup. WR Switch PCB v3.4 Microsemi 3120A Symmetricom Cs4000 AD PCBZ Eval Kit LVDS 62.5MHz WRS SMA board LVDS 62.5MHz LTC6954 LVPECL E5052B Figure 7 Experimental clock connection characterization (Setup 2) Figure 7 shows the experimental setup to characterize the differential connection (LVDS) used to provide the required clock to the FPGA. To measure the connection quality and the clock-tree noise of the FPGA, the same input clock signal is routed to an output pin of the FPGA using the ODDR primitive. The LVDS output clock is fed into the LTC6954 board. One of the board s LVPECL AC output (the unused is 50ohm terminated) is used to measure the phase noise with both Microsemi 3120A (using a divider value of 2) and E5052B (no divider). Figure 8 shows the additive phase noise measured by 3120A (scaled to an equivalent carrier of 10 MHz). Figure 9 shows the same plot measured by E5052B but with a larger bandwidth. The integrated jitter in Figure 9, from 100 khz to 20MHz, varies with different binary synthesis, as depicted in Table 1. The most affected region is between 5 MHz and 20MHz, which seems related to the internal clock routing noise. The binary dependency jitter has not impacted the measured DDMTD noise floor. The phase noise between 700kHz and 2MHs is due to the DC/DC power supply.

14 14 Table 1 Jitter Measurements Trace AD9516 Eval board Output from fpga (full design) 1Hz- 100kHz (measured ) Jitter RMS (s) 100kHz-20MHz (measured) 1Hz 20MHz (calculated) 1.0ps 700fs 1.2ps 1.3ps 3-7ps (depends on the synthesis) 3-7ps (depends on the synthesis) Figure 8 Additive phase noise of the AD Evaluation board (purple) and of the output clock from the FPGA (blue), the phase noise plot has been down-shifted to an equivalent carrier of 10MHz. Measured with 3120A.

15 Evaluation kit Clock from FPGA (full design) -130 L(f) (dbc/hz) Frequency (Hz) Figure 9 Absolute phase noise of the AD Evaluation board (purple) and of the output clock from the FPGA (blue), the phase noise plot has been down-shifted to an equivalent carrier of 10MHz. Measured with E5052B Figure 10 Modified Allan Deviation Equivalent Noise Bandwidth 50Hz

16 16 Figure 11 Allan Deviation Equivalent Noise Bandwidth 50Hz 4.2 Software modifications In order to obtain the phase-tags from the two SoftPLL input channels, the gateware of the WR Switch is modified introducing two additional DDMTD blocks. The WR PLL (SoftPLL) code is modified to take one of the two input clocks signals as the reference (to control the local oscillator, VM53S3). The reason is to get an experimental validation of the noise floor using a modified WR PLL (SoftPLL) that has a large bandwidth (special care is taken to avoid the LO low-frequency noise leaking, using a large integral gain of the PI controller, see [6]). The debug interface of the WR PLL is modified to output the phase-tags to the debug FIFO interface. These phase-tags are then processed to get the phase noise floor calculated with an equivalent carrier of 10MHz.

17 Experimental workflow The following experimental procedure is adopted: Configure the switch in the GrandMaster mode Tune the AD9516 PCBZ Evaluation kit board to the external reference (PLL bandwidth 70 khz) Wait 1 hour for the WR switch to warm up Measure the phase noise of the DDMTD offset clock with E5052B (see Figure 5) Start acquisition of the phase-tags (runtime 30 minutes) Measure the phase noise of the CLK2 (10MHz) output of the switch with Microsemi 3120A, at the same time as starting acquisition of the phase-tags (see Figure 5) The collected phase-tags are post-processed using a MATLAB scripts to calculate the phase noise floor. The acquired phase noise of the DDMTD offset clock signal is used to calculate the common clock signal noise floor using formula (3.18). In order to get stability information, the time error is low-pass filtered using different frequencies, emulating the low-pass filter of an acquisition instrument (Equivalent Noise Bandwidth). In order to get a offset = 0 (best case) we use the same cable length for both input clocks. To obtain a offset = 2π (worst case) a trick is used. The trick is to obtain a phase offset (multiple of 2pi) during postprocessing of the phase-tags instead of physically phase-shifting the input clock signals. In this trick, we use the same cable length for both input clocks. We then obtain the offset = 2π by taking the difference of tags of subsequent cycles, instead of taking the difference of the tags in the same DMTD cycle, which is the usual case. 4.4 Experiments list The DDMTD noise floor is evaluated using the following setups: 1. DDMTD beating frequency of khz (N=14, default value), internal DDMTD common clock, phase offset of 0pi and 2π, 2 clocks input. This is the default setting of the WR Switch 2. DDMTD beating frequency of khz (N=16), internal DDMTD common clock, phase difference of 0pi and 2π, 2 clocks input. 3. DDMTD beating frequency of khz (N=14), external DDMTD common clock, phase difference of 0pi and 2π, 2 clocks input 4. DDMTD beating frequency of khz (N=14), internal DDMTD common clock, phase difference of 0pi, π i and 2π i, 1 clock input. Checking the effect of LVDS input stage 5. DDMTD beating frequency of khz (N=14, default value), internal DDMTD common clock, 16 pi phase difference, 2 clocks input. Verifying the formula (3.18) with a big delay.

18 18 5 Experiment results The following chapters include the results of the experiments with a short comment at the end of each chapter. The DDMTD phase noise floor is presented for a phase-difference of 0 radians and 2π. The stability of the DDMTD is presented only for a phase-difference of 2π since it s the same for both cases (averaging time above 0.1s). In each experiment, the phase noise and the stability of the controlled oscillator (VM53S3) is measured by Microsemi 3120A. The reader will find that the WR PLL (SoftPLL) transfers the (in)stability of the DDMTD phase detector to the controlled oscillator without adding considerable phase noise / instability. The effect of the common clock phase noise on the DDMTD noise floor (as estimated by Formula (3.17)) is presented for a phase-difference of 2π only, where the t VAR[x e ( )] assumption holds. 5.1 Beat frequency khz (N=14), internal DDMTD common clock The experiment is performed using two clock inputs cables (LVDS coupled) into the WR Switch, as depicted in Figure 4. The phase-tags are processed for a 0 pi phase offset and 2 pi phase offset (equivalent to a t of 16ns). Table 3 shows the RMS time-error (jitter) calculated from the phase-tags, while Figure 12 shows the PSD of the time-error (blue trace). Since the jitter is about 4 ps RMS, t VAR[x e ( )] holds only for t greater than 1 ns. Table 3 confirm the very high precision of the DDMTD, 4 ps RMS single shot precision. Table 2 Jitter with 0 pi delay Integration BW Jitter RMS (ps) Full BW (0-1900Hz) 4.0 ps 0 to 1Hz 0.6ps Table 3 Jitter with 2pi delay (16 ns) Integration BW Jitter RMS (ps) Full BW (0-1900Hz) 4.1 ps 0 to 1Hz 0.6 ps DDMTD noise floor DDMTD common clk noise (est.) -85 L(f) (dbc/hz) Frquency offset (Hz) Figure 12 Phase noise floor of the DDMTD without delay (equivalent to a 10MHz carrier) calculated from the tags. The red curve is suppressed since t VAR[x e ( )] is not valid

19 DDMTD noise floor DDMTD common clk noise (est.) -90 L(f) (dbc/hz) Frquency offset (Hz) Figure 13 Phase noise floor of the DDMTD (blue) with 2pi delay (equivalent to a 10MHz carrier) calculated from the tags, additive noise of the common clock noise on the noise floor (red) Figure 14 Additive phase noise measured by 3120A on the CLK2 output of the switch

20 ADEV 0.5Hz ENBW ADEV 1Hz ENBW ADEV 5Hz ENBW ADEV 50Hz ENBW ADEV (s) Figure 15 Allan deviation calculated from the DDMTD tags Figure 16 Modified Allan deviation calculated from the DDMTD tags (Equivalent noise BW 50Hz)

21 21 Figure 17 Allan deviation measured by 3120A on the CLK2 output of the switch Figure 18 Modified Allan deviation measured by 3120A on the CLK2 output of the switch

22 22 Figure 19 DDMTD common clock phase noise measured with E5052B Comments on the results Figure 12 and Figure 13 shows that the noise of the DDMTD comprises flicker noise (1/f noise) and white phase noise. The flicker noise is very common in electronics and it s typically due to transistor noise. The white noise can be traced to thermal noise, DFF meta-stability window and/or to phase noise down-conversion due to aliasing. Figure 13 shows that the effect of the common clock noise is negligible with the 3.814kHz beating rate. Figure 15 and Figure 16 show both Allan Deviation (ADEV) and Modified Allan Deviation (MDEV). A careful reader can notice that the value of the ADEV at τ=1s depends on the Equivalent Noise BW. This is not an artifact of the post-processing (since the calculated values match the measured one in Figure 17 and Figure 18) but rather an issue of the ADEV itself. The ADEV is very sensible to White PM noise, especially when it s close to the carrier (such as in our case). The issue shows as an increased instability even if the phase noise is at large offset value (e.g. ADEV with τ =1s is sensible to phase noise at 50Hz). The Modified ADEV does not exhibit this issue. The limiting factor of the DDMTD is the flicker noise, which is limiting the MDEV at τ =1s to 4E-13. The limiting ADEV value would depend on the WR PLL bandwidth setting and on the measurement bandwidth of the

23 23 instrument used to measure the CLK2 output. If an OCXO 1 were used with a WR PLL bandwidth of 1Hz, the resulting ADEV would be the one with ENBW 1Hz and it would be mostly limited by the flicker noise. 5.2 Beat frequency khz (N=16), internal DDMTD common clock The experiment is performed using two clock input (LVDS coupled) into the WR Switch. Phase-tags are processed for a 0 pi phase offset and 2 pi phase offset (equivalent to 64 ns) Table 4 Jitter with 0pi delay Integration BW Jitter RMS (ps) Full BW (0-1900Hz) 3.0 ps 0 to 1Hz 0.8ps Table 5 Jitter with 2pi delay Integration BW Jitter RMS (ps) Full BW (0-1900Hz) 4.0 ps 0 to 1Hz 0.6ps 1 The assumption is that the OCXO has a better phase noise of the DDMTD starting from 1Hz

24 DDMTD noise floor DDMTD common clk noise (est.) -85 L(f) (dbc/hz) Frquency offset (Hz) Figure 20 Phase noise floor of the DDMTD without delay (equivalent to a 10MHz carrier) calculated from the tags. The red curve is suppressed since t VAR[x e ( )] is not valid

25 DDMTD noise floor DDMTD common clk noise L(f) Frquency offset (Hz) Figure 21 Phase noise floor of the DDMTD (blue) with 2pi delay (equivalent to a 10MHz carrier) calculated from the tags, additive noise of the common clock noise on the noise floor (red) Figure 22 Additive phase noise measured by 3120A on the CLK2 output of the switch

26 ADEV 0.5Hz ENBW ADEV 1Hz ENBW ADEV 5Hz ENBW ADEV 50Hz ENBW ADEV (s) Figure 23 Allan deviation calculated from the DDMTD tags Figure 24 Allan deviation measured by 3120A on the CLK2 output of the switch

27 27 Figure 25 DDMTD common clock phase noise measured with E5052B Comments on the results Using a smaller beating rate resulted in a higher white noise floor, as expected (noise folding) and shown in Figure 20. The flicker noise is unaffected by the different beating rate. As a result, the stability values (ADEV and MDEV) are the same as in the previous experiment. Figure 21 shows the effect of the DDMTD common clock signal noise on the DDMTD noise floor.. The noise floor is rising up at f=200hz due to the common clock signal noise. The effect is also visible in Figure 22 that depicts measurements done with 3120A.

28 Beat frequency khz (N=14), external DDMTD common clock The experiment is performed to assess the phase noise floor of the DDMTD with an external DDMTD common clock signal (supplied to the WR switch using the WR SMA board). This external clock signal is not derived from any of the two input clocks. Thus, it has less phase noise correlation to the input clocks signals. Table 6 Jitter with 0pi delay Integration BW Jitter RMS (ps) Full BW (0-1900Hz) 7 ps 0 to 1Hz 1 ps Table 7 Jitter with 2pi delay Integration BW Jitter RMS (ps) Full BW (0-1900Hz) 7ps 0 to 1Hz 1ps DDMTD noise floor DDMTD common clk noise (est.) -85 L(f) (dbc/hz) Frquency offset (Hz) Figure 26 Phase noise floor of the DDMTD without delay (equivalent to a 10MHz carrier) calculated from the tags

29 DDMTD noise floor DDMTD common clk noise (est.) -90 L(f) (dbc/hz) Frquency offset (Hz) Figure 27 Phase noise floor of the DDMTD (blue) with 2pi delay (equivalent to a 10MHz carrier) calculated from the tags, additive noise of the common clock noise on the noise floor (red) ADEV 0.5Hz ENBW ADEV 1Hz ENBW ADEV 5Hz ENBW ADEV 50Hz ENBW ADEV (s) Figure 28 Allan Deviation calculated from the DDMTD tags

30 30 Figure 29 External DDMTD common clock phase noise measured with E5052B Comments on the results No significant difference is detected with respect to the experiment with the internal DDMTD common clock generation.

31 Beat frequency khz (N=14), internal DDMTD common clock, single clock The experiment is very similar to the one performed in paragraph 5.1, however only one clock signal is supplied to the FPGA. The other clock signal is duplicated inside the FPGA. This is a very interesting configuration that allows decoupling the effect of the LVDS input clock buffer from the other effects of the FPGA fabric. In this experiment, a phase offset of 1 pi is applied additionally to 0 pi and 2 pi. To accomplish a 1 pi phase-shift, the FPGA image is modified to invert one of the two clock signals. It is accomplished by modifying the configuration of the edge sensitivity of one of the DDMTD flip-flops. The modification is done using the Xilinx FPGA Editor, without design synthesis, in order to measure it with the same placement of logic inside the FPGA as in the previous experiments. Table 8 Jitter with 0pi delay Integration BW Jitter RMS (ps) Full BW (0-1900Hz) 3ps 0 to 1Hz 0.27ps Table 9 Jitter with 1 pi delay Integration BW Jitter RMS (ps) Full BW (0-1900Hz) 4.5ps 0 to 1Hz 0.7ps Table 10 Jitter with 2pi delay Integration BW Jitter RMS (ps) Full BW (0-1900Hz) 5.7ps 0 to 1Hz 0.27ps

32 L(f) (dbc/hz) Frequency offset (Hz) Figure 30 Phase noise floor of the DDMTD without delay (equivalent to a 10MHz carrier) calculated from the tags L(f) Frequency offset (Hz) Figure 31 Phase noise floor of the DDMTD with pi delay (equivalent to a 10MHz carrier) calculated from the tags

33 L(f) Frequency offset (Hz) Figure 32 Phase noise floor of the DDMTD with 2pi delay (equivalent to a 10MHz carrier) calculated from the tags ADEV 0.5Hz ENBW ADEV 1Hz ENBW ADEV 5Hz ENBW ADEV 50Hz ENBW ADEV (s/s) (s) Figure 33 Allan deviation calculated from the DDMTD tags for both delay equal to 0 or 2pi

34 ADEV 0.5Hz ENBW ADEV 1Hz ENBW ADEV 5Hz ENBW ADEV 50Hz ENBW ADEV (s/s) (s) Figure 34 Allan deviation calculated from the DDMTD tags with delay equal to pi Comments on the results The results of this experiment are very interesting. Comparing Figure 30 to Figure 12 shows that the flicker noise introduced by the LVDS input clock buffer is dominant. Also the stability at τ=1s is greatly improved. Curiously, introducing a phase shift of pi by flipping the clock edge sensitivity destroys the improvement (see Figure 31 respect to Figure 30) Using the LVPECL inputs could improve the DDMTD stability, however the newer FPGA families (7-Series) don t allow LVPECL on generic clock inputs (only on transceivers inputs) due to power consumption target.

35 Beat frequency khz (N=14), internal DDMTD common clock, 16*2pi delay The last experiment is similar to the one performed in paragraph 5.1, the only difference is that the applied phase difference is greater than 2 pi. The reason is to prove the validity of formula (3.18) with the experimental data DDMTD noise floor DDMTD common clk noise (est.) L(f) (dbc/hz) Frquency offset (Hz) Figure 35 Phase noise floor of the DDMTD with 16*2pi delay (equivalent to a 10MHz carrier) calculated from the tags Comments on the results Figure 35 shows that the predicted effect of the common clock signal noise (red trace) is in good agreement with the experimental data (blue trace)

36 36 6 Final remarks The DDMTD noise floor with the default beating rate is not affected by the common clock signal noise. However, with slower beating rate a slight noise injection is detected. Most of the DDMTD (in)stability is traced to a flicker noise, which is related to the LVDS clock input stages of the FPGA, as the experiments have shown. Using the LVPECL inputs could improve the DDMTD stability. Unfortunately, newer FPGA Xilinx families (7- Series) do not support LVPECL on generic clock input (only on dedicated hardware such transceivers). The limiting factor of the DDMTD is the flicker noise, which is limiting the MDEV at τ =1s to 4E-13. The limiting ADEV value would depend on the WR PLL bandwidth setting and on the measurement bandwidth of the instrument used to measure the CLK2 output. If an OCXO 2 was used with a WR PLL bandwidth of 1Hz, the resulting ADEV would be the one with ENBW 1Hz and it would be mostly limited by the flicker noise. The current DDMTD resolution of ~1 ps, combined with the default PTP sync rate equal to 1 s, may create oscillations of ± 0.5 ps on the boundary clock due to the limited resolution. The effect in Modified Allan Deviation is an additive (in)stability of 3E-13 at Tau=1s. The current implementation of DDMTD is not limiting the performance of WRS since the Gigabit transceiver recover the clock from the medium with an additive (in)stability of MDEV 4E-13 at Tau=1s (using a TX clock with stability of 1E-13 at Tau=1s). 6.1 Improvements tried The author tried to reduce the phase noise floor of the DDMTD. Averaging of the tags using several DDMTDs was tried. When using 32 DDMTDs for both clocks input, the expected improvement is a 15dB lower phase noise floor. Instead, only a 7 db is measured (as shown in Figure 36). The reason is probably the common clock noise floor. Flicker noise was not improved, as expected from experiment 5.4. Figure 36 Phase noise with Multi DMTD averaging 2 The assumption is that the OCXO has a better phase noise of the DDMTD starting from 1Hz

37 Suggestions Preliminary measurements using an (over)heated SPEC showed that the phase noise floor may depend on the temperature. This is not easy to characterize as the heat depends also on the design (bitstream) loaded into the FPGA. Keeping the FPGA cool is a good idea. The beating rate of the DDMTD, combined with its high single-shot precision, is a very valuable asset. The author suggests to not reduce the beating rate below 500 Hz, even when using an OCXO and a narrow bandwidth (i.e. 1Hz or 0.1Hz). The reason is that with high beating rate, the controlling DAC quantization noise is distributed into a wider bandwidth making it easier to filter out the control loop (WR PLL) noise, e.g. filtering out the noise on the EFC line of the controlled oscillator. The phase noise of the common clock must be kept under control when using very low beating rate.

38 38 7 References [1] D. W. Allan and H. Daams, "Picosecond time difference measurement system", in Proc. 29th Annual Frequency Control Symp., May [2] Pedro Moreira, Pablo Alvarez, Javier Serrano, Izzat Darwazeh, "Sub-nanosecond digital phase shifter for clock synchronization applications", Frequency Control Symposium (FCS) 2012 IEEE International, pp. 1-6, 2012, ISSN [3] L. Sze-Ming, Influence of noise of common oscillator in dual-mixer time-difference measurement system, in IEEE Transactions on Instrumentation and Measurement, vol. IM-35, 1986, pp [4] AD9516 EVAL KIT: [5] WR SMA BOARD: [6] Grandmaster report: