IN COMPARISON with the traditional heterodyne architecture,

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1 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 6, JUNE Direct-Conversion Quadrature Modulator MMIC Design With a New 90 Phase Shifter Including Package and PCB Effects for W-CDMA Applications Jian-Ming Wu, Student Member, IEEE, Fu-Yi Han, Tzyy-Sheng Horng, Senior Member, IEEE, and Jenshan Lin, Senior Member, IEEE Abstract This paper presents a wideband code-division multiple-access direct-conversion quadrature modulator monolithicmicrowave integrated-circuit (MMIC) design that employs a new technique to generate the 90 phase shift with low implementation loss. From the bare-chip measurement, this new 90 phase shifter has been proven with an amplitude and phase error less than 0.6 db and 0.8, respectively, within the applied frequency range from 1.85 to 1.98 GHz. The package and printed circuit board (PCB) interconnects are also analyzed using the three-dimensional electromagnetic simulation tool and transformed into the equivalentcircuit elements for co-simulation with the designed quadrature modulator MMIC. The degradation of error vector magnitude and sideband suppression due to the package and PCB can be well predicted and verified by measurements. Although the proposed 90 phase shifter has a remarkable advantage over the others in implementation loss, it is quite susceptible to the package and PCB effects and needs more design efforts to deal with those effects. Index Terms Package and printed circuit board (PCB) effects, phase shifter, quadrature modulator. I. INTRODUCTION IN COMPARISON with the traditional heterodyne architecture, the direct-conversion architecture removes the IF process such that it can reduce the amount of local oscillators (LOs), mixers, and filters and lead to a high integration. The performances of a direct-conversion quadrature modulator such as the error vector magnitude (EVM), sideband suppression, and modulation bandwidth highly depend on the amplitude and phase errors of a 90 phase shifter. Many techniques have been reported to design a 90 phase shifter with low amplitude and phase errors. They are summarized to include the: 1) frequency divide-by-two scheme [1] [3]; 2) RC CR network [4], [5]; 3) LC high- and low-pass filter [6], [7]; 4) RC all-pass filter [8], [9]; 5) ring oscillator [10], [11]; and 6) poly-phase filter [12] [14]. The first technique generates an accurate 90 phase shift, but requires high dc power consumption. For the second technique, it can be done with simplicity and low dc power consumption, but has high implementation loss inherently. The third technique has less Manuscript received October 18, 2005; revised January 13, This work was supported in part by the Ministry of Education under Program of Aim for the Top University Plan, Taiwan, R.O.C., and by the National Science Council, Taiwan, R.O.C., under Grant E J.-M. Wu, F.-Y. Han, and T.-S. Horng are with the Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 804, Taiwan, R.O.C. ( jason@ee.nsysu.edu.tw). J. Lin is with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL USA ( Jenshan@ufl.edu). Digital Object Identifier /TMTT implementation loss, but is difficult to integrate. It is broadband, but complicated in design for the fourth technique. The fifth technique offers a relatively imprecise 90 phase shift and also consumes much dc power. For the sixth technique, it has a large implementation loss of approximately 3 db for one stage and may need at least 2 3 stages for an accurate 90 phase shift. A new technique to generate the precise 90 phase shift has been proposed in this paper. It adopts a similar configuration of the differential amplifier pair shown in [4], but has the distinguishing feature that one differential amplifier with an emitterdegeneration inductance and the other one with an emitterdegeneration capacitance create the 90 phase shift. In further analysis, this phase shifter is based on an RL RC network. The resistances in this RL RC network are the intrinsic resistances of transistors and differ from those in the above-referred RC CR network that uses real resistors. Therefore, the proposed 90 phase shifter is advantageous to have a relatively low implementation loss. A 1.9-GHz direct-conversion quadrature modulator featured with the proposed 90 phase shifter was implemented for wideband code-division multiple-access (W-CDMA) applications as a monolithic microwave integrated circuit (MMIC) and then housed in a leadless wire-bond package for the convenience of testing on a printed circuit board (PCB). It has been reported that the wire-bond packages usually behave like low-pass filters to reduce the operating bandwidth of MMICs [15], [16], and also play important roles to move the input impedance away from the optimum point in noise-figure matching [17], [18] for a low-noise amplifier MMIC. In [19] and [20], we have studied the degradation of linearity due to the package and PCB for an upconverter MMIC. In this research, the package and PCB interconnects are also carefully modeled to account for their effects on the implemented direct-conversion quadrature modulator MMIC during the on-board test. It is noted that, in [21], only some preliminary results of this research were presented without so much detailed analysis and measurement of the package and PCB effects, as shown in this paper. II. DIRECT-CONVERSION QUADRATURE-MODULATOR MMIC FEATURED WITH A NEW 90 PHASE SHIFTER The circuit schematic of the proposed 90 phase shifter is shown in Fig. 1. It consists of two differential amplifiers. One connects an inductance as an emitter-degeneration element, while the other connects a capacitance instead. Each differential amplifier has one input for the coming single-ended LO signal and has /$ IEEE

2 2692 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 6, JUNE 2006 With use of (1), the amplitude and phase error of the 90 phase shifter can be defined as (2) (3) Fig. 1. Circuit schematic of the proposed new 90 phase shifter. In reality, the choices of and are within the constraints and, which can simplify (2) and (3) as (4) From (4) and (5), both amplitude and phase error are equal to zero only when (5) (6) Fig. 2. Small-signal T-equivalent differential half-circuit for the proposed 90 phase shifter using a round spiral inductor as an emitter-degeneration element. the other input ac grounded. The phase difference between two differential amplifier outputs is aimed at 90. In practice, the combination of one inductance and one capacitance cannot generate the 90 phase shift. The 90 phase shift is mainly determined by the intrinsic resistances in the transistors and in conjunction with the emitter-degeneration inductance and capacitance. Assume that the transistors and match each other. The center node between the emitters of the differential amplifier connecting the bias current source is virtually grounded due to the balanced operation of the circuit. We can analyze the differential amplifier with its differential half-circuit in the common-emitter configuration. Fig. 2 shows the equivalent small-signal T-model for such a differential half-circuit having the emitter-degeneration element of impedance, which is equal to either or. In the circuit shown in Fig. 2, and represent the signal source voltage and the base emitter voltage, respectively. The base emitter resistance is denoted by. is the base emitter junction capacitance that consists of the diffusion and depletion capacitance. represents the emitter resistance. The transistor transconductance is denoted by. When the collector is assumed ac grounded, the transconductance gain normalized with respect to for the differential half-circuit shown in Fig. 2 is derived as (1) Under the conditions of (6) and (7), the differential amplifier with an emitter-degeneration inductance has a phase lag of 45, while the differential amplifier with an emitter-degeneration capacitance has a phase lead of 45. However, creating such a 90 phase difference between the two differential amplifiers is at the expense of the gain reduction due to the emitter-degeneration inductance or capacitance. Therefore, an implementation loss can be defined as the ratio of the absolute value of normalized transconductance gain, calculated without the emitter-degeneration inductance or capacitance, to the same gain, calculated considering such an effect, which is expressed as or (7) db (8) When, the implementation loss is calculated equal to 3 db, which is the smallest value among the reported data in the current literature regarding the active 90 phase-shifter designs. In the implementation of the above-described 90 phase shifter using an InGaAs heterojunction bipolar transistor (HBT) foundry process with up to 30 GHz, the quantity of and forward ideality factor ( ) of the HBT is found as 7.05 and 1.042, respectively, in the SPICE model provided by the foundry. Under the bias collector current of 3.2 ma, can be approximated equal to, which is calculated as. Note that represents the thermal voltage and is approximately equal to V at room temperature. For W-CDMA applications, the design center frequency is chosen at GHz. After substituting these quantities into (6) and (7), the calculated solution of and is approximated to 2.6 nh and 2.6 pf, respectively, for constructing such a 90

3 WU et al.: DIRECT-CONVERSION QUADRATURE MODULATOR MMIC DESIGN WITH NEW 90 PHASE SHIFTER 2693 Fig. 3. Block diagram of the direct-conversion quadrature modulator MMIC. phase shifter. We use a round spiral inductor and metal insulator metal (MIM) capacitor to realize these two components with specific value. It is cautioned that the 2.6-nH round spiral inductor has much larger parasitic elements than the 2.6-pF MIM capacitor and, therefore, it is better to use the complete equivalent circuit extracted from -parameter measurement for this inductor in the final circuit design, as illustrated in Fig. 2. The block diagram of the direct-conversion quadrature modulator is shown in Fig. 3. It consists of a 90 phase shifter, two double-balanced mixers, a differential-to-single-ended converter, and an output buffer. All the essential microwave circuits are integrated inside a single chip. The LO signal is split into two in-phase single-ended signals of equal amplitude before applied to the two differential amplifiers. The outputs of the two differential amplifiers featured with the proposed 90 phase shifter are the two differential signals of equal amplitude with 90 phase difference. Quadrature modulation is finally done with the help of two Gilbert-cell mixers. The differential to the single-ended converter is in a totem-pole configuration and takes charge of transforming the double-balanced mixer s differential output into a single-ended one. The buffer is designed with output impedance matched to 50 for the purpose of power amplification. The proposed 90 phase shifter and the direct-conversion quadrature modulator that uses this 90 phase shifter were implemented in a single chip with 2 mm 1 mm area. Its microphotograph is shown in Fig. 4. Fig. 5 shows the amplitude error and phase error extracted from the measured -parameters of the 90 phase shifter. At the center design frequency of GHz, the measured amplitude and phase error is observed as 0.25 db and 0.2, respectively. Within the W-CDMA transmit bands I and II that cover from 1.85 to 1.98 GHz, the measured phase error is maintained quite low, less than 0.8. The measured amplitude error within the same transmit bands is higher due to parasitic loss in the 2.6-nH round spiral inductor, but still under 0.6 db. The average deviation of the theoretical results from the measured data is 0.2 db and 0.4 for the amplitude and phase error, respectively. III. EVALUATION OF PACKAGE AND PCB EFFECTS ON THE IMPLEMENTED QUADRATURE-MODULATOR MMIC The quadrature modulator requires a four-port measurement setup to provide the baseband in-phase (I) and quadrature (Q) signals and the LO carrier with a power sweep as input signals, and generate the output RF modulated signal for test of Fig. 4. Chip micrograph of the implemented direct-conversion quadrature modulator MMIC. Fig. 5. Comparison between theoretical and measured results of amplitude and phase errors for the 90 phase shifter without including the package and PCB effects. Fig. 6. (a) Wire-bonded chip in the packaging process. (b) Packaged chip on PCB for testing. the EVM and sideband suppression. This measurement is not easily done on-wafer. For the convenience of measuring the complete RF parameters, the MMIC was housed in a 32-pin bump chip carrier (BCC) package with an overall dimension of 5 mm 5mm 0.8 mm. Fig. 6(a) presents a chip wirebonding photograph in the packaging process. The packaged chip was finally surface mounted onto a PCB with an area of 27 mm 26 mm for testing, as seen in Fig. 6(b). It is noted that the 32-pin BCC package is a leadless quad package and can reduce more than one-half in the area of a mounting footprint when compared to the conventional lead quad package like quad flat pack (QFP) with the same pin count.

4 2694 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 6, JUNE 2006 phase shifter. (b) Its small- Fig. 9. (a) Circuit schematic of the proposed 90 signal T-equivalent circuit. Fig D configuration shown in an EM extractor for simulating the equivalent parasitic elements of package and PCB interconnects. TABLE I SIMULATED PARASITIC ELEMENT QUANTITIES OF THE OUTPUT AND GROUND INTERCONNECTS IN THE PACKAGE AND PCB Fig. 10. (a) Circuit schematic of the proposed double-balanced mixer. (b) Its small-signal -equivalent differential half-circuit. Fig. 8. Circuit simulation of direct-conversion quadrature-modulator MMIC with inclusion of the package and PCB interconnect parasitic elements. ground impedance in grounding one of the two input ports for each differential amplifier. Fig. 9(a) shows the circuit schematic for one of the differential amplifiers in the 90 phase shifter that considers the common-ground parasitic elements in the package and PCB. It is noted that the extracted quantities of these ground parasitic elements can be found in Table I. After analysis of its equivalent circuit, as shown in Fig. 9(b), one can derive the transconductance gain normalized with respect to in the following form: The parasitic effects for the interconnects realized on the MMIC are assumed negligible in comparison with those realized on package and on the PCB. As illustrated in Fig. 7, we use the electromagnetic (EM) extractor based on a three-dimensional (3-D) quasi-static methodology to calculate the equivalent parasitic element quantities for the package and PCB interconnects in connection to the RF output and ground terminals of the quadrature modulator MMIC. The calculated quantities are listed in Table I. The corresponding equivalent circuit of these interconnects when used for co-simulation with the quadrature modulator MMIC is shown in Fig. 8. It should be particularly noted that the parasitic elements of the package and PCB interconnects in connection to the baseband I and Q and the LO terminals have been neglected because they hardly influence the output modulation quality. The package and PCB effects on the individual stage, as well as the overall circuit of the quadrature modulator MMIC can be analyzed as follows. A. 90 Phase Shifter The dominant package and PCB effects on the proposed 90 phase shifter, as described in Section II, is to cause nonzero where corresponds to the equivalent ground impedance for these ground parasitic elements. B. Double-Balanced Mixer The design of double-balanced mixers in the quadrature modulator adopts a Gilbert-cell structure with emitter degeneration to enhance the linearity performance, as shown in Fig. 10(a). The transistors from to form the basic structure of a Gilbert cell. The input differential baseband signal is amplified by the differential-pair transistors, i.e., and, which are individually degenerated by an emitter resistance. The output voltage drops on the load resistances are then caused by the differential LO signal when applied to switch on the transistors from to. This way, the baseband and LO signals are mixed to generate the output differential RF signal, which is finally transformed into a single-end one by an on-chip differential to single-ended converter. Since the double-balanced mixer has a well-matched differential configuration, one (9)

5 WU et al.: DIRECT-CONVERSION QUADRATURE MODULATOR MMIC DESIGN WITH NEW 90 PHASE SHIFTER 2695 Fig. 11. (a) Circuit schematic of the proposed differential to single-ended converter. (b) Its small-signal -equivalent circuit. can regard the current source terminal as a virtual ground. This implies that the double-balanced mixer is not affected by the ground interconnects in the package and PCB. As a matter of fact, the influence of package and PCB still exists because the output load impedance of the double-balanced mixer, i.e.,, is dependent on the ground parasitic elements. The main reason to account for this dependence is that can be regarded as the input impedance of the next stage component, a differential to single-ended converter, which needs to be common grounded for delivering a single-ended signal and, therefore, has an input impedance with dependence on the common-ground parasitic elements in the package and PCB. Through an analysis of the equivalent differential half-circuit, shown in Fig. 10(b), the transconductance gain of double-balanced mixer can be derived as a function of the equivalent-circuit elements and the load impedance, which is given as (10) C. Differential to Single-Ended Converter Fig. 11(a) shows the circuit schematic of the differential to single-ended converter including the package and PCB parasitic elements. The converter adopts a totem-pole structure with a stack-up of two transistors, i.e., and. One transistor is in a common-collector configuration and serves as the input end of the differential positive signal. The other one is in a common-emitter configuration and serves as the input end of the differential negative signal. Fig. 11(b) shows the equivalent small-signal -model of this converter with a current gain derived as Fig. 12. (a) Circuit schematic of the proposed output buffer. (b) Its small-signal -equivalent circuit. where represents the output load impedance. Note that can be regarded as the input impedance of the next stage component, an output buffer, and still has the dependence on the package and PCB parasitic elements. In (10), can be regarded as the input impedance of this converter and has been found as (12) D. Output Buffer As shown in Fig. 12(a), the ground and output interconnect parasitic impedances and admittance in the package and PCB are considered in evaluation of the output buffer performance. It is noted that the output buffer is in a common emitter configuration with a parallel feedback for consideration of stability. The output impedance is matched to 50. With an equivalent circuit shown in Fig. 12(b), the output buffer has been analyzed to have a transimpedance gain given as (11) (13)

6 2696 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 6, JUNE 2006 Fig. 14. Comparison of the EVM of the quadrature modulator between inclusion and exclusion of the package and PCB effects. Fig. 13. Accumulated amplitude error, phase error, and power loss at consecutive stages of the quadrature modulator including the package and PCB effects. where and represent the equivalent shunt impedances after using Miller s theorem to deal with the parallel feedback elements and. In (12), can be regarded as the input impedance of this output buffer and has been found as (14) E. Overall Effects The overall effects of the package and PCB on the implemented quadrature modulator MMIC can be summarized with the following total gain: (15) The above total gain, as well as the gains of individual stages, can be used to replace the gain without considering the package and PCB effects in (2) and (3) for yielding the amplitude and phase errors in the overall circuit and the individual stages with inclusion of package and PCB effects. Besides, the package and PCB effects also cause a power loss in each stage and overall of the quadrature modulator, which can be modeled as db (16) where with subscript denotes the gain of the th stage or the total gain. Fig. 13 shows the accumulated amplitude error, phase error, and power loss at consecutive stages of the quadrature modulator including the package and PCB effects. In Fig. 13, the symbols are used to pinpoint the quantities of those parameters at the center frequency of GHz, and the gray I bars are used to indicate the variation in quantity for those parameters within the applied frequency range from 1.85 to 1.98 GHz. It can be clearly seen that, after considering the package and PCB effects, the 90 phase shifter is the dominant component to the total amplitude and phase error, while the output buffer is the dominant component to the total loss due to the presence of package and PCB. IV. RESULTS AND DISCUSSIONS A. EVM In Fig. 13, the accumulated magnitude and phase errors at the output buffer stage of the quadrature modulator MMIC in consideration of the package and PCB effects can be used to predict the EVM of quadrature phase-shift keying (QPSK)-modulated output signal. Under the condition that the amplitude error and phase error approach unity and zero, respectively, an approximate formula to calculate the EVM can be found as % (17) Fig. 14 compares the calculated EVM (solid line) with the measured results (square symbols) over the entire applied frequency range. The comparison shows good agreement with an average difference of 0.25%. In a similar fashion, the accumulated amplitude and phase error at the output buffer stage of the quadrature modulator MMIC without inclusion of package and PCB effects can also be obtained by setting all the parasitic impedances and admittances in (9) (14) equal to zero. With these data, we again apply (17) to calculate the corresponding EVM, as plotted in the dotted line of Fig. 14. One can compare to see that the package and PCB effects increase the EVM by an average of approximately 5.8%. B. Sideband Suppression When treated as a single-sideband modulator, the quadrature modulator is selected to output the upper sideband (USB) signal rather than the lower sideband (LSB) signal by inserting the baseband I signal with a 90 phase lag to the Q signal. The variations in both USB and LSB power levels due to the amplitude

7 WU et al.: DIRECT-CONVERSION QUADRATURE MODULATOR MMIC DESIGN WITH NEW 90 PHASE SHIFTER 2697 When compared to the on-pcb measured results (square symbols), good agreement with both simulated and theoretical results can be seen up to an input LO power of 20 dbm. The sideband suppression within this range is approximately 23 db. An input LO power larger than 20 dbm drives the output buffer into compression, which is not well predicted by the presented theory and simulation. From the comparison of output USB and LSB power levels between the bare and packaged chips, the package and PCB effects have caused the USB power level to decrease by approximately 5.2 dbm and the LSB power level to increase by approximately 3.1 dbm. This results in a total of 8.3-dB degradation in the sideband suppression due to the presence of the package and PCB. Fig. 15. Comparison of the sideband suppression of the quadrature modulator between inclusion and exclusion of the package and PCB effects. and phase errors of quadrature modulator have been successfully derived and verified in [22]. However, for this case, not only the amplitude and phase errors, but also the power losses due to the presence of the package and PCB will vary the USB and LSB power levels. Therefore, with the derived formulas in [22] to account for the influence of amplitude and phase errors and (16) to account for the package and PCB losses, we can predict the output USB and LSB power levels for the implemented quadrature modulator MMIC in consideration of the package and PCB effects as follows: dbm (18) V. CONCLUSION A W-CDMA direct-conversion quadrature-modulator MMIC design featured with a new 90 phase shifter has been presented. The main advantage is less implementation loss in comparison with the other available techniques. The package and PCB effects on the implemented quadrature modulator MMIC have also been studied. It was observed through our careful analysis and measurement that the package and PCB effects caused an average of 5.8% increase in EVM and 8.3-dB degradation in sideband suppression. The component most responsible for these phenomena is the proposed 90 phase shifter whose amplitude and phase balances are quite susceptible to the ground parasitic elements in the package and PCB. ACKNOWLEDGMENT The authors wish to thank the National Chip Implementation Center, Taiwan, R.O.C., for providing the InGaAs HBT foundry service, and Advanced Semiconductor Engineering Inc., Kaohsiung, Taiwan, R.O.C., for providing the packaging service. Our gratitude is also given to the National Science Council, Taiwan, R.O.C., for sponsoring the Graduate Student Study Abroad Program (GSSAP) to bring about this international cooperative research project. dbm (19) where the subscript bare chip denotes the results for the barechip case, i.e., the case without considering the package and PCB effects. In the on-pcb measurement, the frequency of the input baseband I and Q signals is set at 5 MHz and the LO frequency is centered at GHz. The output frequency of LSB and USB signal corresponds to 1.91 and 1.92 GHz, respectively. Fig. 15 compares the results for the output USB and LSB power levels between inclusion and exclusion of the package and PCB effects. The simulation results (solid line) are generated from the Advanced Design System (ADS) based on the circuit configuration, as illustrated in Fig. 8. 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J., vol. 43, pp , May Jian-Ming Wu (S 00) was born November 13, 1974, in Kaohsiung, Taiwan, R.O.C. He received the B.S.E.E. degree from Yuan Ze University, Chungli, Taiwan, R.O.C., in 1997, the M.S.E.E. degree from National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C., in 2000, and is currently working toward the Ph.D. degree in electrical engineering at National Sun Yat-Sen University. His research interests include design and modeling of MMIC components and packages. Fu-Yi Han was born December 4, 1979, in Taichung, Taiwan, R.O.C. He received the B.S.E.E. and M.S.E.E. degrees from National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C., in 2001 and 2003, respectively, and is currently working toward the Ph.D. degree in electrical engineering at National Sun Yat-Sen University. His research focuses on the chip-package-board codesign of RF components and modules. Tzyy-Sheng Horng (S 88 M 92 SM 05) was born December 7, 1963, in Taichung, Taiwan, R.O.C. He received the B.S.E.E. degree from National Taiwan University, Taipei, Taiwan, R.O.C., in 1985, and the M.S.E.E. and Ph.D. degrees from the University of California at Los Angeles, in 1990 and 1992, respectively. He is currently a Professor with the Department of Electrical Engineering and also the Director of the Institute of Communications Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C. His research interests include RF and microwave integrated circuits, RF systems-on-package, and digitally assisted RF technology. Jenshan Lin (S 91 M 94 SM 00) received the B.S. degree from National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1987, and the M.S. and Ph.D. degrees in electrical engineering from the University of California at Los Angeles (UCLA), in 1991 and 1994, respectively. In 1994, he joined AT&T Bell Laboratories (later Lucent Bell Laboratories), Murray Hill, NJ, as a Member of Technical Staff, and became the Technical Manager of RF and High Speed Circuit Design Research in Since joining Bell Laboratories, he has been involved with RF integrated circuits using various technologies for wireless communications. In September 2001, he joined Agere Systems, a spin-off from Lucent Bell Laboratories, and was involved with high-speed CMOS circuit design for optical and backplane communications. In July 2003, he joined the University of Florida, Gainesville, as an Associate Professor. He has authored or coauthored over 100 technical publications in referred journals and conferences proceedings. He holds five patents. His current research interests include RF system-on-chip integration, high-speed broadband circuits, high-efficiency transmitters, wireless sensors, biomedical applications of microwave and millimeter-wave technologies, and software-configurable radios. Dr. Lin has been active in the IEEE Microwave Theory and Techniques Society (IEEE MTT-S). He is an elected Administrative Committee (AdCom) member serving the term of He is a member of the Wireless Technology Technical Committee. He has served on several conference Steering Committees and Technical Program Committees including the IEEE MTT-S International Microwave Symposium (IMS), the Radio Frequency Integrated Circuits Symposium (RFIC), the Radio and Wireless Symposium (RWS), and the Wireless and Microwave Technology Conference (WAMICON). He is currently the Technical Program co-chair of 2006 and 2007 RFIC Symposium, and the finance chair of the 2007 RWS. He was the recipient of the 1994 UCLA Outstanding Ph.D. Award and the 1997 Eta Kappa Nu Outstanding Young Electrical Engineer Honorable Mention Award. He has been the coauthor/advisor of several IEEE MTT-S IMS Best Student Paper Awards and advisor of an IEEE MTT-S Undergraduate/Pre-Graduate Scholarship Award.