1.1.1 Functional Block Diagram

Transcription

1 1.1.1 Functional Block Diagram Antenna A1 RF Card A2 Digital/PS Transmitter Frequency Synthesizer LPF T/R DAC & ADC / Control lines System Processor Maintenance Processor Frequency Synthesizer Receiver VOCODER I/O - ARINC, Discretes Power Supply Rear Connector LED Card A3 Rear Interconnect A4 LED Interface

2 1.1.2 Interface Diagram VDL3 Enh V oice Data Activ e Preset Next Next Frequency Upload and Annunciations ANTENNA V/D LS 429 TO OPPOSITE SIDE CMU/OMS HS 429 FOR AUTOTUNE PORT B LS TUNING CMU PORT B OMS PORT B CMU (Optional) HS CMU HS PORT A V/D CMU OUT CMU PORT A V/D VHF-2100 OMS OUT PORT A OMS IN LS 429 OMS LS 429 OMS OMS PORT A LS TUNING +28 VDC LS 429 AUDIO PTT ANALOG MIC ANALOG ACARS (Optional) /2 /2 PORT A/B SELECT DATA KEY DATA AUDIO OUT DATA AUDIO IN /2 /2 AUDIO SYSTEM

3 1.1.3 System Interconnect Diagram

4 A3 ASSEMBLY A4 ASSEMBLY (FRONT PANEL) Rear Connector Phone/ Mic RS- 232 S. T. LED's RF BZT Filter DATA_INPUT_H DATA_INPUT_L MIC_GND AUDIO_OUT_H AUDIO_OUT_L ARINC 429 & Discretes FP_ KEYLINE GND DEBUG _PORT _TX DEBUG _PORT _RX FP_ SELF_ TEST ANT_ FAIL ANT_ PASS LRU_ FAIL LRU_ PASS CONTR _FAIL CONTR _PASS +28VDC_ MAIN_ BUSS MIC_INPUT_L MIC_INPUT_H TXRX_RF IF_SIGNAL AGC_LEVEL D8PSK_MODE MODE_3_CO_SITE T/R SWITCH TX_RF RX_RF RX_LO RECEIVER RX/TX SYN. PRESEL_1 PRESEL_2 PRESEL_3 PRESEL_4 SCOM_TRESH FAST_AGC T/R_SWITCH TX_KEY CLOCK DATA RX_STROBE TX_STROBE REF_FREQ RX_SYNTH_LOCK TX_SYNTH_LOCK DSP/IO/MAINTENANCE/VOCODER CHASSIS GND TX_RF_ DRIVE TRANS. BIAS CLAMP_ENABLE I_MOD Q_MOD Q_PHASE_ADJ I_PHASE_ADJ PA_DRIVER_BIAS PA_FINAL_BIAS V-FWD V_REV Q_DET PA_TEMP GND +28VDC_ MAIN_ BUSS POS_3.3VDC PWR_WARN PS_FREQ CLAMP_ON_INT_F +28VDC_CLAMPED POS_8VDC NEG_8VDC POS_15VDC POWER SUPPLY & CLAMP A1 ASSEMBLY A2 ASSEMBLY VHF-2100 ASSEMBLY INTERFACE DIAGRAM KEY COAX RIBBON

5 1.1.4 Transmitter Block Diagram +20 dbm RF Input TO RCVR INPUT I-Q MOD -40 db cplr -30 db Coupler T/R BTZ LP FILTER I Q PA LO PHASE ADJUST RF LO Q RF I PHASE_I I-Q DEMOD PHASE_Q FWD_PWR FWD/REV SENSORS PA TEMP SENSOR REV_PWR ERROR AMPS/ LOOP FILTERS Q_INPUT PA TEMP I_INPUT

6 1.1.5 Receiver Block Diagram PS#1 PS#2 PS#3 PS#4 RF Input (from T/R Switch) -20 db COUPLER FM BAND REJECT SIMULCOM ATTN 2 Pole Filter 2 Pole Filter RF AMP Simulcomm Control MHz Crystal Filter +16 khz BW MIX IF AMP 2nd Harmonic Rej AGC Control MHz IF output Lo Input MHz 17 dbm min Simulcomm Detector/ Loop Amp RF AMP and VHF BP FILTER AM Detector and 10.5 KHz Filter Integrator/ Comparator/ Monostable Mode 3 Co-Site Detect Simulcomm Control output

7 1.1.6 Transmit Synthesizer Block Diagram +20 dbm MHz Reference Divider Phase/ Frequency detector Loop Filter/ LPF VCO Regenerative Divide by 2 Programmable divide by N MHz Hi Isolation Amp Prescaler 23.1 MHz TCXO (on A2 assy) Output Enable Synthesizer Programming Data Detail of Regenerative Frequency Divider L R LPF - image rejection IF Mixer Pwr Splitter BPF (Series LC) Amp

8 1.1.7 Receiver Synthesizer Block Diagram. Loop Filter/LPF +17 dbm Min MHz Reference Divider Phase/Frequency Detector VCO 23.1 MHz TCXO - on A2 Assembly Programmable Divide by N Counter Dual-Modulus Prescaler Reverse Isolation Amplifier Synthesizer Programming Data A2 DSP Circuit Card Block Diagram

9 VHF IF MHz I Channel Tx Q Channel Tx WD A/D Converter AD6640 bandpass sample Level Translators & Filters Multirate Decimator/ Parallel- Serial AD6620 AD5322 D/A 23.1 MHz Sport0 Rx TMS320VC5416 DSP SYSP Sport2 TX WD Timer Sport1 Tx Sport0 TX Sport1 Rx Sport2 Rx A/D Bus WD AD5322 D/A X2 AD output D/A EPLD Glue Logic Level Translators & Filters RX Preselect I Mod Q Mod I_Phase_ADJ Q_Phase_ADJ Data Audio Out H Data Audio Out L RX Audio H RX Audio L Spare External Discrete Inputs: PTT Data Key SDI 1 SDI 2 CDFS_1_select CFDS_2_select Port B/A Select Tx Timer Disable Voice/Data_Select Frequency offset enable Data_load Shop_mode Squelch Disable Air-Ground Selftest Sport0 Rx TMS320VC5416 DSP VOCODER Sport0 Tx WD 32.0 MHz Intel 28F160C Flash 1M x 16 80C188C MAINTP (VHF-920 reuse) Eland Serial 600 baud ARINC-429 HS/LS Tx 1-8 ARINC-429 HS/LS Rx 1-16 Discrete Inputs Rx Synth Lock Tx Synth Lock Mode 3 Detect ARINC-429 OMS RX External ARINC- 429 OMS RX/TX Snoopy 2 Tx_Synth Clock and Data Rx_Synth Clock and Data Discrete Outputs MAX146A/D x2 Mic Audio H Mic Audio L Data Audio In H Data Audio In L Q Det AGC level DSP +28 Vdc V_FWD V_REF RS-232 front panel External Discrete Outputs: Audio Mute

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