Data Sheet. AFEM-7780 UMTS2100 4x7 Front-end Module (FEM) Feature. Description. Applications. Component Image. Ordering Information.

Transcription

1 FEM-0 UMTS00 x Front-end Module (FEM) Data Sheet Description The FEM-0 is a fully matched WCDM Band Frond- End Module (FEM) featuring the integration of vago Technologies power amplifier and FBR. The FEM-0 offers extended talk time and excellent linearity by using CoolPM technology, which enhances efficiencies in low and medium power mode. Idle current is as low as m. The FBR (Film Bulk coustic Resonator) based duplexer provides low insertion loss and outstanding isolation, which improves efficiency and RX sensitivity. By using CoolPM and FBR technologies, FEM-0 shows best performance with smaller footprint. Component Image Feature Excellent linearity Operating Frequency: Tx: 0~0 MHz Rx: 0~0 MHz. dbm Linear Output Power (HSDP) Very low quiescence current in low power mode High isolation (Low Tx leakage at Rx port) HSDP capable 0 ohm input and output matching 0-pin surface mounting package. 0 x.0 x.(typ) mm SMT Package pplications WCDM handset (HSDP) Ordering Information Block Diagram Part Number Number of Devices Container FEM-0-TR 000 mm ( ) Tape/Reel FEM-0-BLK 00 Bulk Vcc() Vcc() RX() RFIN () Input Match D Inter Stage Match P Output Match NT (0) Bias Circuit & Control Logic Switch Vmode (0) Vmode0 () Ven () CPL ()

2 bsolute Maximum Rating No damage assuming only one parameter is set at limit at a time with all other parameters set at or below typical value Operation of any single parameter outside these conditions with the remaining parameters set at or below typical values may result in permanent damage Description Min Typ Max Unit ssociated Pins Tx Input Power 0 0 dbm RF IN DC Supply Voltage..0 V Vcc Enable Voltage.. V Ven Control Voltages.. V Vmode0, Vmode Storage Temperature - C Recommended Operating Conditions Description Symbol Min Typ Max Unit Tx Frequency 0 0 MHz Rx Frequency 0 0 MHz DC Supply Voltage (Vcc, Vcc)... V Enable Voltage (Ven) Mode Control Voltage (Vmode0, Vmode) LOW V HIGH... V LOW V HIGH... V Case Operating Temperature C Operation Logic Table Power Mode Recommended Pout Range Ven Vmode0 Vmode High Power Mode ~. dbm HIGH LOW LOW Mid Power Mode ~. dbm HIGH HIGH LOW Low Power Mode ~ dbm HIGH HIGH HIGH Shunt Down Mode LOW - -

3 Electrical Characteristics - Conditions: Vcc=Vcc=., Ven=.V, Temp= C - Signal configuration: HSDP modulated uplink (DPCCH/DPDCH=/, HS-DPCCH/DPDCH=/) Parameter Condition Min Typ Max Unit TX to ntenna Port Tx Operating Frequency Range TX 0 0 MHz Maximum Output Power High Power Mode. dbm Gain High Power Mode, Po=.dBm. db Mid Power Mode, Po=.dBm. db Low Power Mode, Po=dBm db Power dded Efficiency High Power Mode, Po=.dBm 0.. % Mid Power Mode, Po=.dBm.. % Low Power Mode, Po=dBm.. % Current Consumption High Power Mode, Po=.dBm 00 m Mid Power Mode, Po=.dBm 0 m Low Power Mode, Po=dBm m Quiescent Current High Power mode 0 m Mid Power mode m Low Power Mode 0 m djacent Channel Power ±MHz offset, High Power Mode, Po=.dBm - - dbc ±0MHz offset, High Power Mode, Po=.dBm - - dbc ±MHz offset, Mid Power Mode, Po=.dBm -0 - dbc ±0MHz offset, Mid Power Mode, Po=.dBm -0 - dbc ±MHz offset, Low Power Mode, Po=dBm - - dbc ±0MHz offset, Low Power Mode, Po=dBm -0 - dbc Harmonics nd Harmonics -0 - dbm/mhz rd Harmonics - - dbm/mhz Input VSWR at Tx port.: Stability, spurious level TX source VSWR < : FEM ntenna load VSWR < :, all angles Leakage current at shutdown Change in TX insertion phase Intermodulation -0 dbc Ven=0V, without RF u MPM HPM 0 degree LMP MPM degree CW interface MHz: Intermod Intermod products dbc dbc

4 Electrical Characteristics (continued) Noise Power from TX GPS Band (0-0MHz) - - dbm/hz DCS Band (0-0Mhz) - - dbm/hz ISM Band (00-0MHz) - - dbm/hz Noise folding at DCS Band Tx port noise input power=-dbm/hz - - dbm/ 00kHz ttenuation 0- MHz 0. db ntenna to Rx port Rx Operating Frequency Range -0 MHz 0. db 0-0 MHz 0. db 0-0 MHz. db 0-0 MHz 0. db 0-0 MHz. db 0-0 MHz 0. db MHz. db MHz db 0-0 MHz. db 0-0 MHz. db RX 0 0 MHz Rx Insertion Loss.. db Input VSWR at RX port : ttenuation 0- MHz. db Noise Power from TX to Rx port -0 MHz 0. db 0-0 MHz. db 0-0 MHz 0. db 0-0 MHz 0. db 0-0 MHz. db 0-0 MHz. db -00 MHz. db 00- MHz 0. db 00-0 MHz 0. db 0-0 MHz 0. db 0-0 MHz. db Noise Power 0-0 MHz - - dbm/hz Coupling port 0-0MHz - - dbm/.mhz Coupled power Measured after db attenuator 0 dbm

5 Footprint 0. y 0. ➀ ➃ ➂ Top View ➄ ➁ ➅ ➆ ➇ x x y x y ➀.0.0 ➄.. ➁. 0.0 ➅. 0. ➂.0. ➆. 0. ➃.. ➇ Notes :. Dimensions in millimeters. ll GND pins are merged into center ground. Radius of non-ground circle is 0.mm. Center position of non-ground circle Pin Description Pin # Name Description Pin # Name Description Ven Module on/off control GND Ground GND Ground GND Ground GND Ground RX DPX RX output GND Ground GND Ground CPL TX Power Coupling Output VCC DC Supply Voltage GND Ground VCC DC Supply Voltage GND Ground GND Ground GND Ground RFIN TX RF Input GND Ground Vmode0 Mode Control Voltage 0 NT ntenna 0 Vmode Mode Control Voltage

6 Package Dimensions (all dimensions are in millimeter) Pin 0.0 Marking Specification VGO FEM-0 PYYWW Pin Identification Manufacturing Part Number Lot Number P Manufacturing info YY Manufacturing Year WW Work Week ssembly lot number

7 Metallization module outline connected to different layer through via. Please see note 0. Via on 0. pitch 0 line G W 0. G W 0 line 0. Note G W : 0. 0 line Solder Mask Opening module outline Solder Plate Stencil perture module outline Notes :. Dimensions in millimeters. W and G adjusted for Zo=0Ω (CPW type is preferable). Extended Ground area and VIs are required for better Tx/Rx isolation. Rx signal line and nt signal line should be at the different layer with proper isolation by GND for better Tx/Rx isolation 0.

8 Evaluation Board Schematic Vcc C.uF C 000pF RX Vcc C.uF C 00pF RF Vmode0 Vmode Ve C 00pF C 00pF C 00pF 0 RF Vcc Vcc RX Vmode0 NT 0 Vmode Ven CPL ntenna Power Detector Evaluation Board Description RX C C C C RF In C NT C C Coupler Ven Vmode Vmode0 Vcc Vcc

9 Tape Drawing Part Orientation in Tape VGO FEM-0 PYYWW df

10 Reel Drawing (all dimensions are in millimeters) FRONT SIDE Notes:. Material: : Polystrene. Surface Resistivity : < 0E OHMS/SQ Method : STM D- at 0% RH. Static Decay : < Secs at 0% RH BCK Tape Width T W W W mm. ± MX

11 Handling and Storage ESD (Electrostatic Discharge) Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, destructive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. MSL (Moisture Sensitivity Level) Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. vago Technologies follows JEDEC Standard J-STD 00B. Each component and package type is classified for moisture sensitivity by soaking a known dry package at various temperatures and relative humidity, and times. fter soak, the components are subjected to three consecutive simulated reflows. The out of bag exposure time maximum limits are determined by the classification test describe below which corresponds to a MSL classification level to according to the JEDEC standard IPC/JEDEC J-STD-00B and J-STD- 0. FEM-0 is MSL. Thus, according to the J-STD-0 p. the maximum Manufacturers Exposure Time (MET) for this part is hours. fter this time period, the part would need to be removed from the reel, de-taped and then re-baked. MSL classification reflow temperature for the FEM-0 is targeted at 0 C +0/- C. Figure and table on following page shows typical SMT profile for maximum temperature of 0 +0/- C. Moisture Classification Level and Floor Life MSL Level Floor Life (out of bag) at factory ambient =< 0 C/0% RH or as stated Unlimited at =< 0 C/% RH year a weeks hours hours hours a hours Mandatory bake before use. fter bake, must be reflowed within the time limit specified on the label Note :. The MSL Level is marked on the MSL Label on each shipping bag.

12 Reflow Profile Recommendations tp T P RMP UP CRITICL ZONE T L TO T P TEMPERTURE T L Ts max Ts min ts PREHET RMP DOWN t L t C TO PEK TIME Typical SMT Reflow Profile for Maximum Temperature = 0 +0/- C Profile Feature Sn-Pb Solder Pb-Free Solder verage ramp-up rate (TL to TP) C/sec max C /sec max Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) 00 C 0 C 0-0 sec 0 C 00 C 0-0 sec Tsmax to TL - Ramp-up Rate C /sec max Time maintained above: - Temperature (TL) - Time (TL) C 0-0 sec C 0-0 sec Peak temperature (Tp) 0 +0/- C 0 +0/- C Time within C of actual Peak Temperature (tp) 0-0 sec 0-0 sec Ramp-down Rate C /sec max C /sec max Time C to Peak Temperature min max. min max.

13 Storage Condition Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is months at <0 C and 0% relative humidity (RH) J-STD-0 p.. Out-of-Bag Time Duration fter unpacking the device must be soldered to the PCB within hours as listed in the J-STD-00B p. with factory conditions <0 C and 0% RH. Baking It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are C for hours J-STD-0 p.. CUTION Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, detaped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking). Board Rework Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 00 C. This method will minimize moisture related component damage. If any component temperature exceeds 00 C, the board must be baked dry per - prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. ny SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. Removal for Failure nalysis Not following the above requirements may cause moisture/reflow damage that could hinder or completely prevent the determination of the original failure mechanism. Baking of Populated Boards Some SMD packages and board materials are not able to withstand long duration bakes at C. Examples of this are some FR- materials, which cannot withstand a hr bake at C. Batteries and electrolytic capacitors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake temperature from Table - in J-STD 0; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC- and IPC-. Derating due to Factory Environmental Conditions Factory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient environmental conditions. safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. This approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 0 C/0% RH. solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials ref. JESD-0). Recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. Table on following page lists equivalent derated floor lives for humidities ranging from 0-0% RH for three temperature, 0 C, C, and 0 C. This table is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in calculating this table:. ctivation Energy for diffusion = 0.eV (smallest known value).. For 0% RH, use Diffusivity = 0.exp ( -0.eV/kT) mm/s (this used smallest known 0 C).. For >0% RH, use Diffusivity =.0exp ( -0.eV/kT) mm/s (this used largest known 0 C).

14 Recommended Equivalent Total Floor Life 0 C, C & 0 C For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified) Maximum Percent Relative Humidity Package Type and Body Thickness Body Thickness. mm Including PQFPs > pin, PLCCs (square) ll MQFPs or ll BGs mm Body. mm Thickness <. mm including PLCCs (rectangular) - pin SOICs (wide body) SOICs 0 pins, PQFPs 0 pins Body Thickness <. mm including SOICs < pin ll TQFPs, TSOPs or ll BGs < mm body thickness Moisture Sensitivity Level % 0% 0% 0% 0% 0% 0% 0% 0% 0% Level a Level Level Level Level a Level a Level Level Level Level a Level a Level Level Level Level a C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C 0 C C 0 C

15 For product information and a complete list of distributors, please go to our web site: vago, vago Technologies, and the logo are trademarks of vago Technologies, Limited in the United States and other countries. Data subject to change. Copyright 00 vago Technologies Limited. ll rights reserved. V0-0EN - October, 00