ACPM-7331 UMTS1900 4x4 Power Amplifier Module ( MHz) Data Sheet

Transcription

1 ACPM- UMTS x Power Amplifier Module (-MHz) Data Sheet Description Features The ACPM-, a Wide-band Code Division Multiple Access(WCDMA) Power Amplifier (PA), is a fully matched -pin surface mount module developed for WCDMA handset applications. This power amplifier module operates in the -MHz bandwidth. The ACPM- meets the stringent WCDMA linearity requirements for output power of up to.dbm. The ACPM- is also developed to meets HSDPA specs. Mode Control pins are provided for high efficiency improvement of the low output power range. The ACPM- is self contained, incorporating ohm input and output matching networks. Excellent linearity Low quiescent current High Efficiency % at Pout=.dBm % at Pout=dBm % at Pout=dBm (without DCDC Converter) -pin surface mounting package ( mm x mm x. mm) Internal ohm matching networks for both RF input & output Functional Block Diagram cc() Applications WCDMA handset (HSDPA) RF Input () Input Match DA Inter Stage Match PA Output Match RF Output () cc () Bias Circuit & Control Logic MMIC MODULE mode () mode () en () This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime. ACPM- Revision Date: May, Revision Number: DS. Preliminary Data Sheet

2 Table. Absolute Maximum Ratings [] Parameter Symbol Min. Normal Max. Unit RF Input Power Pin. dbm DC Supply oltage cc.. Enable oltage en.. Mode Control oltage mode.. mode.. Storage Temperature Tstg - + Table. Recommended Operating Conditions Parameter Symbol Min. Normal Max. Unit DC Supply oltage cc... PA Enable en... Mode Control oltage High Power Mode Mid Power Mode Low Power Mode mode mode mode mode mode mode Operating Frequency Fo MHz Case Operating Temperature To - Table. Power Range Truth Table [] Power Mode Symbol en mode mode Range High Power Mode PR High Low Low ~ dbm Mid Power Mode PR High High Low ~ dbm Low Power Mode PR High High High ~ dbm Shut Down Mode Low - Notes:. No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value.. High (..), Low (..).

3 Table. Electrical Characteristics for WCDMA Mode (cc=., en=., T= ) [] Characteristics Symbol Condition Min. Typ. Max. Unit Operating Frequency Range F MHz Gain_hi High Power Mode, Pout=. dbm. db Gain Gain_mid Mid Power Mode, Pout=. dbm db Gain_low Low Power Mode, Pout=. dbm db PAE_hi High Power Mode, Pout=. dbm. % Power Added Efficiency PAE_mid Mid Power Mode, Pout=. dbm % PAE_low Low Power Mode, Pout=. dbm % Icc_hi High Power Mode, Pout=. dbm Total Supply Current Icc_mid Mid Power Mode, Pout=. dbm Icc_low Low Power Mode, Pout=. dbm Iq_hi High Power Mode Quiescent Current Iq_mid Mid Power Mode Iq_low Low Power Mode Ien_hi High Power Mode. Enable Current Ien_mid Mid Power Mode. Ien_low Low Power Mode. Imode_mid Mid Power Mode. Control Current Imode_low Low Power Mode. Imode_low Low Power Mode. Total Current in Power-down mode Ipd en=. µa MHz offset ACLR in High power mode [] MHz offset ACLR_hi ACLR_hi High Power Mode, Pout=. dbm MHz offset ACLR in Mid power mode [] MHz offset ACLR_mid ACLR_mid Mid Power Mode, Pout=. dbm MHz offset ACLR in Low power mode [] MHz offset ACLR_low ACLR_low Low Power Mode, Pout=. dbm Harmonic Suppression Second Third f f High Power Mode, Pout=. dbm Input SWR SWR :.: Stability (Spurious Output) S SWR :, All phase - Noise Power in Rx Band RxBN High Power Mode, Pout=. dbm - dbm/hz Ruggedness Ru Pout<.dBm, Pin<dBm, All phase High Power Mode : SWR Phase discontinuity Ph mid_hi Ph low_mid Mid <> Hi at Pout=.dBm Low <> Mid at Pout=.dBm Degree Degree Notes:. Electrical characteristics are specified under WCDMA modulated( GPP Uplink DPCCH + DPDCH ) signal. ACP is expressed as a ratio of total adjacent power to signal power, both with.mhz bandwidth at specified offsets.

4 Table. Electrical Characteristics for HSDPA Mode (cc=., en=., T= ) [] Characteristics Symbol Condition Min. Typ. Max. Unit Operating Frequency Range F MHz Gain_hih High Power Mode, Pout=. dbm. db Gain Gain_midh Mid Power Mode, Pout=. dbm db Gain_lowh Low Power Mode, Pout=. dbm db PAE_hih High Power Mode, Pout=. dbm. % Power Added Efficiency PAE_midh Mid Power Mode, Pout=. dbm % PAE_lowh Low Power Mode, Pout=. dbm % Icc_hih High Power Mode, Pout=. dbm Total Supply Current Icc_midh Mid Power Mode, Pout=. dbm Icc_lowh Low Power Mode, Pout=. dbm MHz offset ACLR in High power mode [] MHz offset ACLR_hih ACLR_hih High Power Mode, Pout=. dbm MHz offset ACLR in Mid power mode [] MHz offset ACLR_midh ACLR_midh Mid Power Mode, Pout=. dbm MHz offset ACLR in Low power mode [] MHz offset ACLR_lowh ACLR_lowh Low Power Mode, Pout=. dbm Notes:. Electrical characteristics are specified under HSDPA modulated Up-Link signal (DPCCH/DPDCH=/, HS-DPCCH/DPDCH=/). ACP is expressed as a ratio of total adjacent power to signal power, both with.mhz bandwidth at specified offsets

5 Evaluation Board Description cc RF In C.uF C pf cc RF In cc GND C pf C.uF cc mode mode en C pf C pf C pf mode mode en RF Out GND GND RF Out Figure. Evaluation Board Schematic C C C C AAGO ACPM- PYYWW AAXXXXXX C C C Figure. Evaluation Board Assembly Diagram

6 Package Dimensions and Pin Descriptions Pin Mark. TYP. ±. +/-. TOP IEW. +/-. SIDE IEW.. Pin # Name Description. cc Supply oltage... RF In mode RF Input Control oltage mode Control oltage en Enable oltage GND Ground GND Ground RF Out RF Output. GND Ground cc Supply oltage X-RAY BOTTOM IEW PIN DESCRIPTIONS Figure. Package Dimensional Drawing and Pin Descriptions. Notes:. All dimensions are in millimeters. Dimensions without tolerance:.xx +/-.mm

7 Package Dimensions and Pin Descriptions, continued Pin Mark AAGO ACPM- PYYWW AAXXXXXX Manufacturing Part Number Lot Number P Manufacturing info YY Manufacturing Year WW Work Week AAXXXXXX Assembly Lot Number Figure. Marking Specifications.

8 PCB Design Guidelines The recommended ACPM- PCB Land pattern is shown in Figure and Figure. The substrate is coated with solder mask between the I/O and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. Stencil Design Guidelines A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown in Figure. Reducing the stencil opening can potentially generate more voids. On the other hand, stencil openings larger than % will lead to excessive solder paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads.considering the fact that solder paste thickness will directly affect the quality of the solder joint,a good choice is to use laser cut stencil composed of.mm(mils)or.mm(mils) thick stainless steel which is capable of producing the required fine stencil outline Figure. Metallization Ø.mm on.mm pitch... Figure. Solder Mask Opening Figure. Solder Paste Stencil Aperture

9 Tape and Reel Information AAGO ACPM- PYYWW AAXXXXXX Dimension List Annote Milimeter Annote Milimeter A.±. P.±. B.±. P.±. K.±. E.±. D.±. F.±. D.±. W.±. P.±. T.±. P.±. Figure. Tape and Reel Format mm x mm.

10 Reel Drawing BACK IEW FRONT IEW Figure. Plastic Reel Format (all dimensions are in millimeters)

11 Handling and Storage ESD (Electrostatic Discharge) Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, destructive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. MSL (Moisture Sensitivity Level) Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. Avago Technologies follows JEDEC Standard J-STD B. Each component and package type is classified for moisture sensitivity by soaking a known dry package at various temperatures and relative humidity, and times. After soak, the components are subjected to three consecutive simulated reflows. The out of bag exposure time maximum limits are determined by the classification test describe below which corresponds to a MSL classification level to according to the JEDEC standard IPC/JEDEC J-STD-B and J-STD-. ACPM- is MSL. Thus, according to the J-STD- p. the maximum Manufacturers Exposure Time (MET) for this part is hours. After this time period, the part would need to be removed from the reel, de-taped and then re-baked. MSL classification reflow temperature for the ACPM- is targeted at +/-. Figure and Table show typical SMT profile for maximum temperature of +/-. Table. ESD Classification Pin # Name Description HBM CDM Classification cc Supply oltage ± ± Class RF In RF Input ± ± Class mode Ground ± ± Class mode Control oltage ± ± Class en Enable oltage ± ± Class GND Ground ± ± Class GND Ground ± ± Class RF Out RF Output ± ± Class GND Ground ± ± Class cc Supply oltage ± ± Class Note :. Module products should be considered extremely ESD sensitive Table. Moisture Classification Level and Floor Life MSL Level a a Floor Life (out of bag) at factory ambient =< oc/% RH or as stated Unlimited at =< oc/% RH year weeks hours hours hours hours Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label Note :. The MSL Level is marked on the MSL Label on each shipping bag.

12 Figure. Typical SMT Reflow Profile for Maximum Temperature = +/- o C Table. Typical SMT Reflow Profile for Maximum Temperature = + / - Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Tsmax to TL - Ramp-up Rate Time maintained above: - Temperature (TL) - Time (TL) Peak temperature (Tp) Time within of actual Peak Temperature (tp) Ramp-down Rate Time to Peak Temperature Sn-Pb Solder /sec max - sec - sec +/- - sec /sec max min max. Pb-Free Solder /sec max - sec /sec max - sec +/- - sec /sec max min max.

13 Storage Condition Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is months at < and % relative humidity (RH) J-STD- p.. Out-of-Bag Time Duration After unpacking the device must be soldered to the PCB within hours as listed in the J-STD-B p. with factory conditions < and % RH. Baking It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are for hours J-STD- p.. CAUTION: Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking). Board Rework Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed. This method will minimize moisture related component damage. If any component temperature exceeds, the board must be baked dry per - prior to rework and/ or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. Removal for Failure Analysis Not following the above requirements may cause moisture/reflow damage that could hinder or completely prevent the determination of the original failure mechanism. Baking of Populated Boards Some SMD packages and board materials are not able to withstand long duration bakes at. Examples of this are some FR- materials, which cannot withstand a hr bake at. Batteries and electrolytic capacitors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake temperature from Table - in J-STD ; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC- and IPC-. Derating due to Factory Environmental Conditions Factory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in Table. This approach, however, does not work if the factory humidity or temperature are greater than the testing conditions of /% RH. A solutions for addressing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials (ref. JESD-A). Recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. Table lists equivalent derated floor lives for humidities ranging from -% RH for three temperature,,, and. This table is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in calculating Table :.Activation Energy for diffusion =.e (smallest known value).. For % RH, use Diffusivity =.exp ( -.e/kt) mm/s (this used smallest known ).. For >% RH, use Diffusivity =.exp ( -.e/kt) mm/s (this used largest known ).

14 Table. Recommended Equivalent Total Floor Life & For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified) Maximum Percent Relative Humidity Package Type and Body Thickness Moisture Sensitivity Level % % % % % % % % % % Level a Body Thickness. mm Including PQFPs > pin, PLCCs (square) All MQFPs or All BGAs mm Body. mm Thickness <. mm including PLCCs (rectangular) - pin SOICs (wide body) SOICs pins, PQFPs pins Body Thickness <. mm including SOICs < pin All TQFPs, TSOPs or All BGAs < mm body thickness Level Level Level Level a Level a Level Level Level Level a Level a Level Level Level Level a... For product information and a complete list of distributors, please go to our web site. Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright Avago Technologies, Pte. All rights reserved