A Burst Mode PN Acquisition Processor for Direct Sequence Spread-Spectrum

Transcription

1 UNIVERSITY OF CALIFORNIA Los Angeles A Burst Mode PN Acquisition Processor for Direct Sequence Spread-Spectrum A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Electrical Engineering by Christopher Ke Hong Deng 1998

2 The thesis of Christopher Ke Hong Deng is approved. Mani Srivastava William J. Kaiser Charles Chien, Co-chair Rajeev Jain, Co-chair University of California, Los Angeles 1998 ii

3 Table of Contents 1. Introduction First Generation Radio Second Generation Radio Direct Sequence Spread-Spectrum Introduction Direct Sequence Spread Spectrum Spreading Codes Direct Sequence Spreading Spectrum and Anti-Jamming PN Acquisition in Spread Spectrum Theory of Direct Sequence PN Acquisition Architectures of the PN Acquisition Loop Frequency Offset Effects in PN Acquisition Loop Performance of Serial PN Acquisition Loop The Average Acquisition Time Probabilities in the acquisition process Numerical Results for Mean Acquisition Time Performance of Matched Filters PN Acquisition Loop...26 iii

4 3. Implementation Methodology Design Goals VHDL Coding Netlist Optimization Compiler ASIC Layout Automation Integrated Circuits Implementation Matched Filters Implementation Adders In Matched Filters Multipliers In Matched Filters Squaring Circuits Integrate and Dump Module PN Code Generator Module Finite State Machines and Controls Pipelining Strongest Multipath Detection Fixed-Point Optimization PN Acquisition Loop Testing Features Synthesized IC Area and Power Testing...55 iv

5 5.2.1 Functional and Timing Critical Path Conclusion...63 A. Appendix A...65 A.1 Features:...65 A.2 Input Pins...66 A.3 Output Pins...66 A.4 Addresses...67 A.4.1 A.4.2 A.4.3 ADDS[3:0] addressing scheme...67 DBG_ADRS[2:0] addressing scheme...68 Node Names and Descriptions...69 A.5 Chip Pin Outs...70 References...72 v

6 List of Figures Figure 1-1 First Generation Adaptive DSSS Wireless Radio...3 Figure 1-2 System Architecture for the Second Generation Radio...4 Figure 1-3 PN Generators...5 Figure 1-4 Spread Spectrum in Frequency Domain...7 Figure 2-1 Figure 2-2 Different PN Acquisition Architectures...10 Non-coherent Multiple Dwell Serial Correlator PN Acquisition Loop...11 Figure 2-3 Figure 2-4 Plot of function [2(1-cos(x))/x2]...14 Discrete Time - State Diagram of Markov Process for PN Acquisition...16 Figure 2-5 Figure 2-6 State H1 Expanded...17 Analytical Results of Mean Tacq for Serial Correlator...23 Figure 2-7 Simulations of Serial Correlator PN Acquisition Loop...24 Figure 2-8 Probabilities of False Alarm and Detect...25 Figure 2-9 Figure 2-10 Figure 2-11 Figure 2-12 Matched Filter PN Acquisition Loop...26 Analytical Results of E[Tacq] for MF PN Acquisition...27 Simulation Results of Tacq for MF PN Acquisition...28 Serial vs. Matched Filters Acquisition at Optimal Thresholds...29 vi

7 Figure 3-1 Implementation Process using Design Automation Tools...31 Figure 3-2 Behavioral VHDL Coding...32 Figure 3-3 RTL Coding of Figure Figure 3-4 Figure 3-5 Component Instantiation in VHDL...33 Divide-and-Conquer Netlist Compile Strategy...36 Figure 4-1 Implementation Forms of FIR Filters...38 Figure 4-2 Two Samples per Chip Four Tap Matched Filter...39 Figure 4-3 Adaptive Length Matched Filter...40 Figure 4-4 An Eight Tap Matched Filter Example...41 Figure 4-5 Figure 4-6 Figure 4-7 A Matched Filter Tap In Detail...42 Squarer Array for 2 s Complement numbers...43 An Integrate and Dump Circuit...44 Figure 4-8 Programmable PN Code Generator...45 Figure 4-9 Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13 State Machine for PN Acquisition Process...46 Pipelining the PN Acquisition Loop...47 State Machine for Finding Strongest Multipath...49 Fixpoint Simulations...51 ASIC Testing Setup for Built-In Self Tests...52 Figure 4-14 SBST Number Figure 4-15 SBST Number Figure 5-1 Layout Snapshot of PN Acquisition ASIC in 0.5µm CMOS...55 Figure 5-2 Self Test Number 1 for Matched Filters...56 vii

8 Figure 5-3 Layout Timing Backannotated Simulations for PN AcquisitionTest. (a) Serial Acquisition Mode using half chip skip (b) Serial Acquisition Mode using full chip skip (c) Matched Filters Acquisition under multipath conditions Figure 5-4 Maximum Path Timing Report...59 Figure 5-5 Minimum Path Timing Report...61 viii

9 List of Tables Table 1-1. Gold Code Correlation Bounds...6 Table 2-1. Parameters for Computation...21 Table 3-1. Table 4-1. Table 5-1. Design Goals...31 XOR Truth Table...41 Specifications for PN Acquisition Chip...54 ix

10 ACKNOWLEDGMENT I would like to thank Dr. Charles Chien for his abundant amount of technical input in all of my research. I am also grateful for Dr. Chien s guidance and criticism on my scientific language and responsibilities. In addition, I would like to thank my adviser, Professor Rajeev Jain, for giving me the opportunity to work with a tremendous group of researchers. My thanks also extends to other members of my thesis committee: Professor Mani Srivastava and Professor William Kaiser. Amongst my graduate student and staff colleagues, I would like to thank Vipin Agrawal for his patience and many long hours of discussions on general theories of communications and signal processing, and the meaning of life and project goals; Richard Au and Greg Bringer for their helpful insights on RF sections of a wireless radio and proofreading my thesis; Paul Lettieri for proofreading my thesis; Joey Chen and Stephen Molloy for their inputs on VHDL, Synopsys, Epoch, and Xilinx FPGAs. x

11 ABSTRACT OF THE THESIS A Burst Mode PN Acquisition Processor for Direct Sequence Spread-Spectrum by Christopher Ke Hong Deng Master of Science in Electrical Engineering University of California, Los Angeles, 1998 Professor Charles Chien, Co-chair Professor Rajeev Jain, Co-chair In asynchronous and packet networks adopting direct sequence spread spectrum, a fast PN acquisition loop is essential. Rapid acquisition processors in burst transmissions can significantly reduce the amount of overhead used for preambles to achieve a higher network throughput. This thesis begins with some basic architectures for PN acquisition. The fundamentals of a noncoherent structure for PN acquisition are described mathematically for an additive white Gaussian noise channel. Simulation results are collected to verify theoretical analysis and performance trade-off for different architectures. To achieve a mean acquisition time of less than 10 bits over a wide range of chip-to-noise ratios, the matched filter acquisition architecture is selected. xi

12 To synthesize the PN acquisition loop, current technologies in design automation are used. An overview of what entails in this design automation process is first explained. Then, the matched filter PN acquisition loop is described in RTL VHDL code. A logic synthesizer is used to map VHDL to standard cells in 0.5µm CMOS. The standard cell netlist is placed and routed using a commercial tool. With a clock frequency of 20 MHz, the estimated power dissipation is 140 mw at 3.3 volts and the estimated chip area is 4.6mm x 5.1mm. xii

13 Chapter 1 Introduction In the past decade, the wireless communications market has shown steady and rapid increase in commercial demand. Recently, spread-spectrum techniques have been adopted to solve congestion in wireless services, an example of which is IS-95, a spreadspectrum based digital cellular standard for North America. Furthermore, spread-spectrum schemes have additional benefits in security, anti-jamming, and robustness to multipath fading. Spread-spectrum (SS) in general includes three types: frequency hop (FH), time hop (TH), and direct sequence (DS). FHSS transmits at baseband bandwidth and hops the RF frequency in a pseudo-random pattern. THSS is similar to FHSS except hopping occurs in the time domain. DSSS is a technique where a pseudo-random sequence, or pseudo-noise (PN), modulates the baseband signal. The PN sequence has a much greater bandwidth than the baseband signal which provides frequency diversity in multipath Page 1

14 fading. To demodulate DSSS signals, the received PN sequence must be aligned with the receiver PN sequence. When the sequences are aligned by the receiver, the receiver has acquired the received PN sequence. Since demodulation cannot be performed before DSSS acquisition, rapid acquisition can significantly reduce the overhead used for preambles to achieve higher network throughput. Fast synchronization of direct sequence spread spectrum PN sequences using low complexity and low power architectures is a challenge. This research focuses on performance evaluation of different PN acquisition techniques and architecture design for fast and low power PN acquisition loops. 1.1 First Generation Radio To demonstrate the benefits of spread-spectrum in wireless multimedia applications, a direct sequence spread spectrum radio was implemented [21] [22]. This DSSS radio with coherent BPSK modulation and a digital IF Costas loop was developed at UCLA. The radio, shown in Figure 1-1, has off-chip A/D converters and standard ISA and PC104 bus connections for interface to a multimedia processing unit. Despite the spread-spectrum benefits demonstrated by the UCLA DSSS radio, the radio needed improvements in asynchronous packet networks. In asynchronous packet networks, burst mode transmissions will send many packets in a short amount of time. The preambles in each packet should be kept as small as possible for higher network throughput. The first UCLA DSSS radio lacked the fast acquisition capabilities required Page 2

15 for burst mode transmissions. Furthermore, the first generation radio did not provide multi-megabit transmission rates required by multimedia applications. RF board DSSS Modem PC104 bus interface ISA bus interface Figure 1-1. First Generation Adaptive DSSS Wireless Radio 1.2 Second Generation Radio A system architecture for a multimedia spread-spectrum that combines direct sequence with frequency hop has been adopted. Figure 1-2 shows this system architecture. One of the many research areas for the second generation radio is to support burst mode transmissions in an asynchronous packet network by using rapid PN acquisition in direct sequence spread spectrum. Page 3

16 Modem RF DSSS FHSS Link Layer Controls Figure 1-2. System Architecture for the Second Generation Radio 1.3 Direct Sequence Spread-Spectrum Introduction Spread-spectrum transmission uses a wider band signal over the channel than the original message bandwidth. In direct sequence spread spectrum, the widening of the message bandwidth is accomplished by mixing the message signal with a pseudo-random signal which is much wider in bandwidth. This mixing action is a phase modulation of the original message signal. Since the receiver must be able to demodulate the spread signal, the spreading signal can never be truly random -- hence the term pseudo-random. The spreading signal for DSSS is often called the spreading code or PN sequence Direct Sequence Spread Spectrum Spreading Codes The spreading codes must be periodic in order to be suited for DSSS. In addition, the codes must also follow two other constraints: i. The autocorrelation peak must be much greater than the autocorrelation sidelobes and cross correlation peaks. ii. The code sequence can be easily generated. Page 4

17 While there exist many different classes of codes that are well suited for DSSS, one popular class of codes are the maximal length (ML) sequences [4]. The ML codes are cyclical with a period of L=2 n -1, where n denotes the order of the ML code. The autocorrelation peak of the ML codes is also 2 n -1. One feature of the ML codes that make them well suited for DSSS is their low autocorrelation sidelobe, which is -1. ML cross correlations are also low as compared to the autocorrelation peak. Another advantage of ML codes is their ease of generation, requiring only shift registers and XOR gates. Figure 1-3a shows an order 5 ML code generator. However, one disadvantage of ML codes is that there are very few different ML codes for a given order of codes, thus limiting the number of multiple access users available. (a) ML Sequence Generator (b) Gold Sequence Generator Figure 1-3. PN Generators = Modulo 2 Adder Page 5

18 The restriction of ML codes is overcome by Gold codes. The Gold codes are actually XOR combinations of a preferred pair ML codes of the same order -- an order n Gold code consists of two order n ML codes. Figure 1-3b shows the generator for Gold codes. There are (2 n +1) different Gold codes, including the two ML codes, for every preferred pair of ML codes of order n [5]. The preferred pair of ML codes of order n will produce Gold codes with autocorrelation sidelobes and cross correlations with the same upper bounds as shown in Table 1-1. TABLE 1-1. Gold Code Correlation Bounds n Upper Bound Even 2 n/ Odd 2 (n+1)/2 + 1 To achieve spreading, the spreading codes are clocked at a much higher frequency than the message clock. Often, spreading of the message is over one period of the spreading code. Each symbol or bit, since we are only concerned with binary codes, in the spreading code is called a chip [19] Direct Sequence Spreading Spectrum and Anti-Jamming After multiplying the message symbols with the spreading code, the frequency spectrum of the signal transmitted over the channel is significantly wider band than the original message bandwidth. The spreaded spectrum can be visualized as in Figure 1-4. In the case of a narrow band jammer within the spread-spectrum bandwidth, the de-spreading action at the receiver will spread the jamming signal. The demodulator input signal will perceive the spread jammer as low power noise as seen in Figure 1-4. De- Page 6

19 spreading a received signal over a code length L yields a processing gain [19] [21] of L over the jammer power. spreaded signal Jammer De-spreading original signal Jammer Narrow Band Jammer in Spread Spectrum Figure 1-4. Spread Spectrum in Frequency Domain Page 7

20 Chapter 2 PN Acquisition in Spread Spectrum 2.1 Theory of Direct Sequence PN Acquisition PN acquisition is a process by which the receiver attempts to align its local PN sequence s phase to the incoming signal. Since the autocorrelation peak is much greater than the sidelobes, a correlation between the local sequence and the received signal can yield an estimate of whether the sequences are aligned. Such architectures to determine sequence alignments are called PN acquisition loops. The receiver usually stores a threshold to determine if the correlation is the autocorrelation peak where the two sequences are in alignment. When the local PN sequence is determined to be aligned with the incoming signal, the PN acquisition loop is said to have acquired. The PN acquisition loop can make errors in the correlation. Occasionally, the PN acquisition loop can falsely declare that the sequences are aligned when autocorrelation sidelobes exceed the threshold. This is called false alarm of the PN acquisition loop. Fur- Page 8

21 thermore, the PN acquisition loop may also yield a correlation of aligned sequences lower than the stored threshold. A mistake is made by the loop by not declaring acquisition during sequences alignment. This is called a miss by the PN acquisition loop. 2.2 Architectures of the PN Acquisition Loop While many different PN acquisition loop architectures exist, the most common architectures are the serial correlator and the matched filter based architectures. The matched filter has the same structure as a Finite Impulse Response (FIR) filter. Figure 2-1 shows the two different architectures using coherent BPSK modulation. The correlation output of a serial correlator architecture is R( δ) = T s ct ( + δ)gt ()t d T s 0 (2.1) where c(t+δ) is the local PN sequence with δ offset from the incoming signal, g(t) is the incoming signal, and T s is the period of the spreading code. The autocorrelation peak is at R(0). A matched filter, with code phase (t+φ) and input g(t+δ), with output sampled at time T s is exactly equal to the serial correlator output with local sequence c(t+φ) correlating with g(t+δ) over period T s. Every new chip sampling into the matched filter yields a correlation output with a new offset. For serial correlator, however, each new offset value must be computed with integration over the period T s. Therefore, the matched filter can compute code correlations for different offsets much faster than the serial correlator even Page 9

22 though their output values are mathematically equivalent. The disadvantage of matched filters is their complexity. IN > V th yes no LOCK PN GEN SKIP Serial Correlator PN Acquisition Loop IN > V th yes LOCK phase φ enable PN GEN phase φ To De-spread Matched Filter PN Acquisition Loop where V th is the threshold Figure 2-1. Different PN Acquisition Architectures Unfortunately, the architectures mentioned in Figure 2-1 are very prone to false alarms in noisy channels. After a false alarm in acquisition, the receiver will demodulate many symbols before detecting that the PN acquisition loop has made an error. In other words, the PN acquisition false alarm penalty is very high. A simple solution to reduce the false alarm occurrence is to use a multiple dwell PN acquisition loop. In a multiple dwell architecture of size N, a false alarm or acquisition can only occur when N stages of correlators exceed the stored threshold in succession. For a slightly more complicated design, each stage can have its own threshold. For example, in a two stage multiple dwell architecture, false alarm or acquisition occurs after the following two events: Page 10

23 1. The first stage correlator integrates from 1 to N 1 symbols and its output exceeds the threshold thus activating the second dwell. 2. The second stage correlator integrates from 1 to N 2 symbols and its output exceeds the stored threshold. In most cases, a two stage multiple dwell architecture speeds acquisition time by using a small first stage dwell and a large second stage dwell to prevent frequent false alarms (i.e., N 2 > N 1 ). In a wireless system, a noncoherent architecture greatly simplifies the design as compared to the phase lock loop (PLL) required in a coherent architecture. Moreover, a noncoherent receiver does not have the overhead of convergence time for the PLL. Thus, the following designs will only show the noncoherent structure. I ( ) F.S.M. LOCK Q ( ) 2 enable V th PN GEN SKIP Figure 2-2. Non-coherent Multiple Dwell Serial Correlator PN Acquisition Loop Figure 2-2 illustrates a non-coherent serial correlator PN acquisition loop with two stage multiple dwell. Note that the second stage multiple dwell accumulator is located after the square modules. The square and add modules are equivalent to an envelope detector. There is a very important reason for this feature and that is robustness to fre- Page 11

24 quency offset in multiple dwells. 2.3 Frequency Offset Effects in PN Acquisition Loop Frequency offset is present in every oscillator because the quartz crystals cannot be made to exact frequency specifications in practice. Oscillators with 5 parts per million (ppm) of frequency mis-match -- 5 Hz offset in every 1 MHz -- are very common. In addition, RF usage at 2.4 GHz is also on the rise. At such high RF frequencies, the down-converted signal will suffer large amounts of frequency offset. To see how frequency offset can distort the spread spectrum signal, received signal definition is necessary. rt () = ξct () cos( ( w RF + w offset )t + φ) + nt () (2.2) where ξ is the received power, w RF is the RF frequency, w offset is the oscillator offset, φ is the RF phase offset from local oscillator, and n(t) is the channel noise and interference which is approximated to have Gaussian distribution. After RF down-conversion to baseband and low pass filtering, the signal of the inphase channel (or I-channel) is g I () t = ξct () cos( w offset t + φ) + nt () (2.3) where n(t) term contains the RF cosine term. By substituting (2.3) into (2.1), we get Page 12

25 R I ( δ) = t 0 + T s ( ct ( + δ)ct () cos( w T offset t + φ) + nt ()) dt s (2.4) t 0 If δ is exactly zero and the code sequence is binary {c: -1,1} then the spreading code multiplicative term is a constant 1. Neglecting the noise term, (2.4) can be simplified to R I ( 0) = ξ [ sin( w T s w offset ( t 0 + T s ) + φ) sin( w offset ( t 0 ) + φ) ] offset (2.5) Correspondingly, the quadrature channel, Q, produces the cosine terms R Q ( 0) = ξ [ cos( w T s w offset ( t 0 + T s ) + φ) cos( w offset ( t 0 ) + φ) ] offset (2.6) which when square summed with I channel term in (2.5), yields h 2 ( 0) = R I ( 0) 2 + R Q ( 0) 2 (2.7) ξ = ( T s w offset ) 2 [ sin( w offset ( t 0 + T s ) + φ) sin( w offset ( t 0 ) + φ) ] 2 + [ cos( w offset ( t 0 + T s ) + φ) cos( w offset ( t 0 ) + φ) ] 2 (2.7) then simplifies to h 2 ( 0) = 2ξ ( T s w ) 2 [ 1 cos( w offset T s )] offset (2.8) Page 13

26 which is approximately constant signal envelope as long as (w offset T s ) is << 2π. Figure 2-3 shows a graph of (2.8) as a function of (f offset T s ). However, if the multiple dwell is performed before the squarer circuits then y I (0) and y Q (0) will produce different values for consecutive symbols. Therefore, if the multiple dwell is averaged over many symbols before envelope detection to prevent frequent false alarms, the signal envelope can be lowered significantly in magnitude from frequency offset distortions Radians/2π Figure 2-3. Plot of function [2(1-cos(x))/x 2 ] For example, at 2.4 GHz RF with 5 ppm frequency offset the resulting f offset is 12 KHz or about 80 µs period. For a fast spreading bandwidth, or chipping rate, of 10 MHz with 63 chips/symbol using BPSK the symbol period is about 6 µs. That is in about 3 symbols of dwell before envelope detection, either the first or third symbol depending on I or Q channel, will have a 90 degree rotation modulated by frequency offset. In other Page 14

27 words, there is approximately no signal energy on that symbol. On the other hand, if envelope detection is used before dwelling then even with f offset T s of 12KHz*6µs = the envelope is less than 0.02% from ideal magnitude. 2.4 Performance of Serial PN Acquisition Loop Similar to the PLLs, the PN acquisition loops use the convergence time, or the acquisition time (usually the average acquisition time), as a standard measurement of performance. The amount of noise and interference or signal attenuation in the channel, determinates of receiver SNR, are obvious factors that affect the acquisition time. Another important variable in the PN acquisition loop is the acquisition threshold, V th, which can also affect the acquisition time The Average Acquisition Time To compute the average or mean acquisition time for a particular architecture, several variables are required. They are: probability of false alarm, probability of detect, code length, multiple dwell length, false alarm penalty, or the amount of time taken by the receiver to determine a false alarm, and the number of multiple dwell stages. For greater than one dwell stages, the probability of false alarm can be different for each stage. The probability of detect, on the other hand, is defined as a correct decision of the entire loop. Thus, it is the product of the probability of a correct detect of each dwell stage. The PN acquisition loop converges to the correct code phase by examining each code phase by correlation. If the correlated value does not exceed a stored threshold, it Page 15

28 skips to the next code phase and repeat the correlation and compare processes. Although this linear process is easily described, its analysis can become difficult when multiple dwell stages, false alarms, and misses are considered. Fortunately, the PN acquisition process is Markovian and can therefore be described as a Markov chain shown in Figure 2-4. H C (z) H C (z) H P (z) H FA (z) H P (z) H FA (z) ACQ H 1 H D (z) H P (z) False Alarm H FA (z) H M (z) H P (z) H FA (z) H C (z) H M (z) = Transition weight for a miss H D (z) = Transition weight for detect H C (z) = Transition weight for correct skip H P (z) = Transition weight of false alarm penalty H FA (z) = Transition weight for a false alarm Transition weight = Transition Time * Probability of transition Figure 2-4. Discrete Time - State Diagram of Markov Process for PN Acquisition State H 1 is the only possible phase for PN acquisition. For serial correlator case, state H 1 can be considered as the received signal code phase. For a matched filter architecture, the H 1 state corresponds to the code phase of the matched filter. Expanding H 1 state will show multiple dwell states and fractional chip skip states. A two dwell H 1 state with discrete time quantized to one-half of chip period, is shown in Figure 2-5. Page 16

29 H 1 t 2 (δ) t 2 (δ) t 2 (δ) τ: Offset of local sequence to received code T c : Chip duration t 2,m (δ) t 2,m (δ) t 1 (δ) t 1 (δ) t 1 (δ) t 1,m (δ) t 1,m (δ) t 1,m (δ) δ = -T c /2 δ = 0 δ = +T c /2 = Dwell Mode Figure 2-5. State H 1 Expanded where t i (δ) = H D,i (z,δ) = transition weight of δ offset detection on i th dwell, t i,m (δ) = H M,i (z,δ) = transition weight of δ offset miss on i th dwell. By following the transitions on the markov chain a generating function can be obtained. The average acquisition time for uniformly distributed δ [ 0, T s ) using a double dwell architecture can be derived from the generating function as [2] [3] τ 1 + τ 2 P fa, 1 ( 1 + Pt FA P fa, 2 ) T ACQ = T 2P D, 2 P s ( 2 P D, 2 P D, 1 ) + τ 2 D, 1 (2.9) where Pt FA = false alarm penalty, P D,i = probability of detection on the i th dwell, and P fa,i is the probability of false alarm on the i th dwell. (2.9) differs slightly from the mean acquisition time in [2] -- the extra τ 2 term at the end -- because we assume an architecture which requires a second dwell, τ 2, to confirm every acquisition. Page 17

30 2.4.2 Probabilities in the acquisition process Although the derivation of mean acquisition time is independent of the channel, noise, and signal characteristics, the probabilities for false alarm and detection must assume particular distribution functions. To make analysis possible, a simple additive white Gaussian noise, AWGN, channel is assumed. Furthermore, the local sequence offset, δ, from the received signal is assumed to be integer multiples of T c, or the chip period. That is δ = nt c n 0123 L,,, 1 (2.10) For the architecture shown in Figure 2-2, the detected envelope, h(δ), has a Rician distribution function. A Rician distributed signal results from noncoherent envelope detection of Gaussian distributed inputs [7]. In Figure 2-2, only h 2 (δ) is available for further processing because circuits for fast and exact square-root function are currently nonexistent. h 2 (δ) has a noncentral chi square (gamma) probability density function (pdf) with two degrees of freedom. The pdf of h 2 (δ) can be expressed as f X ( x) = 1 µ 2 + x µ x σ 2 exp σ 2 I σ 2 (2.11) where σ 2 is the variance of the Gaussian noise, which is equal in both I and Q channels, µ 2 is the sum of the mean square in both I and Q channels (i.e. µ 2 = µ 2 I + µ 2 Q ) a.k.a. noncentrality parameter of the distribution, and I 0 (.) is the modified bessel function of the first kind of zeroth order. Page 18

31 At the comparator, or the decision maker of acquisition, the probability of a chisquare function greater than a constant can be obtained by integrating (2.11) which yields Ph ( 2 > V th ) = Q( a 1, a 2 ) (2.12) where µ 2 a 1 = σ 2 a 2 = V th σ 2 h 2 (δ) takes on the chi-square distribution as described in (2.11), and Q(.) is the general Marcum Q function defined as Qab (, ) = x b a 2 + x 2 exp I 0 ( ax) dx (2.13) False alarm occurs when a declaration of acquisition is made even though the local and received sequences are not aligned. Since a double dwell scheme is adopted, each of the false alarm probabilities must be calculated separately. Figure 2-2 shows that the first dwell occurs before the squarer circuits, therefore the noncentrality parameter and variance are µ = ξµ ( Rt ()I, + µ Rt ()Q, ) 2 σ 2 σ 1 = τ 1 (2.14) Page 19

32 where µ 2 R(t),I and µ 2 R(t),Q is the mean squared of PN code autocorrelation sidelobes in I and Q channels respectively, and τ 1 is the first dwell length. (2.14) can then be substituted into (2.12) to solve for the probability of false alarm of the first dwell. To combat frequency offset and for rapid code phase search, the first dwell is constraint to one symbol or the processing gain of the spread signal. The probability of false alarm on the second dwell is very similar to the solutions of the first dwell. An important difference between the second and first dwell is that the second dwell is processed after envelope detection. While the first dwell can reduce the variance of a Gaussian distributed signal by the length of the dwell, as shown in (2.14), the same processing does not, in general, apply to chi-square distributed signals. However, an approximation can be made for signals with chi-square pdf where the noncentrality parameter is much greater than its σ 2 (i.e. high SNR) so that equation (2.12) can be used for the second dwell. This approximation is justified as follows. The variance for chi-square distributed h 2 (δ) of the form (2.11) is 2 σ 2 h = 4σ 4 + 4σ 2 µ 2 (2.15) If the assumption that µ is much greater than σ is true, then the first term σ 4 can be ignored. That is 2 σ 2 h 4σ 2 µ 2 µ» σ (2.16) Clearly, if the variance for h 2 (δ) is reduced by averaging in the second dwell, then it is equivalent to reducing the Gaussian variance, σ 2, by the length of the second dwell. Page 20

33 From the approximation in (2.16), the second dwell parameters can be approximated to µ 2 a 1 = σ 2 2 V th a 2 = σ 2 where µ = ξµ ( Rt ()I, + µ Rt ()Q, ) (2.17) 2 σ 2 σ 2 = τ 2 where τ 2 is the second dwell length. By substituting (2.14) and (2.17) into (2.12), the probability of false alarm for first and second dwell can be found respectively. Solving the probability of detect is not unlike the process for false alarm probabilities. In fact, the probability of detect of both dwells is in general Ph ( 2 > V th ) which is the same as (2.12). The only new variable substitution that must be made is to change the noncentrality parameter from autocorrelation sidelobes to the autocorrelation peak value. That is µ = ξ ( R I ( 0) + RQ( 0) ) (2.18) where R(0) is the autocorrelation peak Numerical Results for Mean Acquisition Time Verification of analytical expressions for mean acquisition time for serial correlator architecture is carried out using the following set of parameters: Code Type TABLE 2-1. Parameters for Computation Process Gain False Alarm Penalty τ 1 τ 2 Gold Code 31 10,000 (bits) 1 (bit) 4 (bits) Page 21

34 The false alarm penalty is set very high because the receiver must analyze the incoming data at the networking level, which can take a long time, to detect incoherent messages. Gold codes are chosen for their large number of unique codes. Because the Marcum Q function does not have a closed analytical expression, numerical integration must be used. The computation of the Marcum Q function proves difficult for finite memory computers due to its infinite upper integration limit. This problem is circumvented by realizing that all cdfs are bounded by 1 and chi-square samples are never negative. Thus (2.13) can be re-written as b Qab (, ) = 1 x 0 a 2 + x 2 exp I 0 ( ax) dx (2.19) Using the Simpson s rule [30], the theoretical results for mean acquisition time of a serial correlator architecture in Figure 2-2 is illustrated in Figure 2-6. Numerical integration is performed by dividing each integration interval into 1000 steps and applying Simpson s rule on each step. The simulation results for the serial correlator architecture is shown in Figure 2-7. Hand analysis seems to deviate from simulations at low chip-to-noise ratios (CNR) and high threshold levels. At high threshold levels, the parameter a 2 is large, yielding a large integration interval and step sizes. It s well known that Simpson s rule has errors proportional to the fourth derivative of the function [30]. If the step size is large enough then finite fourth derivative values will cause numerical errors. In the case of low CNRs, data discrepancies are caused by larger step sizes (1/1000 of the integration length) because of Page 22

35 finite precisions in the computer. In addition, the approximation in (2.16), µ 2 >> σ 2, becomes less accurate as CNR decreases V th =1.1 log(e[t acq ]) (Bits) V th =0.3 V th =0.7 V th =0.9 V th = Chip Noise Ratio (db) --o-- Simulations, V th = *-- Simulations, V th = 0.9 Figure 2-6. Analytical Results of Mean T acq for Serial Correlator Optimal threshold is defined as the threshold where the mean acquisition time is very small for a wide dynamic range of CNR. Clearly from Figure 2-6 and Figure 2-7, the higher thresholds are better suited for extremely low CNR because false alarms are reduced. However, at high CNR the higher thresholds tend to miss acquisition of the signal and thus performs poorly. The reason why higher threshold produce many misses at high CNR is because the variance of the signal output at high CNR is small, thus with a high threshold there is only a small probability for the signal to exceed the threshold. In Page 23

36 the case of Figure 2-7, the optimal threshold is about 0.7. Figure 2-8 shows the probabilities associated with the serial correlator PN acquisition loop. Clearly, P fa is much smaller than P d, which is very important for systems that experience large penalties after false alarms. Moreover, the total false alarm is orders of magnitude less than the false alarm probability of the first dwell. This is the benefit of using a double dwell system where frequent mistakes during the first dwell can be corrected without paying hefty penalties log(e[t acq ]) (Bits) V th =0.3 V th =0.5 V th =0.7 V th =0.9 V th = Chip Noise Ratio (db) Figure 2-7. Simulations of Serial Correlator PN Acquisition Loop The serial correlator at optimal threshold can achieve less than 50 bits of mean acquisition time for a 31 chips spread code. Unfortunately, as the code length, or spreading code period (i.e., T s ), increases, (2.9) demands an increase in the mean acquisi- Page 24

37 tion time. One solution to decrease mean acquisition time in a serial correlator architecture is to add parallel serial correlator paths which independently search for the correct code phase. Obviously, this means that a lot of hardware have to be duplicated: the squarer circuits, the dwell circuits, the comparator, the state machine, and the PN generator block. In addition, another controller must exist to govern all the parallel paths. Moreover, for burst mode transmissions, where PN acquisition preamble is very short, the serial correlator architecture may require even more parallel paths and so more duplicated hardware. 0 1 P fa1 P fa P d 2 log(probabilities) V th = Chip Noise Ratio (db) Figure 2-8. Probabilities of False Alarm and Detect Page 25

38 2.5 Performance of Matched Filters PN Acquisition Loop Like the serial correlator architecture in Figure 2-2, the matched filters PN acquisition loop with double dwell is shown in Figure 2-9. I enable Q 0 1 ( ) F.S.M. LOCK 0 1 ( ) 2 enable V th PN GEN Figure 2-9. Matched Filter PN Acquisition Loop Matched filter of the PN code can search each code phase for every input chip. The serial correlator, on the other hand, must integrate over every bit for each code phase. This is quite obvious since the matched filter, when sampled at the correct instance, is mathematically equivalent to the serial correlator. However, the unsampled outputs of the matched filters are extra processing that are not used for acquisition. During the second dwell, only outputs of the detected phase (determined by the first dwell) can be used. Therefore, by inserting additional correlators and placing the matched filters on stand-by mode for the second dwell, energy dissipation can be reduced dramatically. Page 26

39 Furthermore, the architecture in Figure 2-9 is similar to the one in Figure 2-2. The only difference is the replacement of matched filters for the correlators. Therefore, the probability of detect and false alarm are exactly the same as those derived in the previous section. However, the matched filter searches code phases at different rates, its mean acquisition time is different from (2.9). The mean acquisition time for matched filters architecture is T ACQ = MF τ 1 + τ 2 P fa, 1 ( 1 + Pt FA P fa, 2 ) T 2P D, 2 P s ( 2 P D, 2 P D, 1 ) + τ 2 D, 1 (2.20) Instead of τ 1 delay on the first dwell, the matched filter has τ 1 MF delay which equals one chip period or T s /L V th =0.9 log(e[t acq ]) (Bits) V =0.7 th V =0.5 th V th =0.3 V th = Chip Noise Ratio (db) --o-- Simulation, V th =0.7 --*-- Simulation, V th =0.9 Figure Analytical Results of E[T acq ] for MF PN Acquisition Page 27

40 Figure 2-10 and Figure 2-11 shows the analytical and simulation results, respectively. Clearly, matched filters provide extremely fast acquisition of less than 10 bits and also slightly increasing the acquisition dynamic range of about 2 db. For the matched filter architecture, its optimal threshold is now at 0.9 because the high acquisition time at high CNR of V th =0.9 in the serial correlator case is now being reduced to less than 1 bit difference from the 0.7 threshold acquisition curve. Therefore, by using matched filter designs a higher threshold can be used than the corresponding serial correlator architecture and thereby increasing the acquisition dynamic range V th =0.3 V th =0.5 V th =0.7 V th =0.9 V th =1.1 log(e[t acq ]) (Bits) Chip Noise Ratio (db) Figure Simulation Results of T acq for MF PN Acquisition Figure 2-12 confirms the dynamic range increase of using MF acquisition versus a serial scheme. Moreover, the matched filters architecture also experiences up to 30 times improvement in expected acquisition time with higher improvement as channel conditions Page 28

41 degrade Serial Matched Filter log(e[t acq ]) x speed-up Chip Noise Ratio (db) Figure Serial vs. Matched Filters Acquisition at Optimal Thresholds Page 29

42 Chapter 3 Implementation Methodology Traditional methods of silicon implementation entailed manually drawn circuit schematics and hand optimized layouts. While this methodology produces high performance designs, it is extremely tedious and consumes an enormous amount of time. Current technologies in design automation and sub-micron silicon feature size allow fast turn around time from architecture design to layout for implementations that do not require the peak performance offered by sub-micron technology. Since a PN acquisition loop does not require extremely fast circuits, design based on in VHSIC 1 Hardware Description Language (VHDL) synthesis is the preferred implementation methodology. The implementation cycle from VHDL to layout with current design automation tools can be summarized as follows 1. Very High Speed Integrated Circuits. Page 30

43 User Design Constraints (Area, Speed) VHDL Netlist Optimization Compiler (Synopsys ) Technology Library Optimized netlist (mapped to technology library standard cells) Layout Compiler (Epoch ) Design Constraints (Area, Speed) Timing/Buffering and power estimation Layout File (CIF or GDSII) Figure 3-1. Implementation Process using Design Automation Tools 3.1 Design Goals Implementation specifications for the PN acquisition integrated circuit chip are shown in Table 3-1. TABLE 3-1. Design Goals Clock Frequency (sampling rate) 20 MHz Samples per chip of spreading code 2 Page 31

44 3.2 VHDL Coding TABLE 3-1. Design Goals Max. Chip Area 6 x 6 mm 2 Fixed point sign method 2 s complement Process Gain adaptability 15, 31, 63, 127 There are several levels of VHDL coding. At the highest level, VHDL can be written as a description of the algorithm. This is known as behavioral level coding. An example of behavioral coding style is shown in Figure 3-2. In this example, the VHDL code does not imply how many adders or clock cycles are required to complete the operation. for k in 0 to 2 loop C(k) <= A(k) + B(k) end loop; Figure 3-2. Behavioral VHDL Coding The next level of VHDL coding is Register Transfer Level or RTL coding style. In RTL coding, the VHDL is written to describe the architecture of a design. VHDL using RTL implicitly defines registers, muxes, and datapath modules (such as adders and multipliers). For example, if the behavioral VHDL in Figure 3-2 is written in RTL, then its VHDL coding 1 is as shown in Figure 3-3. The RTL code in Figure 3-3 has defined an architecture which requires three clock cycles with only one adder and some control logic to complete the operation. Behavioral 1. The index k in Figure 3-3 VHDL RTL code is assumed to have some initial reset not shown in the example. Page 32

45 coding, however, leaves the architecture design to the compiler -- it is up to the behavior compiler to determine the trade off of number of clock cycles and adders from user constraints. wait clk event and clk= 1 ; C(k) <= A(k) + B(k); k <= k + 1; Figure 3-3. RTL Coding of Figure 3-2 Behavioral and RTL coding styles can only infer components from a technology library. They are technology library independent. As shown in the previous two figures, no part of the VHDL specifies what type of gates should be used to implement the architecture. Component instantiation, the lowest level of VHDL coding, specifies exactly how cells from a technology library are applied to a design. In other words, instantiating components in VHDL restricts the design to only one implementation. Figure 3-4 shows components instantiated using VHDL. U0: std_and2_2x port map(in0=>a, IN1=>b, OUT=>c); U1: std_dff_1x port map(reset=>asyn_reset, CLOCK=>clk, D=>c, Q=>o, Q_BAR=>o_bar); Figure 3-4. Component Instantiation in VHDL The benefit of using this low level of coding style by instantiating components Page 33

46 from a technology library is to offer excellent user customization on the design. However, in order to have some flexibility on technology upgrades and also controls on architecture implementation, RTL coding style is chosen. 3.3 Netlist Optimization Compiler Synopsys Design Compiler (DC) by Synopsys Inc. is used as the VHDL compiler for RTL style codes. Like all CAD tools, DC requires a designer to enter the performance and cost information. Figure 3-1 shows that clock speed and chip area are common design constraints set by the user to guide DC during netlist optimization. To increase the clock speed, DC may choose to implement one of the following schemes: 1. Increase buffer area or insert additional buffers to reduce capacitive loads on heavily loaded nets. 2. Use a different implementation for modules. For example, replace carry-ripple adders with carry look-ahead adders. 3. Add parallelism to the constrained datapaths. The area and speed trade-off compile implies that the above schemes be computed for all modules in an ASIC concurrently. Due to limitations in computational hardware, a single pass compile for a large ASIC is not feasible. For instance, using today s state-ofthe-art workstation, a Sun UltraSPARC with 256 MB of RAM, a 50K logic gate design can not be completed in one pass with reasonable optimization and time. One solution to these computational restrictions is a divide-and-conquer concept. Page 34

47 First, the design is partitioned into many blocks. Then each of the blocks are compiled separately by making assumptions on the connections they have to other blocks. These assumptions can be improved by exploring the design during the first phase of compile. For optimal results, an initial layout can be made with layout information backannotated into the netlist compiler for another compile. This divide and conquer strategy is demonstrated in a flow chart in Figure ASIC Layout Automation Epoch, by Cascade Design Automatic Corp., is a commercial automated layout compiler that suits this design process well. Moreover, Cascade provides a technology library for Epoch that is also compatible with Synopsys. Since most of the user interventions are to constraint the netlist optimization in DC, layouts in Epoch is fairly automated. The layout task that requires the most user intervention is for the designer to choose the proper pinouts on an ASIC package. Page 35

48 Initial Design Exploratory Compile 1 Use approximations of constraints to re-compile 2 Is the design acceptable? Yes Layout Compiler No 3 Use results and constraints yielded from step 2 and re-compile Is the design acceptable? Yes No Do an initial/improved layout and backannotate to netlist compiler 4 Loosen Constraints No Is the design acceptable? Yes Figure 3-5. Divide-and-Conquer Netlist Compile Strategy Page 36

49 Chapter 4 Integrated Circuits Implementation 4.1 Matched Filters Implementation The matched filters in the PN acquisition loop are very similar to Finite Impulse Response (FIR) filters. In fact, the matched filters are exactly like FIR filters except that the coefficients of the matched filters are neither symmetric nor anti-symmetric. The coefficients of the matched filters are the spread-spectrum sequence bits. Since the matched filters are a type of FIR filters, the two possible FIR architectures can be adopted for matched filters as well. These two architecture, Direct form and Transpose form [5] [20], are shown in Figure 4-1. The direct form architecture has the advantage of small loading on the input -- a register and a coefficient multiplier. On the other hand, the bold line show that the critical timing path for the direct form is very long -- through many adders and a multiplier. To meet a fast clocking rate, a shorter timing path is required. This specification can be met Page 37

50 by using the transpose form which has a critical path of one multiplier and an adder. However, the transpose form has a large loading effect on the input which can be solved by proper buffering. i(0) i(-n+1) c(n-1) c(0) (a) Direct Form of FIR Architecture i(0) c(n-1) c(0) (b) Transpose Form of FIR Architecture Figure 4-1. Implementation Forms of FIR Filters Implementation of a matched filter in transposed form differs from direct form by the orientation of the coefficient sequence. The correlation for direct form and transpose form FIR filters can be expressed as (4.1) and (4.2), respectively. Direct Form = 0 k = N + 1 ik ( )cn ( 1 + k) (4.1) 0 Tranpose Form = ik ( )c( k) (4.2) k = N + 1 where c(k) s are the FIR coefficients. This small difference is not important for linear phase FIR filters which have symmetric or anti-symmetric coefficients. However, in a Page 38

51 matched filter with PN codes as coefficients, the coefficient orientation must be in the correct sense to detect correlation peaks. In order to avoid additional complexity in the matched filters, linear shift registers (LSR) are used to store the PN sequences as coefficients. Moreover, the PN codes are generated from a PN generator. From equations (4.2) and Figure 4-1b, the first PN chip generated must reside at the (N-1) register of the LSR pipeline for transposed form. Another challenge of the matched filters is the input sampling rate of two samples per chip. At this rate, the number of taps in the matched filter must be twice as long as the code length for a full correlation. In Figure 4-2, a two chip PN code yields a four tap matched filter with two samples per chip. Because the input clock rate is twice as high as the chipping rate, the registers that store the PN coefficients must be clocked at half the rate of the input clock frequency. IN c(0) c(1) Figure 4-2. Two Samples per Chip Four Tap Matched Filter Besides the two times sampling rate, the matched filters must also be able to adapt to different PN code lengths. The solution is to construct a filter capable of handling the longest code length and select different taps, through multiplexing, to truncate the perceived filter length. Figure 4-3 shows an example of the actual implementation for adapting code lengths of four, five, and six taps in a matched filter. Page 39

52 Since matched filters are complex modules, 126 tapped matched filters were implemented to satisfy ASIC area constraints. With two samples per chip, the maximum process gain of 127 (21 db) chips will only receive a partial correlation when matched filters are used for PN acquisition. Nevertheless, a process gain of 21 db is fairly high and even with partial correlation of 63 chips out of 127, the maximum autocorrelation sidelobe increases from the ideal 12.3 db to 12.8 db with gold sequences. A 0.5 db increase in the autocorrelation sidelobe is acceptable for this design. OUT Figure 4-3. Adaptive Length Matched Filter Adders In Matched Filters When adding two 2 s complement numbers of B bits wide, the resulting sum must be B+1 bit wide. The extra output bit of the sum, the carry out of the most significant bit (msb), is to prevent overflow when adding two numbers. Similarly, when three numbers of B bits wide are added together, the sum output must be at least B+2 bits wide. In other words, N extra bits beyond B at the sum output can accommodate up to 2 N numbers of B bits wide that are being added. Therefore, as the number of taps grow in the matched filter, the bits in each adder must increase accordingly. Although truncation can be applied in the mid-sections of the filter, that can cause undesirable fluctuations in the correlation values. For example, truncating bits in the mids Page 40

53 section of the filter can cause autocorrelation sidelobes to grow greater than expected amplitudes. Since correlation sidelobes can cause greater false lock probability, it is best to keep the filter at full precision for the entire correlation. Truncation, however, can be applied at the output of the filter because sequence correlation has ended. Figure 4-4 shows how adder bits must increase for an eight tap matched filter with B input bits. B B+1 B+2 B+2 B+3 B+3 B+3 Figure 4-4. An Eight Tap Matched Filter Example The output bus width is not specified because it is the end of the correlation process and truncation is acceptable Multipliers In Matched Filters The spreading sequence has been chosen to be a binary state code that takes on values of 1 and -1. In a digital binary system, logic low is referred to as 1 and logic high is referred to as -1. Therefore, multiplying a one bit number can simplify general purpose multipliers to XOR gates. A two input XOR gate truth table is shown in Table 4-1. TABLE 4-1. XOR Truth Table input A input B output C Page 41

54 Clearly, when one of the XOR inputs is a logic high, 1, the output is an inverted version of the second input. And when one of the inputs is a logic low, 0, the output is the same value as the second input. Hence when the code chip is a -1 the data input will be negated. Unfortunately, this negation by XOR gate is only valid for 1 s complement numbers. For 2 s complement format, a one must be added to the inverted number to complete 2 s complement negation. Usually this 1 is added at the carry-in of the next adder stage. Figure 4-5 shows in detail how 2 s complement multipliers for 1 bit code is implemented at each tap of the matched filter. i(3:0) i(0) i(1) i(2) i(3) c c = one coefficient bit carry-in B B+1 Figure 4-5. A Matched Filter Tap In Detail 4.2 Squaring Circuits Contrary to general purpose multipliers, the multiplication of a number to itself greatly simplifies the multiplying hardware. When squaring a 2 s complement number, the output is always positive. Thus, the output bus width is 2 B-1 bits for a input of B bits where as a general multiplier would have an output bus of 2 B bits wide. To see how the internal hardware is simplified, Figure 4-6 demonstrates an example of a 2 s complement Page 42

55 four bit number called x. T 6 T 5 T 4 T 3 T 2 T 1 T 0 x 0 x 3 x 0 x 2 x 0 x 1 x 0 x 0 x 1 x 3 x 1 x 2 x 1 x 1 x 1 x 0 x 2 x 3 x 2 x 2 x 2 x 1 x 2 x 0 x 3 x 3 x 3 x 2 x 3 x 1 x 3 x 0 x 2 x 3 x 1 x 3 x 0 x 3 x 0 x 2 x 1 0 x 0 x 3 x 1 x 2 x 0 x 1 x 2 1 Figure 4-6. Squarer Array for 2 s Complement numbers where the operator denotes an and logic combination. This method of hardware reduction for squarer starts by assuming x as a negative number (i.e. x 3 is a 1) [23]. The top half of Figure 4-6 shows normal and operations for a multiplier. However, the msb of each row of results is not extended. The reason being that 2 s complement negation will be applied on the msb instead, as will be described shortly. At the bottom half of Figure 4-6, adding each item in every column simplifies the combinational logic. For example, the terms x 0 x 1 in column T 1 are shifted to column T 2 because their sum is the anded result left-shifted by one bit. Shifting of the sum of same terms is then performed for all the other columns as well. When the msb-anded, x 3, terms are left shifted the shifted terms are inverted due to the initial assumption that x is negative. An exception is when x 3 and x 3, where the two msbs try to invert each other and this double inversion yields the x 3 term by itself. Since Page 43

56 2 s complement format is used, the inverted terms must have a 1 added. Figure 4-6 shows that the row of msb inverted terms start at column T 4, therefore the 1 must be added in that column. This algorithm will work for negative x since all designs made that initial assumption. But the msb of x is still carried through out the squaring operations regardless of the sign of x. So if x is actually positive, inverting x 3, which is now 0, and adding a 1 in column T 4 will overflow the inverted terms producing a 1 in column T 7. Since T 7 column is neglected in the final result, the simplified logic in Figure 4-6 is logically equivalent to squaring with a general purpose multiplier. 4.3 Integrate and Dump Module This block is used for serial correlation and for acquisition dwells. Its implementation is very simple as shown in Figure 4-7. The integration part is just an adder with registers delaying the last accumulated value. In order to periodically sample only the final accumulated output, a counter clocks the output registers. Dump clk Counter Figure 4-7. An Integrate and Dump Circuit 4.4 PN Code Generator Module IC architecture of PN code generator is exactly the same as shown in Figure 1-3 Page 44

57 except that the modulo-2 adders are replaced by XOR gates. The actual implementation of the generator is slightly more complex because the PN acquisition loop is adaptable to different code lengths and code sequences. Figure 4-8 illustrates the modified PN generator which is programmable to different orders of codes and feedback taps. c 0 (5) c 0 (4) c 0 (3) c 0 (2) c 0 (1) c 0 (0) I 0 (6) I 0 (5) I 0 (4) I 0 (3) I 0 (2) I 0 (1) I 0 (0) c 1 (5) c 1 (4) c 1 (3) c 1 (2) c 1 (1) c 1 (0) I 1 (6) I 1 (5) I 1 (4) I 1 (3) I 1 (2) I 1 (1) I 1 (0) s Figure 4-8. Programmable PN Code Generator The c 0 and c 1 vectors are the programmable feedback codes to produce the PN sequences. I 0 and I 1 are parameters for the initial phase of the code generator. And finally, the s port is to select the code order. 4.5 Finite State Machines and Controls There are several finite state machines (F.S.M.) for the matched filter PN acquisition loop. The most important F.S.M. is to control the acquisition process. Due to the Page 45

58 double dwell architecture, the former F.S.M. require a first dwell search state, a second dwell verification state, and an acquisition state. Figure 4-9 shows the acquisition F.S.M. transition diagram. h 1 > V th First Dwell Second Dwell h 2 < V th h2 > Vth reset ACQ. Figure 4-9. State Machine for PN Acquisition Process A second F.S.M. is needed to control loading the PN code sequences into the matched filters. The PN code is produced by the PN generator which outputs into the shift registers that store the matched filter codes. This F.S.M. has only two states: code loading and not loading. Nonetheless, the complexity of the code loading F.S.M. is present because of the coefficient orientation in a transposed filter. As indicated in Matched Filter Design section, the first coefficient must be at the last register of the coefficient LSR pipeline. As the matched filter adapts to a shorter PN code length, the coefficient LSR pipeline Page 46

59 must continue the shifting action until the first PN chip has reached the (N-1) th register even after the input from the PN generator has stopped. These additional control complexities are implemented in the PN loading F.S.M. Since the loading action can be easily described in VHDL using conditional statements, the exact implementation will be left to the netlist compiler. 4.6 Pipelining I 4 Q 4 enable ( ) ( ) 2 enable V th 15 1 F.S.M. LOCK 8 PN GEN 8 Pipeline Insertion Figure Pipelining the PN Acquisition Loop The critical path for the matched filter PN acquisition loop is shown by a bold line in Figure This datapath cannot meet a timing constraint of 50 ns. Thus, it is pipelined by inserting registers at the vertical dotted line in Figure 4-10 to satisfy the 20 MHz clock frequency. When a time delay exists between decision blocks and the input of a feedback Page 47

60 loop, the controls must compensate for this lag. For example, when the matched filters detect a code alignment, the decision device receives this signal one clock cycle later due to the pipeline. Now the serial correlators must be enabled for a second dwell. Therefore, the serial correlators must have a PN code generator that is leading the code phase of the matched filters. Another solution is to insert additional delays before the input to the serial correlators. This design opts for the leading phase PN generator method, using additional controls, so that the PN acquisition loop is also adaptable to a serial correlator architecture. 4.7 Strongest Multipath Detection Wireless communications in the outdoor environment often encounter multipath delay spread. Multipath is an artifact of reflected electromagnetic energy from hills, trees, and man-made structures. As signals are reflected off of different obstructions, they may arrive at the receiver antenna with different delays causing multipath signals. Therefore, a desirable feature for PN acquisition is to find the strongest multipath that can yield the highest SNR. The architecture for strongest multipath detection is the same as threshold comparison scheme in Figure 2-9. The difference lies in the controls. To find the strongest multipath, the PN acquisition loop must be able to search transmitted signals within a window of time. Furthermore, searches within this time window must also take on discrete time steps for practical implementations. Hence, the steps of time in which the PN acquisition loop searches for multipath bounds the smallest time difference between arrival of the Page 48

61 multipaths that the receiver can distinguish. Similarly, the time window bounds the largest time difference between the multipaths that are capable of being acquired. new < old, next phase new > old Reset stored phase and energy to zero. reset complete Compare new energy to stored next phase Update stored energy and phase with new info. verification failed Dwell verification of acquisition Alignment complete Align local sequence to received signal using stored phase T s time window expired verification successful ACQ. Figure State Machine for Finding Strongest Multipath The process and controls to find the strongest multipath signal can be described by using a state machine diagram as shown in Figure There are two important insights that can be observed from the state machine controls in Figure 4-11 and the architecture drawing in Figure 2-9. One is that the lower bound caused by discrete time step is Page 49

62 restricted by implementation of the architecture. If the clock of the PN acquisition loop only samples 2 times per chip, then multipaths which arrive less than 1/2 fraction of the chip period are indistinguishable. Two, the bound on finding strongest multipath in a time window is induce by the number of phase searches allowed in the state machine. Clearly, the state machine in Figure 4-11 allocates T s seconds to be searched. Besides these two insights, there is also an important feature when using strongest multipath detection scheme. During the initial phase searches, the energy comparisons are relative to past samples. In other words, a constant threshold parameter need not be supplied although verification still requires a threshold. This algorithm is a maximum-likelihood detection [3]. Note that even if multipaths do not exist in the channel, the maximumlikelihood algorithm can still be used for PN acquisition to detect the autocorrelation peak. 4.8 Fixed-Point Optimization All digital devices must have finite precision. The PN Acquisition loop takes its input directly from an A/D converter. To determine the precision required on the A/D converter, both PN Acquisition loop and Bit Error Rate (BER) must be simulated so that neither limit each other. That is the precision demanded by the demodulator is sufficient for PN Acquisition and vesa versa. Since most DSSS systems employ a BPSK modulation, a noncoherent DPSK demodulator is used to determine required demodulator precision. The matched filter PN acquisition loop in Figure 4-10 is simulated to find its minimum number of input bits. A channel condition of -5 db Chip-to-Noise ratio in AWGN is adopted along with a pro- Page 50

63 cessing gain of 15 db using gold code DPSK PN Acq. w/mf Floating BER log(ber) log(e[tacq]) Number of Input Bits CNR = -5 db Process Gain = 15 db Figure 4-12 shows the results of these simulations. While three bits is sufficient for PN acquisition, the demodulator is about 0.5 db from the ideal floating point boundary. Furthermore, the performance of PN acquisition loop degrades dramatically at two bits input bus width. In order to provide a safer margin of error but still keeping complexity to a minimum, four bits at the input is chosen. Figure Fixpoint Simulations The architecture drawing in Figure 4-10 indicates the bus width at each quantized node. Section on matched filter adders indicates that a four bit input matched filter with 126 taps full precision would produce a 11 bit output. A truncation from 11 bits to 8 bits matched filter output was performed due to adaptations in filter length. For example, when 30 taps are used in the filter there are only 9 bits (where the five extra bits beyond the Page 51

64 input bus width are to ensure that the sum of thirty numbers doesn t overflow) at the output. Since correlation is completed at the output of the filters, truncation is acceptable as mentioned in Section Furthermore, eight bit datapath components are standard whereas nine bit buscells are fairly awkward and uncommon in standard technology libraries. Therefore, an eight bit bus is used as input to the squaring circuits. 4.9 PN Acquisition Loop Testing Features In order to apply continuous testing throughout the life span of the PN Acquisition ASIC, two self tests are built in the ASIC. The Semi-Built In Self Tests (SBST) require some simple controls which can be implemented on a Field Programmable Gate Array (FPGA) as shown in Figure ASIC PN Acq. Loop controls FPGA pass/fail indicators Figure ASIC Testing Setup for Built-In Self Tests The first SBST is designed to test the matched filters functionality. This is accomplished by sending a known sequence of vectors into the ASIC and accumulating the output vectors. After the input test vectors have been exhausted, the accumulated value is dumped and compared to the expected or simulated result. The block diagram for the first SBST is shown in Figure In addition, a select parameter exists to allow the choice of Page 52

65 testing either the I-channel or Q-channel filter. ASIC =? Pass/Fail RESULT1 FPGA Figure SBST Number 1 The second SBST is to test the entire acquisition loop by emulating an acquisition process. Like the first SBST, a known test vector is sent into the ASIC and a counter accumulates the number of cycles used before acquisition. The counter value is then compared to the expected or simulated result. Figure 4-15 shows the second SBST block diagram. ASIC PN Acq. Loop =? Pass/Fail FPGA RESULT2 Figure SBST Number 2 Page 53

66 Chapter 5 Synthesized IC 5.1 Area and Power The core of the chip consist of many modules but there is really only one major block on the ASIC. This block is the matched filter module 1 as can be seen in Figure 5-1. Area and power statistics will be given for the entire chip core. TABLE 5-1. Specifications for PN Acquisition Chip No. of Gates a 39,000 No. of Transistors 156,000 Die Size 4.6mm x 5.1mm Technology HP CMOS14B 0.5µm Package 68-pin PGA Power (3.3 V) 140 mw Fastest Clock Freq. 20 MHz Critical Path Delay 44.2 ns a. This is normalized to a logic nand gate 1. Although there are two instances of this block, they are identical. Page 54

67 Interface Controls and Combinational Logic Q-Channel Matched Filter I-Channel Matched Filter Figure 5-1. Layout Snapshot of PN Acquisition ASIC in 0.5µm CMOS 5.2 Testing Functional and Timing The initial timing checks were performed in Cascade s Epoch. Epoch includes a tool called Tactic which analyzes critical paths for delay violations and short paths for setup/hold violations. Furthermore, Tactic will report delays between each component including clock buffers. Therefore, clock skews are also characterized in the final timing check. For combined functional and timing verifications, Synopsys VSS Expert was used to verify the post-layout netlist. A VHDL timing delay package was created using Page 55

68 Epoch which is then back-annotated to the VHDL netlist of the chip. The testing of the chip was divided into two parts: 1) testing the matched filters and 2) testing the acquisition loop with matched filters, strongest multipath mode, and serial correlators (full and half chip skipping) at different thresholds. The first test of matched filters was carried out by generating test vectors, consisting of random noise at the input, using Angeles Design Systems DSP Canvas system simulator. These test vectors are then annotated into a VHDL testbench for the PN acquisition ASIC. VSS Expert can then verify if the layouts match the system simulations. Another form of this test is to use the first SBST and its result. The timing backannotated simulation for the first self test is shown in Figure 5-2. The signal bsto1[1:0] indicates a passed test with vector 01. Figure 5-2. Self Test Number 1 for Matched Filters For the second test, a known PN sequence with pre-set offset to the receiver PN generator is sent into the acquisition loop. The PN acquisition chip should then acquire after the predicted number of cycles. One way to implement this testing is to use the second SBST on the ASIC and this was the actual conduct of the test. Figure 5-3 shows simulation results for various testing conditions. The signal bsto2[1:0] indicates a passed test with vector 01. The pnl and pn signal are the receiver and transmitter PN sequence, respectively. Under the multipath acquisition test using matched filters, the pn2 is an arti- Page 56

69 ficially generated multipath that is weaker in strength then the main multipath pnl. Figure 5-3(c) shows acquisition to the pnl multipath after acquisition lock is indicated. (a) (b) Figure 5-3. Layout Timing Backannotated Simulations for PN Acquisition Test. (a) Serial Acquisition Mode using half chip skip (b) Serial Acquisition Mode using full chip skip (c) Matched Filters Acquisition under multipath conditions. (c) However, notice that right after lock has gone active, the receiver pn sequence seems to be out of alignment with the incoming signal as shown in Figure 5-3(c). After three clock cycles, the transient of the pn signal reaches the acquisition state. This tran- Page 57