Initial Synchronization

Transcription

1 Wireless Information Transmission System Lab. Initial Synchronization Institute of Communications Engineering National Sun Yat-sen University

2 Contents Introduction and Over-sampling Downlink Synchronization -- Cell Search Correlator Parallel Matched Filter Detail considerations in designing cell search. Serial and Parallel Matched Filter Frequency Offset Coherent vs. Non-coherent Detection Implement of Square Root Circuit Noise Effect and Multi-path Signals. Uplink Synchronization -- PRACH Preamble Detection

3 Wireless Information Transmission System Lab. Introduction and Over-sampling Institute of Communications Engineering National Sun Yat-sen University

4 Initial Synchronization Downlink initial synchronization Initial Cell Search (power on) Capture the slot & frame timing of the chosen BS and establish links. Target Cell Search (handoff) To re-synchronize to a new BS. In WCDMA, there is no global synchronization between BSs. Uplink initial synchronization PRACH preamble code detection. 4

5 Sampling Theorem 5

6 Sampling Theorem Sampling Theorem: A bandlimited signal having no spectral components above f m hertz can be determined uniquely by values sampled at uniform intervals of T s seconds, where TS or sampling rate f S f m f m In sample-and-hold operation, a switch and storage mechanism form a sequence of samples of the continuous input waveform. The output of the sampling process is called pulse amplitude modulation (PAM). 6

7 Sampling Theorem X S ( f ) = X ( f ) X δ ( f ) = X ( f nfs ) T 7 S n=

8 Spectra for Various Sampling Rates 8

9 Natural Sampling 9

10 Initial Synchronization To establish initial synchronization between BS and MS. At the receiving end, there is often a over-sampling procedure, which takes several samples per chip. Depending on the over-sampling rate, the accuracy of initial synchronization is within ±/( over-sampling rate). Determination of over-sampling rate is a trade off between performance and hardware cost. Under most of the conditions, over-sampling rate is chosen among, 4, and 8. 0

11 Over-sampling of a sinc Function (I) Oversampling Rate = Max(Sample)= sinc T

12 Over-sampling of a sinc Function (II) Oversampling Rate = 4 Max(Sample)= sinc T

13 Over-sampling of a Raised Cosine (I) Oversampling Rate = ; Beta = 0.; Max(Sample)= raised cosine T 3

14 Over-sampling of a Raised Cosine (II) Oversampling Rate = 4; Beta = 0.; Max(Sample)= raised cosine T 4

15 Over-sampling of a Raised Cosine (III) raised cosine raised cosine OS Rate = ; Beta = 0.50; Max= T OS Rate = ; Beta =.00; Max= T raised cosine raised cosine OS Rate = 4; Beta = 0.50; Max= T OS Rate = 4; Beta =.00; Max= T 5

16 Wireless Information Transmission System Lab. Downlink Initial Synchronization Cell Search Institute of Communications Engineering National Sun Yat-sen University

17 Downlink Synchronization Base stations always transmit synchronization codes in synchronization channel - T c Synchronization code MS is synchronized to BS with the aid of synch. code In 3GPP, a synchronization code of 56 chips is used. 7

18 Structure of Synchronisation Channel (SCH) Secondary SCH ac s i,0 Slot #0 Slot # Slot #4 Primary SCH ac p ac p ac p 56 chips 560 chips ac s i, One 0 ms SCH radio frame ac s i,4 8

19 Cell Search Procedures During the cell search, the UE searches for a cell and determines the downlink scrambling code and frame synchronisation of that cell. The cell search is typically carried out in three steps:. Slot synchronization. Frame synchronization/code-group identification 3. Scrambling-code identification 9

20 Synchronization Channel and Common Pilot Channel for Cell Search First step of cell search uses primary synchronization (P-SCH). Second step of cell search uses secondary synchronization (S- SCH). Third step of cell search uses common pilot channel (CPICH). One Frame (0 ms) One Slot (0.67 ms, 560 chips) P-SCH 56 chips (0.067 ms) S-SCH CPICH 0

21 Slot Synchronization During the first step of the cell search procedure the UE uses the SCH s primary synchronisation code to acquire slot synchronisation to a cell. In 3GPP W-CDMA, Primary SCH is the same for every BS At each slot beginning, P-SCH codes of 56 are transmitted and then turned off until the next slot. A matched filter could be used to match the code such that the strongest path from a certain BS could be captured. Due to path propagation loss, the strongest path usually comes from the nearest BS.

22 Primary Synchronization Codes Primary SYN code (PSC), C psc Constructed as a so called generalised hierarchical Golay sequence. Good aperiodic auto-correlation properties. Define a = <x, x, x 3,, x 6 > = <,,,,,, -, -,, -,, -,, -, -, > PSC, C psc = ( + j) <a, a, a, -a, -a, a, -a, -a, a, a, a, -a, a, -a, a, a>, The leftmost chip in the sequence corresponds to the chip transmitted first in time

23 Wireless Information Transmission System Lab. Correlator Institute of Communications Engineering National Sun Yat-sen University

24 Structure of Correlator Correlator Correlation is done at chip rate. Received Signal cos(πft) carrier 90 o sin(πft) H*(f) S Sample a n (k) N ( ) n = H*(f) N ( ) n= Samples are taken at over-sampling rate. Read code coefficient at chip rate. Threshold Detection 4

25 Delay Line and Correlator Bank Local PN Code Over-sampling Rate. Delay Line Tc/ Tc/ 3 Tc/.... (N-) Tc/ Received Signals C (t) C (t-tc/) C (t-tc/) C (t-3tc/).... C (t-(n-)tc/) S.... Output i=0 i= i= i=3.... i=n- 5

26 Operation of Correlator Bank Example: Over-sampling rate :. Received signals after over-sampling: r, r, r, r, r, r,..., r, r,... etc. 3 3 PN code or Synchronization code: C, C, C 3,, C 56. Searching window : 560 chips. Note that, we need 560 =50 correlators for a oversampling rate of and searching window of 560 chips. If we consider both I and Q, the number of correlators is doubled. Of course, if hardware re-use is applied, number of correlators needed can be reduced. 6 i i

27 Operation of Correlator Bank Received signals after over-sampling Code Delay Tc Tc 0 C 56 C 56 C C C C 56 i= 56 i= c r + i c r + i i 0 i 0 Tc 59 Tc 58 C 56 C 56 C C C C 56 i= 56 i= c r + ci r i i 7 i 559

28 Wireless Information Transmission System Lab. Parallel Matched Filter Institute of Communications Engineering National Sun Yat-sen University

29 Structure of Parallel Matched Filter Tapped Delay Line Received Signals Output Code Coefficient 9

30 Example: Operation of Parallel Matched Filter Over-sampling rate :. Received signals after over-sampling: r, r, r, r, r, r,..., r, r,... etc. 3 3 i PN code or Synchronization code: C, C, C 3,, C 56. Searching window : 560 chips. i Note that we need only one matched filter of tap length 56 to search virtually infinite large time window. 30

31 Operation of Parallel Matched Filter Time = 0 Over-sampled signals r 56 r 56 r 55 r 55 r 3 r 3 r r r r C 56 C 55 C 3 C C Output 56 i= c r + i i 0 3

32 Operation of Parallel Matched Filter Time = Tc/ Over-sampled signals r 57 r 56 r 56 r 55 r 4 r 3 r 3 r r r C 56 C 55 C 3 C C Output 56 i= c r + i i 0 3

33 Operation of Parallel Matched Filter Time = 58 Tc/ Over-sampled signals r 85 r 85 r 84 r 84 r 56 r 56 r 56 r 56 r 560 r 560 C 56 C 55 C 3 C C Output 56 i= c r + i i

34 Operation of Parallel Matched Filter Time = 59 Tc/ Over-sampled signals r 86 r 85 r 85 r 84 r 563 r 56 r 56 r 56 r 56 r 560 C 56 C 55 C 3 C C Output 56 i= c r + i i

35 Operation of Parallel Matched Filter Received signals after over-sampling Time of output. Tc Tc 0 C 56 C 56 C C C C 56 i= 56 i= c r + i ci r i + 0 i 0 Tc 59 Tc 58 C 56 C 56 C C C C 56 i= 56 i= ci r i ci r i

36 Adder Tree of Matched Filter <5,4,t> m0 m m m3 m4 m5 m6 m7 m8 m9 ma mb mc md me mf <6,5,t> <7,6,t> <8,7,t> <9,8,t> 36

37 Correlator Bank vs. Parallel Matched Filter The number of correlators needed in a correlator bank is equal to the number of chips, which corresponds to the length of the search window, times the over-sampling rate. The length of the matched filter tapped delay line equals to both the accumulation time and the number of code chips. The matched filter needs much more registers, multipliers, and adders. Matched filter is adopted under most of the situations for coarse synchronization. 37

38 Wireless Information Transmission System Lab. Detail Considerations in Designing Cell Search Institute of Communications Engineering National Sun Yat-sen University

39 Problems with the st Stage Cell Search There are a few problems with the st stage cell search using matched filter: Matched filter usually occupies a large area in the IC. Serial and Parallel Matched Filter Frequency error due to low cost crystal oscillator (frequency offset). Coherent vs. non-coherent detection. Complexity of square root circuit. Noise effect and multi-path signals. 39

40 Serial and Parallel Matched Filter Received Signal tapped delay line Output Parallel Load 3 N N-chip digital delay PN code coefficient G.. J. R. Povey and P. M. Grant, Simplified matched filter receiver designs for spread spectrum communications applications, Electronics & Communication Engineering Journal, Apr

41 Serial and Parallel Matched Filter Example: Over-sampling rate :. Matched filter tap length : 3 (N=3). Received signals after over-sampling: r, r, r, r, r3, r3,..., ri, ri,... etc. PN code or Synchronization code: C, C, C 3,, C 56. Note that N=3 implies that we would like to search for a time window of 3 chips. We need to store the sampled data of 64 samples. We need a 3-chip digital delay registers (64 data). We need a matched filter of 3 taps in length. 4

42 Serial and Parallel Matched Filter Time = 0 Tc/ Received sample: - r 3 r 3 r 3 r 3 r r Length of matched filter times over-sampling rate. 3 X 3 ci r i i= C 3 C 3 C 4

43 Serial and Parallel Matched Filter Received sample: - Time = Tc/ r 33 r 3 r 3 r 3 r r 3 X 3 3 ci r i + 0ci r i i= i= C 3 C 3 C C 33 43

44 Serial and Parallel Matched Filter Received sample: - Time = Tc/ r 33 r 3 r 3 r 3 r r 3 X 3 i= ci r i + 3 ci r i i= C 3 C 3 C C 33 44

45 Serial and Parallel Matched Filter Received sample: 3- Time = 6 Tc/ r 63 r 63 r 6 r 6 r 3 r 3 3 X 3 i= 3 ci r i + 3 i= c r + i i 9 0 C 3 C 3 C C 63 C 6 45

46 Serial and Parallel Matched Filter Received sample: 3- Time = 63 Tc/ r 64 r 63 r 63 r 6 r 33 r 3 3 X 3 i= 3 ci r i + 3ci r i + 3 i= 3 i= ci r i + 0 C 3 C 3 C C 64 C 63 C 33 46

47 Serial and Parallel Matched Filter Received sample: 33- Time = 64 Tc/ r 64 r 64 r 63 r 63 r 33 r 33 3 X 64 i= ci r i i= c r + i i 3 3 i= c r + i i 0 C 64 C 63 C ci ri + ci ri i= i= 33 47

48 Serial and Parallel Matched Filter Received sample: 64- Time = 7 Tc/ r 96 r 95 r 95 r 94 r 65 r 64 3 X 64 i= ci r i i= ci r i i= ci r i + 0 C 64 C 63 C 33 C 96 C 95 C ci ri+ 3 + ci ri+ 3 i= i= 33 48

49 Serial and Parallel Matched Filter Received sample: 65- Time = 8 Tc/ r 96 r 96 r 95 r 95 r 65 r 65 3 X 96 i= ci r i i= ci r i i= ci r i + 0 C 96 C 95 C ci ri + ci ri i= i= 65 49

50 Serial and Parallel Matched Filter Code Length Received sample: 56- Over-sampling Rate Time = 5 Tc/ r 88 r 87 r 87 r86 r 57 r 56 3 X 56 cr i i + 3 i= 56 ci r i + 3 i= 56 ci r i + 0 i= C 56 C 55 C Stop matching!! 50

51 Serial and Parallel Matched Filter Received signals after over-sampling C 56 C 56 0 C 56 C 56 C C C C 56 i= i 56 i= c r + c r + i i 3 i 3 C C C 56 C i= 56 i= i c r + i c r + Output read at time = 5 Tc/ i 0 i 0 5

52 Serial and Parallel Matched Filter The serial parallel matched filter is more flexible than the parallel matched filter. The accumulation time can be much longer than the tapped delayed line length. The length of the N-chip digital delay equals to the length of the matched filter tapped delay line. The PN code is shifted to the code tapped delay line. After N code chips are loaded, they are parallel loaded to the matched filter. The input signal is loaded into the upper tapped delay line continuously. The matched filter output results are accumulated in the N- chip digital delay. 5

53 Problems Due to Frequency Offset Crystal oscillators at mobile terminal have inaccuracies in the range of 3-3 ppm, which gives rise to a frequency error in the range of 6-6 KHz when operated at GHz. ppm = 0-6 = one part per million. An important goal for the MS is thus to reduce its frequency error to a reasonable range during initial search so that further communication functions can take place. Non-coherent detection is adopted instead of coherent detection. Wang, Y.-P. E., and Ottosson, T., Cell Search in W-CDMA," IEEE Journal on Selected Areas in Communications, pp , Volume 8, Issue 8, August

54 System Model for Frequency Error Due to Imperfect Crystal Oscillator s(t) r(t) h r (t) x k Despread y k j π f + θ c(t) n(t) e e t SNR y = σ N sin ( πf e NT N sin ( πf T e c c ) ) f e is equal to sum of frequency error and maximum Doppler shift. Yi-Pin Eric Wang and Tony Ottosson, Initial Frequency Acquisition In WCDMA VTC 99, pp

55 Non-coherent Detection for Frequency Error SNR Under Different Frequency Error (Chip Rate = 3.84 Mcps) fe = 5 KHz fe = 0 KHz fe = 0 KHz 40 0 Normalized SNR N 55

56 Non-coherent Detection for st Stage Cell Search Received Signals I/Q Splitter Matched Filter Non-coherent Combiner I + Q Peak Detection Matched Filter Non-coherent Combiner 56

57 Approximation of Square Root Circuit In practice, it is very difficult to implement the square root circuit. A few approximations can be adopted for square root circuitry:. I + Q. I + Q 3. max, min, where I cosθ ( I Q ) + ( I Q ) Q sinθ 57

58 Approximation of Square Root Circuit.5 Approximation of Non-Coherent Detection Amplitude 0.5 sin a=max( sin, cos ) cos b=min( sin, cos ) (sin) +(cos) sin + cos a+b/ a+(sqrt()-)*b max((a+b/8),(53a+37b)/64) Radian (pi) 58

59 Slot Synchronization To reduce the noise effect, slot-wise accumulator could be used for accumulating the output power in several slots. Slot timing is then acquired by finding the maximum peak of accumulator output within one observation interval. One observation interval = slot period Matched filter (c p ) Slot-wise accumulation Find maximum Timing modulo T slot T slot Two rays from BS i One ray from BS j Multipath channel!! 59

60 Frame Synchronization and Code Group Identification During the second step of the cell search procedure, the UE uses the SCH s secondary synchronisation code to find frame synchronisation and identify the code group of the cell found in the first step. This is done by correlating the received signal with all possible secondary synchronisation code sequences, and identifying the maximum correlation value. 60

61 Secondary Synchronization Codes 6 codes: {C ssc,,,c ssc,6 } Complex-valued with identical real and imaginary components. Constructed from position wise multiplication of a Hadamard sequence and a sequence z The Hadamard sequences are obtained as the rows in a matrix H 8 constructed recursively by: H H 0 k = () H = H k k H H k k k 6 Rows are numbered from the top (row): the all ones sequence.

62 Secondary Synchronization Codes z = <b, b, b, -b, b, b, -b, -b, b, -b, b, -b, -b, -b, -b, -b> b = <x, x, x 3, x 4, x 5, x 6, x 7, x 8, -x 9, -x 0, -x, -x, -x 3, -x 4, -x 5, -x 6 > The k-th SSC, C ssc,k, k =,, 3,, 6 C ssc,k = ( + j) <h m (0) z(0), h m () z(), h m () z(),, h m (55) z(55)> m = 6 (k ) C ssc,k (0) is the first transmitted chip in time. 6

63 Code Allocation of SSCs The 64 secondary SCH sequences are constructed such that their cyclic-shifts are unique. A non-zero cyclic shift less than 5 of any of the 64 sequences is not equivalent to some cyclic shift of any other of the 64 sequences. Also, a non-zero cyclic shift less than 5 of any of the sequences is not equivalent to itself with any other cyclic shift less than 5. 63

64 Allocation of SSCs for secondary SCH 64

65 Allocation of SSCs for secondary SCH 65

66 Frame Synchronization and Code Group Identification After the receiver knows the slot timing in the first step of cell search, the receiver can correlate the received signal with 6 matched correlators. Each matched to Secondary Synchronization codes. However, the receiver has no knowledge about the slot position in the frame and in what group. 66

67 Frame Synchronization and Code Group Identification Solution: Exhaustive search for the slot position and the sequence of S-SCH codes. Accumulate these 6 output samples extensively slot-byslot over all possible 960 combinations. 64 sequences and 5 slot positions. Choose one from 960 candidates to determine the code group and frame timing of the chosen BS. Since the cyclic shifts of the sequences are unique, the code group as well as the frame synchronisation is determined. 67

68 Scrambling-code Identification During the third and last step of the cell search procedure, the UE determines the exact primary scrambling code used by the found cell. The primary scrambling code is typically identified through symbol-by-symbol correlation over the CPICH with all codes within the code group identified in the second step. Recall that 8 scrambling codes are in the derived code group. After the primary scrambling code has been identified, the Primary CCPCH can be detected. And the systemand cell specific BCH information can be read. 68

69 Serial Searching Procedure Start Failure First Trial Success N-th Trial Stage Stage Stage 3 Stage Stage Stage 3 69

70 Pipeline Searching Procedure Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage 3 Stage 3 Stage 3 Stage 3 Stage 3 rejects candidates. Stage 3 accepts candidates. 70

71 Wireless Information Transmission System Lab. Uplink Initial Synchronization PRACH Preamble Detection Institute of Communications Engineering National Sun Yat-sen University

72 Uplink PRACH Preamble Detection The purpose of PRACH detection is to provide Node B the information of incoming requests, as well as the reference timing for delay estimation. The random-access transmission is based on a Slotted ALOHA approach. The UE can start the random-access transmission at the beginning of a number of well-defined time intervals, denoted access slots. There are 5 access slots per two frames and they are spaced 50 chips apart. 7

73 Uplink RACH Access Slot Numbers and Their Spacing radio frame: 0 ms radio frame: 0 ms 50 chips Access slot #0 # # #3 #4 #5 #6 #7 #8 #9 #0 # # #3 #4 Random Access Transmission Random Access Transmission Random Access Transmission Random Access Transmission 73

74 Structure of the Random-Access Transmission The random-access transmission consists of one or several preambles of length 4096 chips and a message of length 0 ms or 0 ms. Preamble Preamble Preamble Message part 4096 chips 0 ms (one radio frame) Preamble Preamble Preamble Message part 4096 chips 0 ms (two radio frames) 74

75 RACH Preamble Code Construction Each preamble is of length 4096 chips and consists of 56 repetitions of a signature of length 6 chips. There are a maximum of 6 available signatures. The random access preamble code C pre,n, is a complex valued sequence. It is built from a preamble scrambling code S r-pre,n and a preamble signature C sig,s as follows: C pre, n, s ( k) = S r pre, n ( k) C sig, s ( k) e π π j( + k ) 4, k = 0,,,,4095 where k=0 corresponds to the chip transmitted first in time. The modulation is performed by multiplying each chip of the RACH preamble sequence with a rotating vector that takes the values (,j,-,-j) 75

76 PRACH Preamble Scrambling Code The scrambling code for the PRACH preamble part is constructed from the long scrambling sequences. There are 89 PRACH preamble scrambling codes in total. The n:th preamble scrambling code, n = 0,,, 89, is defined as: S r-pre,n (i ) = c long,,n (i ), i = 0,,, 4095; The 89 PRACH preamble scrambling codes are divided into 5 groups with 6 codes in each group. There is a one-to-one correspondence between the group of PRACH preamble scrambling codes in a cell and the primary scrambling code used in the downlink of the cell. The k:th PRACH preamble scrambling code within the cell with downlink primary scrambling code m, k = 0,,,, 5 and m = 0,,,, 5, is S r-pre,n (i) as defined above with n = 6 m + k. 76

77 PRACH Preamble Signature The preamble signature corresponding to a signature s consists of 56 repetitions of a length 6 signature P s (n), n=0 5. This is defined as follows: C sig,s (i) = P s (i modulo 6), i = 0,,, The signature P s (n) is from the set of 6 Hadamard codes of length 6. 77

78 PRACH Preamble Signature Preamble Signature Value of n P 0 (n) P (n) P (n) P 3 (n) P 4 (n) P 5 (n) P 6 (n) P 7 (n) P 8 (n) P 9 (n) P 0 (n) P (n) P (n) P 3 (n) P 4 (n) P 5 (n)

79 PRACH Preamble Detection cos ω t SRRC y I MF c I ( ) Y I R(t) MF c I MF sin ω t SRRC y Q c Q MF Y Q ( ) π π j( + k) I Q 4 pre,, n s ( ) = c, c = r pre, n( ) sig, s( ) C k j S k C k e c Q 79

80 PRACH Preamble Detection Transmitter: C ( k) = c + jc = S ( k) C ( k) e I Q pre, n, s k k r pre, n sig, s where c = a= c or c = a= c I Q I Q k k k k At the receiving end, because of propagation delay, I Q I Q jφ ( ) I Q I Q ( ci cosφ ci sinφ) + j( ci sinφ+ ci cosφ) r = r + jr = c + jc e k k k k k = At the output of matched filter: N N ( r I I Q I ) ( I Q Q Q k ck + rk ck + rk ck + rk ck ) ( I ( )) Q Nck cosφ sinφ Nck ( cosφ sinφ) ( ) ( ) k= k= = Na + Na = ain ( ) = π π j( + k ) 4

81 PRACH Preamble Detection with Phase De-rotator cos ω t SRRC y I d I ( ) Y I R(t) π j( ) I Q 4 j Sr pre, n k Csig, s k e d, d = ( ) ( ) sin ω t y Q SRRC ( ) d Q Y Q 8

82 The De-rotation Block The de-rotation block performs the reverse operation by multiplying each complex data sample with a rotating vector that has the opposite phase (,-j,-,j). Data i+0 Data i+ Data i+ Data i+3 Data I = Data I Data I = Data Q Data Q = Data Q Data Q = - Data I Data I = - Data I Data I = - Data Q Data Q = - Data Q Data Q = Data I 8

83 PRACH Preamble Detection ( ) ( ) π j k π π j( + k ) 4 r pre, n sig, s I Q Transmitter: d, jd e = S ( k) C ( k) e I Q Note that d = d =± a. After de-rotator, because of propagation delay, r = r + jr = d + jd e I Q I Q jφ k k k k k I Q I Q = d cosφ d sinφ + j d sinφ+ d cosφ i i i i At the output of matched filter: N N ( r I I ) ( Q Q k dk + rk dk ) 83 ( ) ( I ( )) Q Ndk cosφ sinφ Ndk ( sinφ cosφ) ( ) ( ) k= k= = Na + Na = a N ( ) = + +

84 Non-coherent Detection of PRACH Preamble Data Buffer = 04 x Over-Sampling De-rotation RACH Segment Detector 3 RACH Segment Detector RACH Segment Detector Non-Coherent Summation RACH Segment Detector 0 Matched Filter Length = 04 84

85 Fixed Point < 8,6,t > < 0,8,t > <,,t > <0,,t> < 6,5,u > a0 a a a3 a4 a5 a5 a6 a7 a8a9 a0 s0 s... s5 Hadamard Transform ( 6 X 6 ) Delay.. DSP. Delay 85