Implementation of OFDM Modem using VHDL and Comparison on Different FPGA Platforms

Transcription

1 Implementation OFDM Modem using VHDL and Comparison on Different FPGA Platforms Shyam Sunder Sharma, Deepak Bhardwaj, V K Pandey Department Electronics and Communication Engineering Noida Institute Engineering and Technology Greater Noida, India Abstract: OFDM is a multi-carrier system where data bits are encoded to multiple sub-carriers, while being sent simultaneously. This results in the optimal usage bandwidth. A set orthogonal sub-carriers together forms an OFDM symbol. To avoid ISI due to multi-path, successive OFDM symbols are separated by guard band. This makes the OFDM system resistant to multi-path effects. Field Programmable Gate Arrays (FPGAs) is an emerging technology to implement these standards, as they are having higher capability producing speed and area efficient systems. In this work we implement and evaluate a complete OFDM modem using VHDL and using higher version FPGA families such as Virtex series, the operating frequency and resource utilization can be further improved. The circuit parameters and simulation results are obtained using ModelSim XE stware. Keywords-OFDM,ISI,FEC,FPGA,VHDL I. INTRODUCTION OFDM is a multi-carrier system where data bits are encoded to multiple sub-carriers. Unlike single carrier systems, all the frequencies are sent simultaneously in time. OFDM fers several advantages over single carrier system like better multi-path effect immunity, simpler channel equalization and relaxed timing acquisition constraints. But it is more susceptible to local frequency fset and radio front-end non-linearities. The frequencies used in OFDM system are orthogonal. Neighboring frequencies with overlapping spectrum can therefore be used. The global demand for multimedia data services has grown at a remarkable pace which has led to the expansion system capacity in terms the number subscribers supported, higher data rate and ubiquitous coverage with high mobility. Broadband wireless access (BWA) systems have evolved as the solution for the persistent demand these multimedia services [1]. It provides enhancement in multimedia data services and quality service (QoS). It support simultaneous voice, data and multimedia services to a large group subscribers without the need for digital subscriber line (DSL) or cable modem. High processing speed, design flexibility and fast design Turn Around Time (TAT) is the important requirements BWA to meet the challenges poised to it [2]. These requirements make the designers to choose reconfigurable hardware platform like Field Programmable Gate Array (FPGA). A product implemented on FPGA can easily be upgraded by making necessary changes in the Hardware Description Language (HDL) code and thus becomes obsolescence free. In addition the TAT FPGA based circuits is much shorter compared to Application Specific Integrated Circuit (ASIC). WiMAX and WLAN are based on IEEE and IEEE standards for BWA system [3]. WLAN plays as important role as a complement to the existing or planned cellular networks. The market penetration WLAN has been extensive due to its easy and low cost deployment, wide interoperability and inherent flexibility. They provide connectivity for slow mobility with high throughput for both indoor and outdoor environments. WiMAX is a nonprit corporation formed by equipment and component suppliers to promote the adoption IEEE compliant equipment by operators BWA systems [4]. It also ensures the compatibility and interoperability broadband wireless access equipments. Both these standards use OFDM PHY layer that greatly increase their performance. Basically, OFDM technique consists dividing the flow entrance data over orthogonal channels. In this way, and based on the orthogonality principle, the interference between each transmission channel is minimal. 1

2 Another advantage that comes from this approach is related to the assumptions about the noise in each channel. Over a large and unique passband channel it is difficult (impossible in fact, in many situations) to assume that the model noise is AWGN (Additive Noise Gaussian Noise). That is important because if the model is know, and it is correct, one can select the best way frequency equalization. But, in large passband channels (tenths Mhz) the noise model is unknown and unpredictable. The solution dividing a unique channel in subchannels simplifies the assumptions the noise over each subchannel and, course, one can suppose it approximately AWGN. In each one these subchannels, a digital modulation is made, each one with a subcarrier that presents different frequency, in a such form that a channel does not intervene with another one, thus keeping the orthogonallity. The way implementation and the orthogonallity property a system this type can vary sufficiently: since band pass filters each frequency until sophisticated techniques as the use the FFT with guard interval, which is the used one for the OFDM. In literature, this technique has been called for some designations as orthogonally multiplexed QAM (O- QAM), parallel quadrature AM, and so one. However, OFDM for wireless and DMT for systems wired (like DSL) are the most common designations that one can find in literature. As all the above techniques basically use the same principle, it is common to refer to them by means a generic name: MCM (to Multi-Carrier Modulation). In that way, MCM is the technique in the general direction, and OFDM is related to the implementation technique MCM using the FFT. Field-Programmable Gate Array (FPGA) is an example VLSI circuit which consists a sea NAND gates whereby the function are customer provided in a wire list. This hardware is programmable and the designer has full control over the actual design implementation without the need (and delay) for any physical IC fabrication facility. An FPGA combines the speed, power, and density attributes an ASIC with the programmability a general purpose processor will give advantages to the OFDM system. An FPGA could be reprogrammed for new functions by a base station to meet future needs particularly when new design is going to fabricate into chip. This will be the best choice for OFDM implementation since it gives flexibility to the program design besides the low cost hardware component compared to others. Figure 1 represents the OFDM block diagram in VLSI architecture perspective. The rest the paper is organized as follows: section II presents the detail Orthogonal Frequency Division Multiplexing. Section III describes Basics FPGA Resources and Devices; Concluding remarks are given in Section III. II. ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING Orthogonal Frequency Division Multiplexing (OFDM) is an alternative wireless modulation technology to CDMA. OFDM has the potential to surpass the capacity CDMA systems and provide the wireless access method for 4G systems [8]. OFDM is a modulation scheme that allows digital data to be efficiently and reliably transmitted over a radio channel, even in multipath environments. OFDM transmits data by using a large number narrow bandwidth 2

3 carriers. These carriers are regularly spaced in frequency, forming a block spectrum. The frequency spacing and time synchronization the carriers is chosen in such a way that the carriers are orthogonal, meaning that they do not cause interference to each other. This is despite the carriers overlapping each other in the frequency domain. The name OFDM is derived from the fact that the digital data is sent using many carriers, each a different frequency (Frequency Division Multiplexing) and these carriers are orthogonal to each other, hence Orthogonal Frequency Division Multiplexing [9]. The origins OFDM development started in the late 1950 s with the introduction Frequency Division Multiplexing (FDM) for data communications. Figure 2: OFDM orthogonal subcarriers representation In 1966, Chang patented the structure OFDM and published the concept using orthogonal overlapping multitone signals for data communications. In 1971, Weinstein introduced the idea using a Discrete Fourier Transform (DFT) for implementation the generation and reception OFDM signals, eliminating the requirement for banks analog sub carrier oscillators [10]. This presented an opportunity for an easy implementation OFDM, especially with the use Fast Fourier Transforms (FFT), which are an efficient implementation the DFT [11-12]. This suggested that the easiest implementation OFDM is with the use Digital Signal Processing (DSP), which can implement FFT algorithms. It is only recently that the advances in integrated circuit technology have made the implementation OFDM cost effective. The reliance on DSP prevented the wide spread use OFDM during the early development OFDM [13]. Figure 3: OFDM Time and Frequency domain (different view) 3

4 Divisor Limitador Multiplicador Gerador de Ângulo Simetria Hermetiana Somador Saída de dados Serial/ Paralelo Codificador Entrada Entrada do bloco de dados m complexos n bits reais Porta Gerador de Ângulo Multiplicador Divisor Limitador Sincronizador Serial Paralelo/ Serial Decodificador Saída Saída do bloco de dados m n bits complexos Somador Entrada de dados reais Figure 4: OFDM Block diagram Transmitter: The block diagram a typical OFDM transceiver is shown in Figure 4. The transmitter section converts digital data to be transmitted, into a mapping subcarrier amplitude and phase. It then transforms this spectral representation the data into the time domain using an Inverse Discrete Fourier Transform (IDFT). The Inverse Fast Fourier Transform (IFFT) performs the same operations as an IDFT, except that it is much more computationally efficient, and so is used in all practical systems. In order to transmit the OFDM signal, the calculated time domain signal is then mixed up to the required frequency. As a result the serial to parallel conversion stage involves filling the data payload for each subcarrier. At the receiver the reverse process takes place, with the data from the subcarriers being converted back to the original serial data stream [9]. When an OFDM transmission occurs in a multipath radio environment, frequency selective fading can result in groups subcarriers being heavily attenuated, which in turn can result in bit errors. These nulls in the frequency response the channel can cause the information sent in neighboring carriers to be destroyed, resulting in a clustering the bit errors in each symbol. Most Forward Error Correction (FEC) schemes tend to work more effectively if the errors are spread evenly, rather than in large clusters, and so to improve the performance most systems employ data scrambling as part the serial to parallel conversion stage. This is implemented by randomizing the subcarrier allocation each sequential data bit. At the receiver the reverse scrambling is used to decode the signal. This restores the original sequencing the data bits, but spreads clusters bit errors so that they are approximately uniformly distributed in time. This randomization the location the bit errors improves the performance the FEC and the system as a whole. Receiver The receiver basically does the reverse operation to the transmitter. The guard period is removed. The FFT each symbol is then taken to find the original transmitted spectrum. The phase angle each transmission carrier is then evaluated and converted back to the data word by demodulating the received phase [10]. The data words are then combined back to the same word size as the original data. III. FPGA RESOURCES AND DEVICES Field Programmable Gate Arrays (FPGAs) is an emerging technology to implement wireless standards like WLAN and WiMAX [13]. Pressional media equipment designers have traditionally relied on digital signal processing 4

5 (DSP) devices to provide processing power for audio and video subsystems. For better audio and video streaming performance at lower costs FPGA are used rather than dozens DSP device. FPGAs essentially creates a universal hardware platform useful for a number media applications requiring realtime audio and video processing power from low-cost recording and editing platforms to large-format consoles with integrated HD video. The FPGAs fer high flexibility which means that many functions can be placed on the most efficient location in the logic flow the device rather than in peripheral hardware [14]. A FPGA is a semiconductor device that is made up reprogrammable logic components. These logic components are made up combination look-up tables (LUT) and flip-flops (FF) which can be programmed to perform simple logic function operations as well as more complex combinatorial functions. In recent years, vendors started to include specialty resources in the FPGA fabric such as multipliers, specialty logic units and block RAM making it difficult to specify the size an FPGA with a single number. These specialty resources improve performance for specific operations only and may not be utilized in many other applications. Because these specialty resources different families FPGAs with similar gate counts can have significantly different capabilities. Field Programmable means that the FPGA's function is defined by a user's program rather than by the manufacturer the device so flexibility is also obtained [15]. Xilinx has fered two main FPGA families: the high-performance Virtex series and the high-volume Spartan series, with a cheaper easy path option for ramping to volume production. The company also provides two CPLD lines, the Cool Runner and the 9500 series. The Virtex-II Pro, Virtex-4, Virtex-5, and Virtex-6 FPGA family s targets high performance applications that require higher clock rates, extensive math operations or significant use single cycle timed loops. The Spartan-3 family Field-Programmable Gate Arrays is specifically designed to meet the needs high volume, cost-sensitive consumer electronic applications [16]. The eight-member family fers densities ranging from 50,000 to five million system gates. The Spartan-3 family architecture consists five fundamental programmable functional elements: 1) Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety logical functions as well as to store data. 2) Input/output Blocks (IOBs) control the flow data between the I/O pins and the internal logic the device. Each IOB supports bidirectional data flow plus 3-state operation. 3) Block RAM provides data storage in the form 18-Kbit dual-port blocks. 4) Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. 5) Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. These elements are organized as shown in figure 5. A ring IOBs surrounds a regular array CLBs. Figure 5: Spartan-3 Family Architecture The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. Each CLB comprises four interconnected slices as shown in Figure 6. 5

6 Figure 6: Arrangement Slices within the CLB Xilinx Spartan-3 FPGA (device XC3S400) [11] have 896 Configurable Logic Blocks (CLBs). Each CLB contains four slices and each slice contains two Logic Cells (LCs). Each LC contains a 4-input Look up Table (LUT). Two slices a CLB are termed as SLICEM and the other two as SLICEL as shown in Figure 6 [17]. The two LCs a SLICEM slice can be utilized as two 16 X 1 bit DRAM. The LCs slice, SLICEL can be used as ROM/logic generator. Each 16 X 1 RAM can be cascaded for deeper and wider memory applications. Spartan-3 device XC3S400 FPGA fers 56Kbits DRAM [18]. This device contains total 288K bits dedicated BRAM arranged in 16 blocks 18K bit each. Out 18K bits, 16K bits are used for data and rest 2K bits are used for parity purpose. Each block can be organized in various manner like 16K X 1bit, 8K X 2bit, 4K X 4bit etc. With the introduction 28 nm FPGAs recently, Xilinx replaced the high-volume Spartan family with a highly efficient Kintex family and the low cost Artix family. The total power consumption is minimized by adopting a high-k metal gate (HKMG) process which minimizes static power consumption. At the 28 nm node, static power is a significant portion the total power dissipation a device and in some cases is the dominant factor [19]. With the use a HKMG process, Xilinx has reduced the power consumption while increasing logic capacity. The Kintex-7 family is the first Xilinx mid-range FPGA family that the company claims delivers Virtex-6 family performance at less than half the price while consuming 50 percent less power. The use these efficient reconfigurable platforms for the implementation wireless standards can further improve the performance these standards [20]. IV. SIMULATION RESULTS The schematic diagram and simulation are shown in figure 7 and figure 8. 6

7 Figure 7: RTL Schematic OFDM Figure 8: Simulation results OFDM Transmitter The following tables gives the results obtained using different FPGA platforms. Table 1: Result for Spartan 3 FPGA Resources Slices FF 4 input LUTs bonded IOBs BRAMS GCLKs Spartan

8 Table 2: Result for Vertex 4 FPGA Resourc es Slices NO : FF 4 input LUTs bonde d IOBs B- RA MS GCLKs Vertex FPGA Resourc es slice regist er Table 3: Result for Vertex 5 slice LUTs fully used LUT FFs bonded IOBs BRA MS Of BUF G Vertex Table 4: Comparison FPGA Families FPGA Familie s Spartan 3 Virtex- 4 Virtex- 5 Frequency MHz M Hz M Hz Change in frequenc y Power Consumpt ion Change in Power consumpti on W MHz M Hz W 0.69 W W 0.66 W V. CONCLUSION With the so much development techniques digital transmission data as current FPGAs possibility to do systems digital transmission integrated in a single chip. To do use those modern technologies the complete structure it was developed for the transmitter and for the receiver OFDM that use FFT to do the modulation. Several forms were analyzed implementing that modem OFDM in a FPGA, and chosen the most efficient and versatile. In this paper we have implemented the OFDM modem using VHDL and simulate the result using different FPGA families. 8

9 VI. REFERENCES [1]. A. Ghosh, D. R. Wolter, J. G. Andrews and R. Chen, Broadband Wireless Access with WiMAX/802.16: current performance benchmarks and future potential, IEEE Communication Magazine, vol. 43, pp , Feb [2]. J. Garcia, FPGA-Based Hardware Implementations OFDM Modules for IEEE 802 standards: A common design, Thesis Report, Tonantzintla, Mexico, Sep [3]. IEEE e 2005: IEEE Standard for local and metropolitan area networks, Part 16: Air Interface for Fixed Broadband Wireless Access Systems Amendment 2: Medium Access Control Layers for Combined Fixed and Mobile Operations in Licensed Bands. [4]. ETSI EN V1.5.1: Digital Video Broadcasting (DVB); Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television, Nov [5]. IEEE : Standard for local and metropolitan area networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Sepcifications, Revision IEEE Std [6]. W. Konhauser, Broadband wireless access solutions progressive challenges and potential value next generation mobile networks, Wireless Personal Communications, vol 37, May 2006, pp [7]. S. B. Wicker, Error Control System for Digital Communication and Storage, Englewood Cliffs, NJ: Prentice-Hall, Inc. [8]. J. Hieskala and J. Terry. OFDM Wireless LANs: A Theoretical and Practical Guide. SAMS Publishing, U.S, [9]. U. S. Jha and R. Prasad, OFDM towards fixed and Mobile Broadband Wireless Access. Artech House Publisher.2007 [10]. A. Sghaier, S. Ariebi, and B. Dony, A pipelined implementation OFDM transmission on reconfigurable platforms, CCECE08 Conference, Dec, 2007 [11]. K. Chang, G. Sobelman, E. Saberinia and A. Tewfik, Transmitter Archeiticture for Pulsed OFDM, in the proc. the 2004 IEEE Asia- Pacific conf. on circuits and systems, Vol. 2, Issue 6-9, Tainan, ROC, Dec [12]. M. Engels. Wireless OFDM Systems: How to Make Them Work? Springer, 2001 [13]. A. Sghaier, S. Ariebi, and B. Dony, A pipelined implementation OFDM transmission on reconfigurable platforms, CCECE08 Conference, Dec,, [14]. Xilinx Inc., Interleaver/De-Interleaver, Product Specification, v5.1, DS250, March [15]. Altera Inc., Symbol Interleaver/De-Interleaver Core, Mega Core Function User's Guide, ver , June [16]. Lattice Semiconductor Inc., Interleaver/De-Interleaver IP Core, isplever Core User's Guide, ipug_61_02.5, August [17]. Xilinx, Spartan-3 FPGA Family: Complete Data Sheet, 2007, available at [18]. Altera, Cyclone III Device Handbook, vol. 1, 2007 available at [19]. D. Perry, VHDL: Programming by Example, 3rd Edition,Tata McGraw Hill, New Delhi, [20]. S. Brown & J. Rose, FPGA and CPLD Architectures: A Tutorial, IEEE Design & Test Computers, Summer 1996, pp