ELECTRONIC GIANT. EG4002 Datasheet. PIR Controller. Copyright 2012 by EGmicro Corporation REV 1.0

Transcription

1 ELECTRONIC GINT EG400 Datasheet PIR Controller REV 1.0

2 Contents 1. Features.... General Description.... pplications Device Information Pin map Pin Functions Block Diagram pplication Schematics EG400 Typical pplication Schematic EG400 pplication Schematic to Drive Relay EG400 pplication Schematic in uto Trigger and CDS detector Electrical Characteristics bsolute maximum ratings Recommended operating conditions Functional Description Oscillator Turn on delay timer and Stable timer Single Trigger and uto Trigger on pin Enable/Disable Trigger Function on Vc pin OP amp Gain Setting Package Information DIP8 Dimension SOP8 Dimension... 1 / 1

3 1. Features EG400 Datasheet V1.0 8-Pin SOP8/DIP8 Packaging Minimal Peripheral Components Required Low Supply and Built-in -stage Operational mplifier Built-in Fixed-gain 0x in nd Stage OP amp Built-in Window Comparator for Two Independent Voltage Monitors Built-in Internal Reference Voltages for OP amps and Comparators Provide djustable Turn on Delay Timer and Stable Timer Wider supply voltage:+v~+6vdc. General Description The EG400 IC is a, using analog mixing digital designed by CMOS process, The EG400 contains two operational amplifiers, window comparator, voltage reference, turn on delay timer and stable timer, and digital state controller, dedicated to larm system, uto door system, and LED light controller etc. The EG400 is available in an 8-Pin SOP/DIP the necessary features to implement PIR control schemes with a minimal external parts count, which can reduce the material cost and save the PCB board space.. pplications PIR larm System utomatic Dryer PIR Sensor Door Bell PIR Light Controller LED Microwave Radar Light Controller uto Door System / 1

4 4. Device Information 4.1. Pin map 1 1 VDD 8 1IN1- EG400 CT Figure 4.1 EG400 pin map 4.. Pin Functions Designator Name I/O Descriptions 1 1 O First stage OP amp output. 1IN- I First stage OP amp negative input. I Enable/Disable trigger function for photo resistor input: Disable the sensor function when voltage of pin is lower than 0.VDD, and pin is always to low level Enable the sensor function when voltage of pin is higher than 0.VDD. Trigger mode selection for single trigger or auto trigger input: 4 I It s in auto trigger mode when voltage of pin is higher than 0.7VDD. It s in single trigger mode when voltage of pin is lower than 0.VDD. 5 I Device ground reference. Output, active high 6 O Sink current:10 m and 5 m Source current:10 m and 5 m 7 CT I Oscillator timing capacitor input 8 VDD I Supply voltage: +V~+6Vdc. 4 / 1

5 5. Block Diagram VDD 8 VDD OP1 OP 1IN- OP1 OP 0X COP1 0.7VDD 0.VDD COMP1 COP COMP OR VS State Controller OSC 7 CT COP COMP ND 6 0.VDD 4 5 Figure 5.1EG400 block diagram 6. pplication Schematics 6.1 EG400 Typical pplication Schematic C10 0.1uF C9 10uF U HT75 IN C8 C7 0.1uF 10uF +Vin LED1 IR PIR1 D 1 S R1 47K C1 10nF C 10uF R 10K Vdd Vdd C R 10nF M VDD 1IN- EG400 7 CT R4 00K C4 1nF R6 10K R5 1K Q1 S8050 Figure 6.1a EG400 typical application schematic U1 5 / 1

6 6. EG400 pplication Schematic to Drive Relay C7 0.1uF HT75 IN C8 10uF C5 0.1uF C6 47uF Vin K1 POWER+ IR D 1 S R1 C1 47K 10nF C 10uF R 10K Vdd C 10nF R.0M 1 OP1 EG400 VDD CT R4 100K C4 1nF R5 10K RELY Q1 S8050 OPIN1- POWER- Vdd 4 5 Figure 6.1b EG400 application schematic to drive relay 6. EG400 pplication Schematic in uto Trigger and CDS detector C10 0.1uF C9 10uF U HT75 IN C8 C7 0.1uF 10uF +Vin LED1 IR PIR1 D 1 S R1 47K C1 10nF C 10uF R 10K R7 RG 1M C R 10nF M VDD 1IN- U1 EG400 7 CT R4 00K C4 1nF R6 10K R5 1K Q1 S8050 R8 D1 1N K Figure 6.1c EG400 application schematic in auto trigger and CDS detector 6 / 1

7 7. Electrical Characteristics 7.1 bsolute maximum ratings T=5 unless otherwise specified Symbol Ratings Conditions Min Max Unit VDD Supply voltage Respect to the V Output Respect to the V CT Timing RC input Respect to the V Trigger mode selection Respect to the V Enable/Disable Trigger Respect to the V 1IN- 1 First stage OP amp negative input First stage OP amp output Respect to the V Respect to the V T mbient temperature Tstr Storage temperature TL Lead temperature Soldering, T=10S - 00 Note:Exceeding extreme conditions may permanently damage the chip. EG400 s reliability may be affected running at the extreme conditions for a long time. 7 / 1

8 7. Recommended operating conditions T=5 unless otherwise specified Symbol Ratings Conditions Min Typ Max Unit VDD Operating Range V Icc Operating Supply Current Vdd=5V u Vdd=V u Vos Input Offset Voltage Vdd=5V - 5 mv Ios Input Offset Current Vdd=5V n vo Voltage Gain Open loop db VOPH VOPL H L VOH VOL VH VL Output Voltage High for OP mp Output Voltage Low for OP mp Enable Threshold for Disable Threshold for Output Voltage High for Output Voltage Low for uto Trigger Mode for Single Trigger Mode for Vdd=5V, ILOD=5u V Vdd=5V, ILOD=-5u V Vdd=5V V Vdd=V V Vdd=5V V Vdd=V V Vdd=5V, ILOD=10m V Vdd=V, ILOD=5m V Vdd=5V, ILOD=-10m V Vdd=V, ILOD=-5m V Vdd=5V V Vdd=V - V Vdd=5V V Vdd=V V 8 / 1

9 8. Functional Description 8.1 Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT shown in Figure8.1a. The capacitor CT is charged from the VDD through resistor RT to approximately COMP 0.6Vdd 0.4Vdd On/Off 0K 8 Vdd 7 CT 5 RT CT 0.6Vdd and discharged to 0.4Vdd by an internal 0KΩ pull-down resistor. The approximately oscillator frequency is determined by: Tosc=0.4R TC T RT RT 0K (Here resistor unit is KΩ, capacitor is nf, Tosc is us), and f=1/tosc. For example, R T=100K, C T=1nF, Tosc=0.4*100*1*1.5=50uS, f=1/t=0khz. When choosing the pull-up resistor RT, the resistance must be greater than 100K or more. Figure 8.1a oscillator frequency setting 8. Turn on delay timer and Stable timer The turn on delay timer of EG400 is defined to Tx,stable timer is defined to Ti,the ratio-coefficient of Tx and Ti is defined to K,K= Tx. For adapt to more applications, the EG400 has different K values, and Ti the suffix in the EG400 product model is distinguished, as shown in table 8.. Table 8. Model Tx Ti K EG xTosc 0000xTosc 5 EG400B xTosc xtosc 10 EG400C xtosc 7000 xtosc 14 EG400D xtosc 5000 xtosc 0 EG400E xtosc 4000 xtosc 5 EG400F x Tosc 000 xtosc EG400G x Tosc 000 xtosc 50 The turn on delay timer is used for setting up the timing of how long pin is active, the timing time of Tx is equals to Tosc clock cycles, Tx time as shown in Figure8.a. The stable timer is used for trigger blocking after Tx time out, pin is output low level during trigger blocking as shown in Figure8.a, the timing time of Ti is shown in table 8.. The total timing time is T=Tx+Ti, for example using EG400,choosing Tosc=50uS, then Tx=100000*50uS=5S,Ti=0000*50uS=1S as table8., total timing time is T=6S When setting Tx is less than 15S, suggested the use of a K=5 of EG400 product, which is to obtain better stable time for filter the load switching. 9 / 1

10 Figure 8.a turn on delay timer Tx and stable timer Ti 8. Single Trigger and uto Trigger on pin When pin input is lower than 0.VDD, EG400 is working in single trigger mode. s Figure 8.a, if Vc input is valid, the first rising edge of Vs will make the to high level output, chip enters Tx delay timing and Ti blocking timing stage, in this Tx stage, the Vs signal will be invalid until Tx and Ti time out. When pin input is higher than 0.7VDD, EG400 is working in auto trigger mode. s Figure 8.b, if Vc input is valid, the first rising edge of Vs will make the to high level output, chip enters Tx delay timing, in this Tx stage, the Tx delay time will be recount when Vs signal is trigged again, until Tx time out, chip enters Ti blocking time stage. 0.7VDD 0.5VDD 0.VDD 0.7VDD 0.5VDD 0.VDD Vs Vs Vc Vc Tx Ti Tx Ti Tx Ti Tx Ti Figure 8.a single trigger timing diagram Figure 8.b auto trigger timing diagram 8.4 Enable/Disable Trigger Function on Vc pin When Vc pin input is lower than 0.VDD, EG400 disable the PIR sensor function, and pin is always to low level. When Vc pin input is higher than 0.VDD, EG400 enable the PIR sensor function, pin will be controlled by Vs trigger signal as shown in Figure8.a and Figure8.b. photo resistor can be applied to Vc pin for light and dark activated detector circuits. 10 / 1

11 8.5 OP amp Gain Setting The gain of first stage OP amp is determined by R and R, the second stage OP amp is fixed gain of 0 times, as shown in figure 8.5a, the total gain is =1 x. In figure8.5a configuration, the 1=R/R=(*10 6 )/(10*10 )=00,=0, =1 x =00 x0=9000.by adjusting the gain, the PIR distance of detection can be changed. Here C is DC-blocking capacitor. C R 10nF M VDD OP1 OP PIR C 10uF R 10K 1IN- OP1 OP 0X Figure 8.5a EG400 OP amp gain setting 11 / 1

12 9. Package Information 9.1 DIP8 Dimension 9. SOP8 Dimension 1 / 1