AS1705 High Speed Bidirectional I 2 C Digital Isolator with Five Unidirectional Data Channels

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1 High Speed Bidirectional I 2 C Digital Isolator with Five Unidirectional Data Channels Bidirectional Communications 2.7V/5.5V level translation No user startup initialization required Dual high-speed bi-directional I 2 C channels Meets I 2 C Bus requirements Standard, fast mode and high-speed mode 30mA current sink capability Power Down to Hi-Z does not load I 2 C Bus Supports clock stretching Supports bus capacitance up to 100pF Low Power Wide Operating Range Independent 2.7V to 5.5 V supply on each side At 5V supply quiescent current is: 3mA per channel 0 to 2Mbps 15mA per channel for I 2 3.4MHz -40 to +125 C Operation Level Translation Independent 2.7V to 5.5 V supply on each side Mixed voltage system level translation for I 2 C 20 Lead SOIC wide body package These devices may be powered by supplies in the 2.7V to 5.5V range on either side in any combination. The input pins are all 5.5V tolerant irrespective of the voltage supply level being used. The I 2 C channels tri-state the outputs on loss of power and will not load the I 2 C bus. ORDERING INFORMATION Part Number Pin/Package Basic Isolation Pkg(1min.) Package Dimensions (mm) AS SOIC 2.5kV RMS 12.8 x 7.5 x 2.5 TYPICAL APPLICATIONS Digital Bus Interface isolation in PSE s Isolated signal Monitoring/Control Instrumentation Data Acquisition FUNCTIONAL BLOCK DIAGRAM SAFETY & EMC COMPLIANCE UL1577 recognition: 2500 Vrms CSA Component Acceptance Notice #5A IEC conformity (Pending) VDE certification conformity: IEC (Pending) GENERAL DESCRIPTION The AS1705 is a seven channel digital isolator based on Akros Silicon s proprietary silicon isolation technology which provides up to 2.5kVrms withstand voltage per UL1577. Five of the AS1705 channels are unidirectional; four are in the same direction and one is in the opposite direction. The remaining two channels are bidirectional configured for I 2 C interface isolation. Achieving fast propagation times, these isolators provide outstanding performance far superior to competing alternatives such as opto-couplers supporting both prevention of data latching and 3.4MHz I 2 C high speed bus requirements.

2 TABLE OF CONTENTS SAFETY & EMC COMPLIANCE... 1 GENERAL DESCRIPTION... 1 ORDERING INFORMATION... 1 TYPICAL APPLICATIONS... 1 FUNCTIONAL BLOCK DIAGRAM... 1 TABLE OF CONTENTS... 2 FIGURES... 2 TABLES... 2 PIN DESCRIPTIONS... 3 DEVICE FUNCTION DESCRIPTIONS... 3 TEST SPECIFICATIONS... 4 BLOCK DETAILS... 8 FUNCTIONAL DESCRIPTION... 9 APPLICATION INFORMATION... 9 TIMING RELATED PARAMETERS START UP/SHUTDOWN UNIDIRECTIONAL CHANNELS BIDIRECTIONAL I 2 C CHANNELS PACKAGE SPECIFICATIONS CONTACT INFORMATION IMPORTANT NOTICES LEGAL NOTICE REFERENCE DESIGN POLICY LIFE SUPPORT POLICY SUBSTANCE COMPLIANCE FIGURES Figure 1- AS1705 Typical Operating Circuit... 8 Figure 2 - Test Circuit for Unidirectional Channels Figure 3 - Test Circuit for Bidirectional I 2 C Channels Figure 4 - Common-Mode Transient Immunity Test Circuit Figure 5 - AS1705, 20-pin SOIC Dimensions TABLES Table 1 - AS1705 Signal Descriptions... 3 Table 2 - Device Function Table AS1705 Unidirectional Channels... 3 Table 3 - Absolute Maximum Ratings... 4 Table 4 - Normal Operating Conditions... 4 Table 5 - Isolation Electrical Characteristics... 4 Table 6 - Package and Thermal Protection Electrical Characteristics... 4 Table 7 - Side 1/2 (DC Voltage) Electrical Characteristics... 5 Table 8 - Side 1/2 (Current) Electrical Characteristics:... 6 Table 9 - Side 1/2 (Switching) Electrical Characteristics

3 PIN DESCRIPTIONS Table 1 - AS1705 Signal Descriptions AS1705 Name I/O Description 1 VDD1 P Supply voltage, side 1. 2 RSTA O Output, side 1 3,4,5 PWROUT O Output side 1 6 INTA I input side 1 7 SDAA OD Bidirectional I/O side 1 (for I 2 C Data). I 2 C Compatible (Special Logic signal levels) 8 SCLA OD Bidirectional I/O side 1 (for I 2 C clock). I 2 C Compatible (Special Logic signal levels) 9,10 GND1 P Ground, side 1 11,12 GND2 P Ground, side 2 13 SCLB OD Bidirectional I/O side 2 (for I 2 C clock). I 2 C Compliant (Conventional Logic levels) 14 SDAB OD Bidirectional I/O side 2 (for I 2 C Data). I 2 C Compliant (Conventional Logic levels) 15 INTB O Output side 2. 16,17,18 PWRIN1 I Input side 2 19 RSTB I Input side 2 20 VDD2 P Supply voltage, side 2 DEVICE FUNCTION DESCRIPTIONS Table 2 - Device Function Table AS1705 Unidirectional Channels VDD1 STATE VDD2 STATE Data Input Data Output Powered Powered H H Powered Powered L L Powered No Power X hold previous (unpowered side) No Power Powered X hold previous (unpowered side) 3

4 TEST SPECIFICATIONS Table 3 - Absolute Maximum Ratings CAUTION: Exceeding the maximum ratings specified in this table may cause permanent damage to the device. Parameter Min Max Unit VDD1: to GND1 6 V VDD2 to GND2 6 V INTA to GND1 1 6 V PWRIN1-3, RSTB to GND2 1 6 V PWROUT1-3, RSTA to GND V INTB to GND V SDAA, SCLA to GND1 1 6 V SDAB, SCLB to GND2 1 6 V ESD Rating, Human body model (per JESD22-A114) 4 kv ESD charged device model 500 V Storage Temperature C Operating Junction Temperature C 1 Inputs are all 5V tolerant irrespective of the supply voltage VDD1, VDD2 levels. Table 4 - Normal Operating Conditions Parameter Min Typ 1 Max Unit Conditions VDD1, VDD V VDD1 to GND1; VDD2 to GND2 Data, clock and I/O signal levels V Power dissipation mw TBD Operating temperature range C 1 Typical specifications not 100% tested. Performance guaranteed by design and/or other correlation methods. Table 5 - Isolation Electrical Characteristics Symbol Parameter Min Typ Max Unit Conditions 1 VISO_DC Rated insulation voltage - DC 4500 VDC RH 50%, Ta = 25 C, t = 1min VISO_AC Rated insulation voltage - AC 2500 Vrms RH 50%, Ta = 25 C, t = 1min IIO_ISO Input-output insulation leakage current 1.0 µa RH (Relative Humidity) = 45%, Ta = 25 C, t = 5s leakage current VIO_ISO = 2500 VDC 1 Device is considered a two terminal device: Side 1 pins are shorted together and Side 2 pins are shorted together. Table 6 - Package and Thermal Protection Electrical Characteristics Symbol Parameter Min Typ 1 Max Unit Conditions 1, 2 CI Input capacitance 10 pf CIO Side 1 to Side 2 capacitance 3 pf RIO Side 1 to Side 2 Resistance 10^12 Ω θ JC Thermal Resistance, Junction to Case 50 C/W 1 Typical values at: Ta = 25 C, VDD1, VDD2 = 5.0 VDC. Typical specifications not 100% tested. Performance guaranteed by design and/or other correlation methods. 2 Device is considered a two terminal device: Side 1 pins are shorted together and Side 2 pins are shorted together. 4

5 Table 7 - Side 1/2 (DC Voltage) Electrical Characteristics Symbol Parameter Min Typ 1 Max Unit Conditions VDD1/2 Side 1/ 2 supply voltage V Referenced to respective ground (GND1/2). THVDD_R VDD1/2 Under-Voltage Referenced to respective ground 2.3 V Threshold (rising) (GND1/2). THVDD_F VDD1/2 Under-Voltage Referenced to respective ground 2.1 V Threshold (falling) (GND1/2). VIH 0.7VDD V Unidirectional Channels VIL 0.3VDD V Unidirectional Channels VOH VDD-0.4 V IOH = -8mA (Unidirectional Channels) VOL 0.8 V IOL = 8mA (Unidirectional Channels) VOH VDD-0.1 V IOH = -20µA (Unidirectional Channels) VOL 0.1 V IOL = 20µA (Unidirectional Channels) VIH, S B 0.7VDD V I 2 C Compliant (Side 2, Bidirectional I 2 C channels) VIL, S B 0.3VDD V I 2 C Compliant(Side 2, Bidirectional I 2 C channels) VIH, S A 700 mv I 2 C Compatible (Side 1, Bidirectional I 2 C channels) VIL, S A 500 mv I 2 C Compatible (Side 1, Bidirectional I 2 C channels) VOL, S B 400 mv IOL = 30mA I 2 C Compliant (Side 2, Bidirectional I 2 C channels) VOL, S A mv IOL = 3mA I 2 C Compatible (Side 1, Bidirectional I 2 C channels) VL Side 1: Input /Output Logic Low Level Difference 2 50 mv I 2 C Compatible (Side 1, Bidirectional I 2 C channels) VL Side 2: Input /Output Logic Low Level Difference VDD mv I 2 C compliant (Side 2, Bidirectional I 2 C channels) 1 Typical values at: Ta = 25 C, VDD1/2 = 3.3 V/5V DC (unless otherwise noted). Typical specifications not 100% tested. Performance guaranteed by design and/or other correlation methods. All voltages are relative to their respective ground. 2 VL = (VOL VIL). This is the minimum difference between the output logic low level and the input logic threshold within a given component. This ensures there is no possibility of the part (I 2 C channels) latching up the bus to which it is connected. 5

6 Table 8 - Side 1/2 (Current) Electrical Characteristics: Symbol Parameter Min Typ Max Unit Conditions DC Supply Current No load I DD1(Q) Input Supply Current Side 1 I DD2(Q) Input Supply Current Side SCLA=SDAA=VDD1=5V SCLA=SDAA=0; VDD1=5V ma SCLA=SDAA=VDD1=3.3V SCLA=SDAA=0; VDD1=3.3V 6 10 SCLB=SDAB=VDD2=5V 6 10 SCLB=SDAB=0; VDD2=5V ma 6 10 SCLB=SDAB=VDD2=3.3V 6 10 SCLB=SDAB=0; VDD2=3.3V Switching Supply Current Figure 1 I DD1(Q) I DD2(Q) Leakage Currents Input Supply Current Side 1 Unidirectional inputs at DC and Bidirectional inputs switching Input Supply Current Side 2 Unidirectional inputs at DC and Bidirectional inputs switching ma ma R1=1kΩ; R2=120Ω; VDD1=3.3V 100kHz switching frequency 33% duty cycle R1=1.6kΩ; R2=180Ω; VDD1=5V 3.4MHz switching frequency 33% duty cycle R1=1kΩ; R2=120Ω; VDD2=3.3V 100kHz switching frequency 33% duty cycle R1=1.6kΩ; R2=180Ω; VDD2=5V 3.4MHz switching frequency 33% duty cycle I PWRIN, I RSTB, I INTA, I S A, I S B Input Leakage Currents µa VDD1=VDD2=5.5V 2.7V VDD1 5.5V, 2.7V VDD2 5.5V; Typical values at: Ta = 25 C, (unless otherwise noted). All Min/Max specifications apply over the entire normal operating range unless otherwise noted. Typical specifications not 100% tested. Performance guaranteed by design and/or other correlation methods. All voltages are relative to their respective ground. 6

7 Table 9 - Side 1/2 (Switching) Electrical Characteristics Symbol Parameter Min Typ Max Unit Conditions Unidirectional Channels Specifications t PLH, t PHL Propagation Delay µs C i Input capacitance to ground 2 pf CM Common Mode transient immunity kv/ µs Bidirectional I 2 C Channel Specifications Figure 3 Timing specifications for Unidirectional are preliminary CL=10pF±20%, CMOS Signal levels f CLK Clock frequency MHz 33% Duty cycle C IN Input Capacitance 2 pf tf1_1 Fall Time side 1 tf2_1, Fall Time side 2 t PLH1_1 1 t PHL1_1 2 t PLH2_1 3 t PHL2_1 4 Propagation Delay Rising Edge from side1 to side2 Propagation Delay Falling Edge from side1 to side2 Propagation Delay Rising Edge from side2 to side1 Propagation Delay Falling Edge from side2 to side1 CL=10pF CL=100pF CL=10pF CL=100pF CL1=10pF CL1=10pF CL1=10pF CL1=10pF ns ns ns ns ns ns Maintain output V O >0.8V (high level) or V O < 0.8V (for low level) at this slew rate. External pull up (R1) equivalent to 3mA External pull up (R2) equivalent to 6mA R1=1kΩ; R2=120Ω; VDD1/2=3.3V R1=1.6kΩ; R2=180Ω; VDD1/2=5V R1=1kΩ; R2=120Ω; VDD1/2=3.3V R1=1.6kΩ; R2=180Ω; VDD1/2=5V R1=1kΩ; R2=120Ω; VDD1/2=3.3V R1=1.6kΩ; R2=180Ω; VDD1/2=5V R1=1kΩ; R2=120Ω; VDD1/2=3.3V R1=1.6kΩ; R2=180Ω; VDD1/2=5V 1 The pulse width distortion (PWD) is specified at the maximum data rate and minimum pulse width. 1 t PLH1_1 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDD2 2 t PHL1_1 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V 3 t PLH2_1 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDD1 4 t PHL2_1 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V 2.7V VDD1 5.5V, 2.7V VDD2 5.5V; Typical values at: Ta = 25 C, VDD1=VDD2=5V (unless otherwise noted). All Min/Max specifications apply over the entire normal operating range unless otherwise noted. Typical specifications not 100% tested. Performance guaranteed by design and/or other correlation methods. All voltages are relative to their respective ground. 7

8 BLOCK DETAILS Figure 1- AS1705 Typical Operating Circuit 8

9 FUNCTIONAL DESCRIPTION The AS1705 comprises of seven digital isolators. Two isolators are bi-directional and are configured to provide isolated High Speed I 2 C two wire communication buffering and level shifting. Five unidirectional digital isolators are included for providing isolated buffering and/or level shifting for control logic signals. Each unidirectional channel can only be used in the direction shown in the functional block diagram. The five unidirectional channels operate independently. The output driver of each unidirectional channel does not need pullup resistors. The outputs are able to drive CMOS logic inputs. There are many applications requiring ground isolation or logic-level translation between devices where the I 2 C protocol is very useful. Systems in which devices on either side of the isolation barrier may function as bus master need bidirectional isolation of both lines of the I 2 C bus. The AS1705 are digital isolators with dual non latching bidirectional communication channels compatible with I 2 C interfaces and support I 2 C clock stretching. Internally the I 2 C is split into two unidirectional channels communicating in opposing directions via a dedicated Akros GreenEdge isolation channel for each. Both the Side 1 and the Side 2 I 2 C pins are designed to interface to an I 2 C bus operating in the 2.7 V to 5.5 V range. A logic low on either causes the opposite pin to be pulled low enough to comply with the logic low threshold requirements of other I 2 C devices on the bus. A distinction is made between I 2 C compatibility and I 2 C compliance. I 2 C compatibility refers to situations in which a component's logic levels do not necessarily meet the requirements of the I 2 C specification but still allow the component to communicate with an I 2 C -compliant device. I 2 C compliance refers to situations in which a component's logic levels meet the requirements of the I 2 C specification. Avoidance of I 2 C bus contention is ensured by having one side of the AS1705 with conventional logic level thresholds that are I 2 C compliant while the other side has special logic levels (3 levels as opposed to two) that are I 2 C compatible. The I 2 C compatible side (side 1 in AS1705) has an input low threshold guaranteed to be at least 50 mv less than the output low signal at the same pin. This prevents an output logic low at I 2 C compatible side from being transmitted back to I 2 C compliant side and pulling down the I 2 C bus. The output logic low levels are independent of the VDD1 and VDD2 voltages. The input logic low threshold at the I 2 C compatible side is also independent of VDD. However, the input logic low threshold at the I 2 C compliant side is designed to be at 0.3 VDD, consistent with I 2 C requirements. Both sides have open-collector outputs whose high levels are set via external pull-up resistors to their respective supply voltages. The logic low output from the I 2 C compatible receiver is 0.75 V (typical). This is low enough to be read as an input low by other standard CMOS devices, but high enough to avoid being interpreted as a logic low by the I 2 C compatible transmitter, which has its logic low threshold at 0.6 V (typical). Therefore, an output low from the Side 1 receiver is properly detected by devices connected to the bus, but is not fed back to Side 2 by the Side 1 transmitter. This prevents the bus problems commonly associated with opto-coupler solutions while still supporting clock frequencies up to 3.4 MHz. Because the feedback loop is broken at Side 1, there is no need to do the same at Side 2. On that side, standard logic voltage levels are used. Data transfer can occur at up to 100 kbps (standard mode), 400 kbps (fast mode), 1 Mbps (fast mode plus), or 3.4 Mbps (high speed mode). There is no limit to the number of devices that can be connected to the bus as long as a 100 pf bus limit is not exceeded. APPLICATION INFORMATION For years designers of industrial and telecommunication systems have used transformers and opto-couplers for isolation. But recent breakthroughs in silicon isolation technology have spawned faster, smaller and more costeffective solutions. Designers use isolation to improve safety requirements or remove ground noise loop problems. Isolation ensures data transfer without a closed loop electrical connection but imposes a penalty of delays and power constraints. Akros GreenEdge digital isolators meet this goal of safety and reduced noise while minimizing the penalties incurred. Designers need to consider key parameters such as power consumption and timing parameters like propagation delay, pulse width distortion and common mode transient immunity in addition to field related specifications such as EMI and susceptibility to surge events. Akros GreenEdge digital isolators use capacitive coupling to transfer data across the isolation barrier. The benefit of capacitors as opposed to other isolation techniques such as magnetic coupling for example is that they use low currents to create the coupling electric field. This is especially noticeable at high data rates. Timing specifications are important in isolator applications to ensure consistent and correct system operation. Unlike opto-couplers the digital isolators timing parameters are a function of internal precision timing circuits and fixed propagation delays within the signal path. All timing parameters vary only slightly with supply voltage and remain flat with temperature. 9

10 Figure 2 - Test Circuit for Unidirectional Channels Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal s timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single AS1705 component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple AS1705 components operating under the exact same conditions. Figure 3 - Test Circuit for Bidirectional I 2 C Channels Common mode transient is one of the leading causes of data corruption in isolated systems. Common Mode transient Immunity (CMTI) is commonly measured (figure 4) in kv/µsec and refers to the ability of an isolator to reject noise present between the isolator input and output. The Akros GreenEdge digital isolator has a typical CMTI of 35kV/µsec substantially higher than opto-couplers. Figure 4 - Common-Mode Transient Immunity Test Circuit TIMING RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to logic high. START UP/SHUTDOWN Unidirectional Channels The AS1705 unconditionally drives the output low when the supplies are below it s under voltage lockout (UVLO) threshold which is 2.7V typical during power up. The UVLO has hysteresis and AS1705 typically enters shutdown when the supplies fall below 2.5V. The behavior of the AS1705 when the power to the input (/transmit) side is lost is summarized in Table 2. The true fail safe feature of the AS1705 ensures the outputs are in a stable state in the event power is lost on the input/transmit side. The AS1705 also monitors the input line for idle conditions. If there is no activity (logic transitions) on the input for more than 1 µsec the AS1705 starts an internal timer that reverts the output to its default state (Table 2) after 5 µsec. Bidirectional I 2 C Channels The under voltage lockout (UVLO) feature on VDD1/2 prevents the bidirectional I 2 C channels from operating unless certain criteria are met. This avoids the possibility of input logic low signals from pulling down the I 2 C bus inadvertently during power-up/power-down. The two criteria that must be met in order for the signal channels to be enabled are as follows: Both supplies must be at least 2.5 V. At least 40 µsec must elapse after both supplies exceed the internal startup threshold of 2.5 V. Until both of these criteria are met for both supplies, the I 2 C outputs are pulled high, ensuring a startup that avoids any disturbances on the bus. All devices connected to the bus must be at a logic high state in order for the bus to be at a logic high state. When this situation exists for both the SDA and SCL lines, the bus is considered to be free for a device to initiate a data transfer. Both SDA and SCL are bidirectional lines to support the ability of devices to take on both transmitter and receiver roles. Hence the default output state is always HIGH during power up/down or during shutdown due to any fault condition. 10

11 PACKAGE SPECIFICATIONS Figure 5 - AS1705, 20-pin SOIC Dimensions 11

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