Clock Jitter Estimation and Suppression in OFDM Systems Employing Bandpass Σ ADC

Transcription

1 Clock Jitter Estimation and Suppression in OFDM Systems Employing Bandpass Σ ADC Bakti Darma Putra and Gerhard Fettweis Vodafone Chair Mobile Communications Systems Technische Universität Dresden, D Dresden, Germany {baktidarmaputra, Abstract In this paper, we analyze the effect of clock jitter on the performance of OFDM-based systems applying digital IF architecture A bandpass Σ ADC is used for the analog to digital conversion process An accurate and realistic model of the clock jitter in bandpass Σ ADC is implemented Results from this paper show that clock jitter severely degrades OFDM system performance by introducing both phase and waveform noise It is shown that for the case of sampling at IF stage, the effect of waveform noise is quite small and negligible compared to the phase noise effect Therefore, an estimation and compensation method based on the existing phase noise compensation method is proposed for alleviating the effect of clock jitter Simulation results are presented, showing the significant performance gain of our proposed algorithm, providing a new and innovative way of dealing with the clock jitter problem of bandpass A/D conversion in OFDM systems Index Terms - Sigma-delta modulators, analog-to-digital conversion, clock jitter, signal-to-noise ratio I INTRODUCTION The trend in modern communications is to create a flexible communication system which supports multi-standard and multi-mode transmissions This means being able to handle many different carrier frequencies and bandwidths Systems employing A/D conversion at an early stage play an important role for achieving such a flexibility at the receiver Digital IF is perceived as one of the most promising candidate technology The idea is to perform an A/D conversion of the received signal at IF stage and then process the signal content digitally 1] 2] This means providing a higher degree of reconfigurability at the software level by programming the communications system Furthermore, the problems associated with analog baseband demodulation, such as I/Q imbalance and DC offset, can be avoided by implementing this scheme The concept of digital IF has become even more attractive recently, especially for emerging systems which require higher transceiver flexibility while keeping the terminals compact in size and energy efficient (eg Opportunistic Radio, SDR) As commonly known, analog stages of the transceiver terminal usually comprise of bulky and energy consuming parts Replacing more analog parts with digital ones will significantly reduce the energy consumption as well as terminal dimension Despite all these supporting facts, there is still one main obstacle for implementing this architecture, which is the fact that it requires a fast high-bandwidth high-dynamic-range conventional ADC for converting radio signal with sufficient fidelity Fortunately, this is not the case for a bandpass Σ ADC A bandpass Σ ADC is able to selectively enhance the conversion resolution at a specific frequency band by its inherent capability of noise shaping and oversampling Recently, implementing high resolution bandpass Σ ADC at IF frequency have been made feasible However, as the sampling process occurs at higher frequency, the probability of sampling time error increases and introducing serious clock jitter problems 3] 4] To the author s best knowledge, so far there is no significant investigation on how to compensate the clock jitter effect in OFDM systems Therefore, the main question behind this paper is how to make this system work with this nonideal time reference without losing too much in performance The main contribution of this paper is to propose an estimation and compensation method of the clock jitter in digital domain in order to increase the system performance Furthermore, by implementing our proposed algorithm, we can gradually break the fundamental limit of implementing bandpass A/D conversion The remainder of this paper is organized as follows: the OFDM system model in digital IF architecture, followed by the discussion of the clock jitter effect on this system is addressed in Section II The clock jitter correction schemes are presented in Section III Simulation results are presented in section IV The conclusion will be given in section V A OFDM System M-QAM OFDM Demod r Fig 1 OFDM Mod Downconverter and Downsampler II SYSTEM MODEL s Upsampler and Upconverter rfilt Quantization Noise Filter sif radc Bandpass Σ Converter OFDM system on digital IF architecture rif Channel Channel Noise Rejection Filter The block scheme of the simulated OFDM system is depicted in Fig 1 We consider an OFDM system with N subcarriers, digitally modulated by Quadrature Amplitude

2 Modulation (QAM) symbols S k The OFDM modulator consist of Inverse Fast Fourier Transform (IFFT) process and cyclic prefix (CP) addition After grouping N QAM symbol into (N 1) vectors S = S 0, S 1,, S N 1 ], the OFDM modulator processes this vector by performing an IFFT and adding a CP to overcome the intersymbol interference (ISI) possibly introduced by a frequency selective channel The discrete-time of an OFDM symbol which is sampled at time instants t = nt s can be represented by s(n) = 1 N 1 S k e j2πkn/n, n = {0,, N 1, (1) n k=0 where T s is the sampling rate OFDM signal is then upsampled by a factor of OSR (oversampling ratio) and upconverted by an intermediate carrier frequency f IF The transmitted bandpass signal can be represented as follows: s IF (n) = Re { s up (n)e 2πf IF nt os (2) with s up as the upsampled version of the OFDM modulator output s and T os = T s /OSR is the sampling rate after oversampling process The signal is then transmitted through the channel The noise rejection filter is needed at the receiver part in order to avoid the aliasing problem This filter has the characteristic of a bandpass rectangular filter with the center freguency at f IF and bandwidth of W = 1/T s B Clock Jitter on Bandpass Σ ADC The bandpass Σ ADC at the receiver performs an A/D conversion at the IF stage Using the bandpass Σ ADC model from our previous work 3], we analyze the effect of clock jitter on the system performance Σ ADCs consist of a Σ modulator followed by a digital decimation filter The linear model of a discrete time (DT) Σ modulator is presented in Fig 2 The terms x(t) and y(n) in this linear model represent the input (r IF ) and the output (r ADC ) of the bandpass Σ ADC respectively In the condition of perfect sampling, the output of the modulator is defined as y(n) = (x(n) y(n)) h ADC (n) q(n) (3) where q(n) = y(n) u(n) and h ADC (n) represent the quantization error and the loop filter s impulse response, respectively x(t) x(n) = x(nt) f s - Fig 2 h ADC(n) u(n) q(n) Discrete time Σ modulator The output spectrum can be obtained by performing the Z- transform of equation (3) and rearranging it: ] ] 1 Y (z) = Q(z) X(z) (4) NT F (z) ST F (z) y(n) where NT F (z) and ST F (z) are the noise and signal transfer function, respectively The output of the modulator is now the input signal modulated by ST F (z) plus the quantization error modulated by NT F (z) As mentioned before, the sampling process usually contains uncertainty of the sampled signal due to the uncertainty of the sampling clock This process is mainly due to the instability of the oscillator which leads to sampling time errors at the input of the ADC In order to correctly model the clock jitter process, we use the result from Awad 5] With this approach, the time variation of the sampling process at time instant n1 can be expressed as follows: d n1 = d n δ n (5) where δ n is a Gaussian distributed random variable with zero mean and standard deviation (RMS cycle jitter) σ δn = c vco T 6] The constant c vco indicates the instability of an oscillator and T is the sampling clock period Reevaluating the bandpass Σ modulator model in Fig 2, in the presence of clock jitter, the output y j (n) now contains error from both the quantization noise and clock jitter, given by: y j (n) = (x(nt d n ) y j (n)) h ADC (n) q j (n) (6) By subtracting (3) from (6), the additional error due to jitter process is given by which leads to e y (n) = y j (n) y(n) (7) e y (n) = ((x(nt d n ) x(nt )) e y (n)) h ADC (n) (q j (n) q(n)) e x (n) e q(n) (8) Performing Z-transform of (8) yields the output spectrum under jitter condition as 1 E y (z) = ] ] E q (z) E x (z) (9) As indicated by (9), the error due to the clock jitter follows the STF, while the additional quantization noise in the presence of clock jitter is affected by the NTF This means that the spectrum of the clock jitter will occupy the frequency of interest and consequently reduce the achievable SNR at the output of the bandpass Σ ADC Since for this paper we restrict our scope of research on the clock jitter problem, we will select the order and OSR value of bandpass Σ such that the quantization noise in the band of interest can be approximated as zero and the STF can be designed to be approximately unity 7] In our case, we use a 6 th order bandpass Σ ADC with OSR = 8 Therefore, the above equation can be rewritten as: ] E y (z) = E x (z) (10) 1 After being sampled by the Σ ADC, the sampled IF OFDM signal can be represented as (11), where h(n) is the

3 r ADC = r IF (nt os d n ) = Re {s(nt os d n ) h(nt os d n ) η(n)]e j2πf IF (nt os d n ) { = Re s(nt os d n ) h(nt os d n ) η(n)]e j(2πf IF nt os φ(n)) (11) channel impulse response and η(n) is the AWGN The quantization noise rejection filter then removes all the quantization noise outside the frequency of interest After downconversion and downsampling process, the digitally low pass filtered baseband signal is given by r = s(nt s d n ) h(nt s d ] n ) e j φ(n) ὴ(n) (12) where d n is the representation of the time jitter after downsampling process with its new RMS cycle jitter = OSR σ σ δn δn and φ(n) = 2πf IF dn Noise ὴ(n) remains AWGN From equation (12) we can conclude that the clock jitter at bandpass A/D conversion introduces both the phase noise and waveform noise Moreover, for the system implemented in fading environment, clock jitter also introduces an additional channel estimation error Using the principle of Taylor series expansion, equation (12) can be modified as follows: r = (s(n) s (n) d n ) (h(n) h (n) d ] n ) e j φ(n) ὴ(n) (13) while s (n) and h (n) are the first derivatives of the transmitted signal and channel impulse response respectively III CLOCK JITTER COMPENSATION At the baseband, after removing the cyclic prefix and taking the DFT operation, the demodulated received symbol R l at subcarrier l 0,, N 1 is given as (14) Where S l, S n, H l and η l are the transmitted symbols on the subcarriers, the first derivative of the transmitted symbol, the channel transfer function at subcarrier l and AWGN term, respectively D(i) and Ď(i) are the frequency domain representation of d n and d 2 n respectively The terms I(i), i =,, 1 correspond to the DFT realization of e j φ(n) during one OFDM symbols, defined as follows: I(i) = 1 N N 1 n=0 e j2πni N e j φ(n) (15) The term I(0) is common to all subcarriers of one OFDM symbol, regarded as common phase error (CPE) The ICI term is caused by non-zero frequency components of phase noise process Additional term due to waveform and channel estimation error is called jitter-induced excess noise (JEN) However, the effect of waveform error to the system performance is so small and negligible compared to the phase noise Therefore, even though we run the simulation with the real clock jitter model, our algorithm is limited to the estimation and compensation of the error due to phase noise For the condition of more severe clock jitter, for example in a digital RF architecture, substantial performance gain can be obtained by performing compensation of the waveform error along with the one for the phase noise This issue will be addressed in detail within our next publication Result from 8] is used for the CPE estimation In order to correct the CPE, a set of pilots P are used Based on these pilots, the CPE can be estimated using least square estimation 9]: e jφ 0 I(0) = AH p R p A H p A p (16) where R p is the set of received pilot symbols and A p = H p S p H p and S p represent the channel and the transmitted pilot symbols respectively CPE compensation is not sufficient to recover the distorted signal In order to improve our phase noise estimation performance, we implement the minimum mean square estimaton (MMSE) for estimating ICI components Assuming the Lorentzian shape of the spectrum due to Wiener process, estimating several low frequency spectral components of the phase noise process results in the approximation of the phase noise realization within an OFDM symbol 10] Rewriting equation (14) into a vector matrix notation for a subset of C different received symbols R l1 up to R lc leads to the following set of linear equations 9]: R l1 R lc R lc R A l1 u A l1 A l1 u = A lc u A lc A lc u A lc u A lc A lc u A ζ ICI,l1 η l1 ζ ICI,lc η lc ζ ICI,lC {{ η lc ζ ICI η I(u) I(1) I(0) I( 1) I( u) I We estimate the spectral components I(i), i = u,, u, using minimum mean square estimation (MMSE) 11] Equation (17) can be rewritten in a more concise form as R = A I ɛ (18) where ɛ = ζ ICI η is the noise vector that represents the equivalent measuring noise (ICI AWGN) The MMSE estimate of the vector I is given by Î = M R (19) (17)

4 R l = S l H l (I(0)) CP E,n l S n H n I(l n) ICI n= m= ((S nh n S n H n) D l m I(l n) S nh nďl mi(l n)) η l JEN (14) while M = K II A H (AK II A H K ɛɛ ) 1, K II and K ɛɛ represent correlation matrices of I and ɛ respectively The calculation of K II is clearly explained in 10] The complete correction algorithm can be explained as follows: 1) An estimate Î(0) of I(0) can be obtained by performing least square estimation (LSE) to the set of known pilot symbols P in frequency domain The demodulated signal constellation is then derotated 2) Using such a derotated constellation, we make a decision to the transmitted signals and use these hard decision for the estimation of the Î(i), i = uu according to the MMSE method previously described 3) After obtaining the estimate of DFT coefficients Î(i), i = uu, the ICI cancellation for obtaining ICI free symbols is then performed in frequency domain by following method 10]: u R l = (R l S l v H l v I(v))Î (0) (20) v= u v 0 IV SIMULATION RESULTS ICI Correction (3 order) 10 4 Fig 3 Performance of OFDM system with bandpass Σ ADC under AWGN channel RMS cycle jitter is 16 ps The system s performance is studied for the case of WLAN(80211a) standard The system parameters used related with this standard is 48 carriers used for data, 4 carriers reserved for pilots and 12 zero subcarriers High order constellations which are 64-QAM and 256-QAM are used 80 MHz IF frequency carrier is choosen as comply with cellular 10 4 Fig 4 Performance of OFDM system with bandpass Σ ADC under AWGN channel RMS cycle jitter is 5 ps application We investigate the performance on both AWGN and fading channel (ETSI A) The simulation results can be differentiated into 4 different schemes, which are: 1) without clock jitter 2) clock jitter without CPE correction 3) clock jitter with CPE correction using LSE 4) ICI correction with initial CPE correction ICI correction can also be done iteratively to improve the system performance However the complexity of the algorithm is quite large Moreover, since the effect of clock jitter to our system is quite modest, the compensation method without iterative correction has already shown a good performance From the simulation result of the system in AWGN channel, which are shown in Fig3 and Fig4, we can conclude that without any compensation, signal heavily distorted by the clock jitter One can also see that the of both clock jitter condition, RMS cycle jitter of 16 ps and 5 ps, are reduced significantly after applying our algorithm Even with only implementing CPE correction already gives significant performance improvement, especially under moderate value of RMS cycle jitter as in Fig 4 Further refinement is then achieved by implementing ICI correction The ICI correction algorithm shows a significant performance improvement, especially under severe clock jitter condition (see Fig3) As expected, system with higher RMS clock jitter requires more approximation of the spectral components I(i) of the signal compare to the one with lower RMS clock jitter value

5 Fig 5 and Fig 6 show the result in the condition of Indoor Rayleigh fading channel (ETSI A) From these 2 graphs, one can see the robustness of our compensation method even in a more hostile channel condition For the case of RMS cycle jitter = 5 ps, ICI compensation can almost σ δn completely alleviate the effect of clock jitter from the system Basic CPE compensation has also already shows significant improvement to the system performance For extremely severe clock jitter condition in ETSI A channel (see Fig 6), ICI correction method with low order gives almost perfect clock jitter compensation model into OFDM system working under digital IF receiver architecture Our investigation reveals that the clock jitter in bandpass A/D conversion introduce both phase noise and waveform noise which in turn causing significant performance degradation In our system setup, phase noise is introducing more dominant effect to the system compare to the waveform one Results show that by only applying phase noise compensation method there exists significant improvement to the system performance, even in a very bad clock jitter condition Furthermore, our results show the robustness of the compensation method even in a severe channel condition Therefore, through the outcome of this paper, we bring out the solution to the fundamental limit of implementing bandpass A/D conversion ICI Correction (3 order) Fig 5 Performance of OFDM system with bandpass Σ ADC under ETSI A channel RMS cycle jitter is 16 ps 64 QAM 256 QAM REFERENCES 1] A Hairapetian, An 81-MHz IF Receiver in CMOS, IEEE Journal of Solid State Circuits, vol 31, pp , December ] T Salo, S Lindfors, T Hollman, J Jrvinen, and K Halonen, 80-MHz Bandpass Delta-Sigma Modulators for Multimode Digital IF Receivers, IEEE Journal of Solid-State Circuits, vol 38, pp , March ] BD Putra and G Fettweis, The Effect of Clock Jitter on the Performance of Bandpass Σ ADCs, IEEE International Symposium on Control, Communications and Signal Processing, 2008, ISCCSP 08, pp , March ] R Walden, Analog-to-digital converter survey and analysis, IEEE J Select Areas Commun, vol 17, pp , Apr ] S S Awad, Analysis of Accumulated Timing-Jitter in the Time Domain, IEEE Transactions on Instrumentation and Measurement, vol 47, no 1, pp 69 73, February ] MLöhning and G Fettweis, The effects of aperture jitter and clock jitter in wideband ADCs, International Journal Computer Standards and Interfaces (CS&I), vol 29(1), pp 11 18, January ] R Schreier and G C Temes, Understanding Delta-Sigma Data Converters, Wiley-IEEE Press, November ] S Wu and Y Bar-Ness, A Phase Noise Suppression Algorithm for OFDM based WLANs, IEEE Communications Letters, vol 6, no 12, pp , ] S Bittner, Wolfgang Rave, and Gerhard Fettweis, Joint Iterative Transmitter and Receiver Phase Noise Correction using Soft Information, IEEE International Conference on Communications (ICC 07), June ] D Petrovic, W Rave, and GFettweis, Effect of Phase Noise on OFDM Systems With and Without PLL: Characterization and Compensation, IEEE Transactions on Communications, vol 55, no 8, pp , August ] S M Kay, Fundamentals of Statistical Signal Processing I: Estimation Theory, Person Prentice Hall, 1998 Fig 6 Performance of OFDM system with bandpass Σ ADC under ETSI A channel RMS cycle jitter is 5 ps V CONCLUSIONS Emanating from our previous investigation on the effect of clock jitter on bandpass Σ ADC 3], we implement this