Design of Over GIGA bit Wireless LSI systems

Transcription

1 Design of Over GIGA bit Wireless LSI systems Yoshikazu Miyanaga Hokkaido University Laboratory of Information Communication Networks Graduate School of Information Science and Technology Sapporo , Japan

2 Contents Research Background OFDM, MIMO Proposed MIMO-OFDM System 600Mbps, 80 MHz Band by 2x2 MIMO-OFDM 2.6Mbps, 160 MHz Band by 4x4 MIMO-OFDM VLSI Design of Proposed Transceiver Super Low-Power LSI Design 2

3 Background on Methods Communication Methods Current Main Stream: 54MBPS (IEEE a,.11g) It is not enough when wireless USB and multi-media communication are considered. Establish of IEEE n Standardization Over 100 different methods have been nominated at the end of In late 2009, its standardization will be completed. The 600MBSP throughput of IEEE n is most suitable candidate as final one but it is not enough. The new standardization, i.e., IEEE ac, has started since 2008 Autumn. IEEE ac is now trying to develop a system over 1 Gbps wireless throughput with beyond 80MHz. 3

4 Transmit Speed Current Trend of MIMO-OFDM Systems IEEE Standards Development by Hokkaido Univ. (Baseband) 1Gbps IEEE VHT Study Group Hokkaido Univ. 4x4 MIMO-OFDM (2008) 1.5 Gbps 500M bps IEEE802.11n Optional (2008?) 600Mbps IEEE802.11a (2002) 54Mbps IEEE802.11n Draft (2007) 300Mbps Hokkaido Univ. 2x2 MIMO-OFDM (2006) 600 Mbps Hokkaido Univ. SISO-OFDM (2005) 300 Mbps 20MHz 40MHz 60MHz 80MHz Bandwidth

5 Background on Systems Digital Baseband (BB)+ Radio Frequency (RF) MIMO indicates many antennas. A system will be large. Its decoder must be quite complicated. A package of a low power consumption system including BB and RF can be designed, cannot it? A real MIMO-BB chip has been developed but what kind performance can be realized? Is it possible to realize 4x4, 6x6 larger MIMO system in LSI? 5

6 Basic OFDM System Input Data Mapping S/P IFFT Guard Interval P/S D/A channel Output Data Demapping P/S Equalizer FFT Delete GI S/P A/D

7 Basic OFDM System p FFT within several nano second Coder: cov, blk Input Data Mapping S/P IFFT Guard Interval P/S D/A Low Power Design channel Output De-Coder: Data Viterbi, LDPC Demapping P/S Equalizer FFT Delete GI S/P A/D p FFT within several nano second

8 MIMO System Transmitter Receiver TX Encoder Encoder Mapper Mapper IFFT IFFT FFT FFT MIMO Detector De-Mapper De-Mapper Decoder Decoder RX

9 MIMO Decoding Circuit The instance when the receiver gets the training symbols The estimation of channel and the inverse matrix calculation should be completed. The instance when the receiver gets data symbols MIMO decoding should be done. from FFT A, Β Channel Estimation H (from 1st and 2nd training symbols) y MIMO Detector G s Inverse Matrix 1 G Memory

10 MIMO Decoding Circuit Super high speed & Ultra low power. from FFT A, Β H (from 1st and 2nd training symbols) 1 G y Channel Estimation Low Power Design Inverse Matrix Memory MIMO Detector s GMatrix Inversion within several nano second

11 Overview One Chip/Package Wireless System A total system including interface, BB, RF and antennas. The Next Generation LAN/PAN: Super Speed Hot Spot, Wireless Home Theater, Next Generation High Speed LAN etc Realization of both high speed and Low power High Speed Wireless 2.6 GBPS Throughput High Performance MIMO System In Door Wireless Very Low Power BB-LSI 1W System Dynamic Architecture Optimum Low Power Consumption Soft Wireless High Throughput and Low Power Consumption 11

12 Wireless Communication Chip Con MAC OFDM: Modulation/De-Modulation IEQ: Intelligent Equalizer Con: System Controller MAC: Media Access Controller MIMO: Multi I/O Module RF: Radio Frequency Analog Circuits OFDM IEQ MIMO Antenna RF 12

13 Conventional Wireless Communication Chip Conventional.11a 54MBPS.11n 300MBPS mW power consumption Conventional BLAST 4x4 Streams Distance: Several meters 2x3MIMO System Con MAC OFDM MIMO General Networks Antenna RF 13

14 Proposed Wireless Communication Chip 1SISO 300MBPS by parallel/pipeline processing General Networks 2 Low Power Consumption of 300mW by Dynamic Architecture 3BER Improvement by Noise Reduction 4 Cognitive OFDM System Con MAC 1 4x4 MIMO-OFDM 2 700mW Power Consumption 3 2.6GBPS Throughput OFDM MIMO Antenna RF 14

15 MIMO, OFDM. BASIC TECHNOLOGIES 15

16 Basic OFDM System Input Data Mapping S/P IFFT Guard Interval P/S D/A channel Output Data Demapping P/S Equalizer FFT Delete GI S/P A/D 16

17 OFDM OFDM Orthogonal Frequency Division Multiplexing One of Digital Modulation Technique in which many orthogonal carrier are multiplexed. OFDM is important, isn t it? Several key systems, e.g., surface digital TV of Japan and EU, High Speed ADSL MODEM, Wireless LAN etc employs OFDM. OFDM can be fabricated into LSI. 17

18 Digital Modulation s( t) Acos(2 f c t k ) ASK : Amplitude Shift Keying PSK : Phase Shift Keying FSK : Frequency Shift Keying bit/1 symbol Modulation Technique 18

19 ASK and PSK Modulation in OFDM Multi-Valued Modulation Technique 1 symbol represents several bits at one time. Binary PSK (BPSK) Quadrature PSK (QPSK)

20 Representation of Digital Modulation The signal s(t) in communication can be represented as where f t e j 2 c ak jb k s( t) Re[( a k jb ) e j2 f t : carrier component : digital modulation component : signal k c ] All digital signals are represented as complex values: ( a k jb k ) e j2 f c t 20

21 QAM (Quadrature Amplitude Modulation) a The digital components k jb k in case of QPSK can be represented in the complex domain. 2 2 j j j j

22 16QAM and 64QAM 16QAM 64QAM 22

23 Data Mapping on Spectrum Domain Data are assigned onto spectrum domain. Accordingly, each complex signal can be mapped to each frequency. High efficiency can be kept within a communication bandwidth. 23

24 Basic OFDM System Input Data Mapping S/P IFFT Guard Interval P/S D/A channel Output Data Demapping P/S Equalizer FFT Delete GI S/P A/D 24

25 Basic OFDM System Input Data Mapping S/P IFFT Guard Interval P/S D/A channel Output Data Demapping P/S Equalizer FFT Delete GI S/P A/D 25

26 Gard-Interval The n-th Symbol T G T FFT T G Same data are copied. 26

27 Multi-Path Fading Same signals are coming to a receiver with different time delays. 27

28 GI and Multi-Path 1 st transmitted data stream 2 nd transmitted data stream A receiver can get an original symbol but a phase rotation happens by multi-paths. 28

29 Influence to Symbols Phase Rotation on Complex Domain 29

30 Basic OFDM System Input Data Mapping S/P IFFT Guard Interval P/S D/A channel Output Data Demapping P/S Equalizer FFT Delete GI S/P A/D 30

31 2 2 MIMO System Transmitter TX Receiver Encoder Encoder Mapper Mapper IFFT IFFT FFT FFT MIMO Detector De-Mapper De-Mapper Decoder Decoder RX 31

32 MIMO Decoder Linear Decoding ZF MMSE Sequential Decoding V-BLAST (ZF Criterion) V-BLAST (MMSE Criterion) Cost Low High Performance Low High 32

33 Zero-Forcing (1) MIMO Channel Model y Hs n Received Signal Channel Matrix Transmitted Signal Noise The inverse matrix of an estimated channel matrix is applied and then the original transmitted signal is estimated. s H 1 y 33

34 Zero-Forcing (2) Calculation of Inverse Matrix In case of 2x2 matrix, its processing can be implemented as inverse matrix equation explicitly. H a b c d 1 H 1 ad bc d c b a 34

35 MIMO Decoding Circuit In case of the receive of training symbol: Blocks of channel estimation and inverse matrix calculation are activate. In case of the receive of data symbol: A block of MIMO decoding is activate. from FFT A, Β Channel Estimation H (from 1st and 2nd training symbols) y MIMO Detector G s Inverse Matrix 1 G Memory 35

36 Contributes in this Study New MIMO-OFDM Systems by Our Project IEEE a/g (54 Mbps) Wideband SISO-OFDM (300 Mbps) New OFDM Format at MHz Bandwidth VLSI Design of OFDM Transceivers 2x2 MIMO-OFDM (600 Mbps) 4x4 MIMO-OFDM (2.6 Gbps) 36

37 Proposed 2x2 MIMO-OFDM Format Transmit mode Mode Coding Rate Modulation Data Rate (Mbps) SISO-OFDM Data Rate (Mbps) MIMO-OFDM 1 1/2 QPSK /2 16QAM /2 64QAM /4 64QAM Frame Format FFT/IFFT Window Length 6.4 us (512 samples) Guard Interval Length 0.8 us (64 samples) Number of Subcarriers 512 Number of Data Subcarriers 480 Frequency Spacing MHz 37

38 Transmit Performance Packet Size: 1000-byte Packet Length Modulation: 64-QAM Channel Model: 150-ns Delay Spread TGn Channel Model D Evaluation 4x4 IEEE802.11n (600 Mbps, 5/6-Coding Rate) 4x2 Proposed-MIMO (600 Mbps, 3/4-Coding Rate) 2x2 Proposed-MIMO (600 Mbps, 3/4-Coding Rate) 38

39 Bit Error Rate BER Performance x4 IEEE802.11n 4x2 STARC-MIMO 2x2 STARC-MIMO dB Average CNR per Receiver Antenna [db] 39

40 SISO-OFDM System Specification 512-point FFT/IFFT IIR Filter Type Flame Syncronization Convolutional Coding Soft Viterbi Decoding (Constraint Length 7 Rate 1/2) QPSK, 16QAM, 64QAM Mod/De-Modulation Metric 16bit 6 BB Receiver 12bit BB Transmitter 12bit MAC Receiver 3bit MAC Transmitter 3bit OFDM Viterbi Error Correction Output 3bit 40

41 SISO-OFDM (ASPLA 90nm) mm 2 Game # Power Con Tra (mw) Power Con Rec (mw) System Control Coding/Mapping Flame Synchronization FFT/IFFT, Channel Eq GI Preamble Signal Pro Modulation/Sync. SRAM Demodulation GI SRAM Soft Viterbi Viterbi Decoding Total 4,289,401 1,429,

42 FPGA Board for Evaluation Gigabit Ethernet PHY Xilinx Gigabit Ethernet MAC STARC MAC Altera STARC PHY Output

43 2x2 MIMO-OFDM SDM-MIMO Decoding Transmission Rate 600Mbps Transmission Distance It is shorter than our proposed 4x2 MIMO-OFDM System Overview 2 Parallel SISO-OFDM MIMO Decoding 43

44 MIMO System Transmitter Receiver TX Encoder Encoder Mapper Mapper IFFT IFFT FFT FFT MIMO Detector De-Mapper De-Mapper Decoder Decoder RX 44

45 PPDU Format The format is based on 02.11n and STARC MIMO- OFDM PPDU. Number of training symbol is set to 2. SC-STF SC-AGC SC-LTF SC-SIG, DATA St.1 I -I St.2 I I SNR Estimation Channel Estimation 45

46 Simulation Results SISO MIMO Mapping Coding Bandwidth FFT # 64QAM Convolutional Coding (R=1/2) Viterbi Decoding 80M Hz 512 (data:480, pilot:20) OFDM Symbol # 8 TX Rate 200M bps 400M bps Antenna # 1 x 1 2 x 2, 4 x 2 Channel Model HYPERLAN2/Model A AWGN TGn Sync Channel/Model D AWGN Channel Est. Legacy Orthogonal Coded Pilot MIMODecoding 2x2 ZERO-FORCING 2x2 BLAST (MMSE) 4x2 G-LST (MMSE) 46

47 Results 1.00E E-01 STARC SISO 2x2 MIMO zero-forcing 2x2 MIMO BLAST_mmse 4x2 MIMO VLSTBC_mmse 1.00E-02 BER 1.00E E E CNR 47

48 Circuit Structure of 2x2 MIMO-OFDM Transceiver Full-Pipelined Processing Duplicated Processing Blocks Supporting for Two Data Streams (A) Encoding & Mapping (D) GI/PLCP Insertion (E) Pre- Transform Memory (C) FFT/IFFT (F) Post- Transform Memory (B) Frame Sync. (G) MIMO Detection (H) De- Mapping (I) Viterbi Decoding Transmitter ZF, MMSE, V-BLAST,... Receiver 48

49 Dynamic Architecture of Low Power OFDM BB Transmitter Sensor Monitering OFDM BB Receiver Sensor OFDM BB Receiver OFDM BB Transmitter Realization of High Throughput and Low Power All right reserved. All right reserved. Copyright Copyright Yoshikazu Yoshikazu Miyanaga, Miyanaga Hokkaido Univ.

50 Timing of MIMO Decoding High Latency Type (It can be designed by General Purpose Processor) Merit... Circuit Scale is small. Demerit... Long processing time is required. Training Symbols Data Symbols T 1 T 2 D 1 D 2 D L D K Channel Est Inv. Matrix or QR Deconv Latency Low Latency Type (Pipeline and Parallel Processing are used ) Demerit... Circuit Scale is large and it is complicated. Merit Small Circuit size is obatained. MIMO De-convolution T 1 T 2 D 1 D 2 D L D K Latency (In case of GI time, it is 0)

51 Channel Estimation & Inverse Matrix 1 OFDM symbol sampling time 512(FFT)+64(GI)=576 Processing time of Channel Est and Inv Matrix 480(Data Subcarriers) + 11 (Pipeline Latency) = 491 A1 A2 Processing can be done in 1 symbol. B 1 H 11 H 11 G 11 H 12 H 12 G 12 H 21 H 21 B 2 G 21 H 22 H 22 G 22 H 11H 22 H 12H 21 * * 1 *

52 VLSI Implementation of OFDM Transceivers Circuit Design Fixed-Point Simulation: Matlab RTL Design: Verilog CMOS Implementation ASPLA 90nm SISO-OFDM Transceiver 2x2 MIMO-OFDM Transceiver 52

53 Circuit Performance Detection Algorithm Zero Forcing MMSE-BLAST No. of Subcarriers 480 No. of Pipeline Stages Pipeline Latency (μs) No. of Complex Multipliers 8 16 No. of Real Multipliers Clock Frequency (MHz) 2x2 MIMO-OFDM Decoder 80 NAND Gate Count 371,537 1,160,092 53

54 2x2 MIMO-OFDM (MIMO Decoding :ZF ) (ASPLA 90nm) Area Power Power Gate # (mm 2 ) TX (mw) RX (mw) System Control Coding/Mapping Flame Syncronization FFT/IFFT MIMO Decoding GI PLCP Addition Modulation/Syncro SRAM De-Mod/GI Addition SRAM Soft Decision Viterbi De-Modulation 合計 9,209,872 3,069,

55 Implementation Results Circuit Area (mm 2 ) No. of Logic Gates Power TX (mw) Power RX (mw) SISO-OFDM M x2 MIMO-OFDM M

56 SC-STF SC-AGC SC-LTF SC-LTF SC-LTF SC-LTF SC-LTF SC-SIG DATA DATA 80MHz 20MHz Proposed MIMO-OFDM PPDU Format 64μs 8.0μs 8.0μs 4.0μs 4.0μs 2.0μs 2.0μs 28.8μs 7.2μs 7.2μs L-STF L-LTF L-SIG HT-SIG 7.2μs Tx1 L-STF L-LTF L-SIG HT-SIG L-STF L-LTF L-SIG HT-SIG L-STF L-LTF L-SIG HT-SIG IEEE802.11a Compatible Preamble & SIGNAL TGnSync Compatible 56

57 Real-time MIMO Detection MIMO-OFDM systems must compute inverse matrices of the channels for all the subcarriers. Proposed Algorithm Complexity SISO V-BLAST 2 3 =8 4x2 MIMO V-BLAST & STBC 4 2 =16 IEEE802.11n 4x4 MIMO V-BLAST 4 3 =64 (Use of QR decomposition) Processing time of MIMO detection influences response time in PHY and MAC layer. Low-Latency and High-Throughput Architecture 57

58 Overview of 4 2 V-LSTBC System Max Throughput 600Mbps 4 2 V-LSTBC System Using LST(SDM), the throughput increases. Using STBC, the transmission length increases. 4 2 V-LSTBC Decoding 4 The cost of O M can decrease to 2 O M by using new algorithm. PPDU Flam Format is proposed. IEEE802.11a/IEEE802.11n based Format Using GA, its preamble is optimized. Evaluation of System based on standard channel models Transmission with 600 Mbps(MAX) 20m transmission 58

59 HU-VHT MIMO-OFDM Transmitter A FEC Enc Puncture Spatial stream parse frequency Interleaver frequency Interleaver Mapper Stream 1 Mapper Stream2 S/P S/P STBC Encoder STBC Encoder IFFT IFFT IFFT IFFT P/S P/S P/S P/S B C D 59

60 HU-VHT MIMO-OFDM Receiver Channel 1 2 S/P S/P FFT FFT Estimator Interference Canceller Channel P/S P/S frequency De-Interleaver frequency De-Interleaver De-Mapper De-Mapper Spatial Stream De-parse De-Puncture Viterbi Dec Estimator 60

61 PER HU-VHT MIMO-OFDM vs. IEEE802.11n(Model B) x4 IEEE802.11n dB x2 V-LSTBC 4x2 HU-VHT STARC-MIMO (iid) 4x2 HU-VHT STARC-MIMO (corr) 4x4 IEEE802.11n (iid) 4x4 IEEE802.11n (corr) CNR [db] 61

62 Distance [m] Comparisons of Link Budget STARC HU-VHT IM=5[dB] TGn IM=5[dB] STARC HU-VHT IM=10[dB] TGn IM=10[dB] m is improved All right reserved. Copyright CNR Yoshikazu [db] Miyanaga 62

63 Block Diagram of 4x4 MIMO-OFDM Circuit Transmitter Scrambler Encoder Interleave Mapper Pilot & Puncture Insertion Receiver Demapper IFFT Re-order & GI Insertion Viterbi Decoding Preamble Insertion Frame & Freq. Synchronization FFT Re-order & Pilot Remove MIMO Channel Est. & Decoding De-interleave & Dummy Data Insertion De-scrambler

64 Complexity in MIMO Detection Detection Algorithm Complexity (MIMO) Complexity (MIMO-OFDM) ML MLD O(2 QN ) K * O(2 QN ) OSIC V-BLAST(MMSE) O(N 4 ) K * O(N 4 ) Linear MMSE O(N 3 ) K * O(N 3 ) ZF O(N 2 ) K * O(N 2 ) N: No. of Antennas, Q: Quantization Level, K: No. of OFDM Subcarriers MIMO-OFDM Considerable Complexity Even for Linear Detection IEEE802.11n... K=128, WiMAX... K=1024 Conventional Hardware Architectures Insufficiency for Real-Time MIMO-OFDM Detection

65 MMSE Detection Received Signal (Freq. Domain) y k ( t) H s ( t) n ( t) k MMSE Detection G k ( H H k H k k Training Symbols k 2 1 k I) H H k MIMO Decoding sˆ ( t) G k Data Symbols k y k ( t) Guard Interval Channel Estimation Preprocessing Decoding L(3) L(4) s(1) s(2) s(3) Latency Requirement H 1 H k s 1 (t) s k (t) G 1 G k

66 Algorithm Consideration Matrix Inversion (Most Costly) QR Decomposition Sherman-Morrison Matrix Inversion Lemma Cholesky Decomposition Rely on Iterative Operations Analytic Solution (Strassen s Matrix Inversion) Suitable for Pipelined Architecture Hardware Simple Circuit Structure Using Systematic Operations Reduce Complexity by Making Use of Properties of Complex Conjugate Symmetric (in case of MMSE)

67 1/SNR 4x4 Matrix Multiplication Pipeline Delay Matrix Inputs 4x4 Matrix Inversion 4x4 Matrix Multiplication Matrix Outputs Circuit Structure of MMSE Detector Complete Pipelined Architecture Total 30 Pipeline Stages 22 stages k: Subcarrier Index P 11 (k) R 11 (k) P 12 (k) R 12 (k) H 11 (k) H 12 (k) P 44 (k) R 44 (k) G 11 (k) G 12 (k) S b (k) H 44 (k) S a (k) G 44 (k) Q 11 (k) 2 ( k) Q 12 (k) S c (k) Q 44 (k) Scaling Factor in Block Floating- Point 4 stages 22 stages 4 stages

68 Matrix Operations Use of 2x2 Submatrices Conjugate Symmetry in Non Diagonal Submatrices P k H H k H k 2 k I Hermitian Transpose Conjugate Symmetry P 11 P 21 P P P 22 P31 P32 P 41 P 42 Complexity Reduction P 14 P24 P23 P P33 34 P43 P44 A C Strassen s Matrix Multiplication and Inversion Use of Conjugate Symmetry Submatrices B D B A H B D

69 Matrix Inversion (1) Strassen s Matrix Inversion Block Operations by 2x2 Submatrices 1 A C A 1 B D A E 1 1 BE CA 1 1 CA 1 A 1 E E BE D CA Conjugate Symmetric B Mul Add/Sub Div/Rec Direct Cholesky Strassen Comparison of Real Operations

70 Matrix Inputs Block Floating Arithmetic Scaling Matrix Outputs s1, s2, s3, s4 Scale In Matrix Inversion (2) Pipeline Stages by 2x2 Matrix Operation Units A -1 9 D 13 D 1 D A C B D 7 [ ] -1 x x - [ ] -1 x,[] H x + 7 D D 10 D CA -1 s1 s2 s3 s4 E -1 A -1 BE -1 C H -E -1 CA -1 (=C ) D 2 D 2 D A B C D 1 Scale Out

71 Block Diagram of MIMO Decoder

72 BER Evaluation of Calculation Precision Simulation IEEE802.11n Standards (4x4 MIMO-OFDM) Multipath Rayleigh Fading (i.i.d. MIMO Spatial Correlation) 1x10 0 1x10-1 1x10-2 1x10-3 1x10-4 1x bits 18 bits 20 bits floating point 1x E b /N 0 [db]

73 Circuit Implementation RTL Design Verilog nm CMOS Implementation 1.0-V Voltage Supply 160-MHz Clock Frequency Wordlength (bits) Area (mm 2 ) Gate Count Power Dissipation (mw) ,559, ,862, ,203,

74 Performance Comparison Reference [2] [3] [4] Proposed Matrix 2 x 2 4 x 4 4 x 4 4 x 4 Detection Algorithm ZF ZF MMSE MMSE Hardware Configuration DSP TMS ASIC 90 nm 43 k gates ASIC 0.25 µm 89 k gates ASIC 90 nm 1.86 M gates Operating Freq. 225 MHz 500 MHz 167 MHz 160 MHz Latency Time 104 x K (µs) 180 x K (ns) 600 x K (ns) (ns) K: No. of OFDM Subcarriers [2] V. Jungnickel, A. Forck, T. Haustein, et al., 1 Gbit/s MIMO-OFDM transmission experiments,'' IEEE Vehicular Technology Conference (VTC), [3] Johan Eilert, Di Wu, and Dake Liu, Efficient complex matrix inversion for MIMO software defined radio, IEEE ISCAS, [4] A. Burg, S. Haene, D. Perels, P. Luethi, N. Felber, and W. Fichtner, Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems, IEEE ISCAS, 2006.

75 Maximum Transmission Speed (Mbps) Available Data Speed Necessary Conditions Clock Frequency Baseband Bandwidth Processing Latency GI Duration (400 ns) point FFT 256-point FFT 512-point FFT 5/6 Coding Rate 64-QAM 400-ns GI Duration Bandwidth (MHz) A 2.6-Gbps MIMO-OFDM receiver is available by the proposed MMSE detector.

76 4x4 MIMO-OFDM with 512 SUBCARRIERS

77 Performance Evaluation

78 Summary We have proposed the high-speed OFDM transceivers with the 80MHz-bandwidth. The proposed transceiver offers available hardware solution for real-time MIMO detection. The SISO-OFDM and MIMO-OFDM transceiver consumes a maximum of 260mW and 540mW in power dissipation in a 90-nm CMOS process. 78

79 Who? Yoshikazu Miyanaga He received the B.S., M.S., and Dr. Eng. degrees from Hokkaido University, Sapporo, Japan, in 1979, 1981, and 1986, respectively. He is currently a Professor at Graduate School of Information Science and Technology, Hokkaido University. His research interests are in the areas of signal processing for wireless communications, nonlinear signal processing and low-power LSI systems. He was a chair of Technical Group on Smart Info-Media System, IEICE. He is an advisory member of this technical group. Currently, he is IEICE fellow. He served as a member in the board of directors, IEEE Japan Council as a chair of student activity committee from 2002 to He is a chair of student activity committee in IEEE Sapporo Section from He is a chair of IEEE Circuits and Systems Society, Digital Signal Processing Technical Committee from He has been serving as international steering committee chairs/members of IEEE ISPACS, IEEE ISCIT, IEEE/EURASIP NSIP and honorary/general chairs/co-chairs of their international symposiums/workshops, i.e., ISPACS 2003, ISCIT 2004, ISCIT 2005, NSIP 2005, ISPACS 2008, ISMAC 2009 and APSIPA ASC He also served as international organizing committee chairs of IEICE ITC-CSCC , IEEE MSCAS 2004, IEEE ISCAS

80 References of this Topic in Shingo Yoshizawa, Kazuto Nishi, Yoshikazu Miyanaga, Reconfigurable Two-Dimensional Pipeline FFT Processor in OFDM Cognitive Radio Systems, Proceedings of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), pp , May Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga, A Complete Pipelined MMSE Detection Architecture in a 4 4 MIMO-OFDM Receive r, Proceedings of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), pp , May Yuki Ogasawara, Shinya Odagiri, Shindo Yoshizawa, Yoshikazu Miyanaga, Performance Evaluation of Environment-Adaptive Agent System in OFDM Cognitive Radio, Proceedings of 2008 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), December Risanuri Hidayat, Kobchai Dejhan, Phichet Moungnoul, Yoshikazu Miyanaga, OTA-Based High Frequency CMOS Multiplier and Squaring Circuit, Pr oceedings of 2008 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), December Takayuki Sugawara, Shingo Yoshizawa, Yoshikazu Miyanaga, Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Sy stems, IEEE International Symposium on Circuits and Systems (ISCAS), pp.2287-pp.2290,may Shingo Yoshizawa, Yoshikazu Miyanaga, Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation, IEEE Interna tional Symposium on Circuits and Systems (ISCAS), pp , May Shingo Yoshizawa, Yoshikazu Miyanaga, "Tunable Word-length Architecture for a Low Power Wireless OFDM Demodulator", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No.10, pp , October Shingo Yoshizawa, Yoshikazu Miyanaga, "Tunable Word-length Architecture for Low Power Wireless OFDM Demodulator", Proceedings of 2006 IEEE International Symposium on Circuits and Systems, Vol.1, pp , May Shingo Yoshizawa, Yoshikazu Miyanaga, Hiroshi Ochi, Yohsio Itho, Nobuo Hataoka, Baiko Sai, Norihisa Takayama, Masaki Hirata, "300-Mbps OFDM Baseband Transceiver for Wireless LAN Systems", Proceedings of 2006 IEEE International Symposium on Circuits and Systems, Vol.1, pp , May Yasushi Yamauchi, Shingo Yoshizawa, Yoshikazu Miyanaga, "A New Decision Feedback Compensation Technique of Carrier Frequency Offset and IQ Imbalance in Wireless OFDM Systems", Proceedings of IEEE International Symposium on Communications and Information Technologies 2006, Vol.1, W2F-1, pp.94-97, October Takayuki Sugawara, Yoshikazu Miyanaga, "Doppler Frequency Estimation Schemes for Multi-carrier Systems", Proceedings of IEEE International Symposium on Communications and Information Technologies 2006, Vol.1, T3F-1, pp , October Shingo Yoshizawa, Yoshikazu Miyanaga, "VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System", Proceedings of 2006 IEEE Asia Pacific Conference on Circuits and Systems, Vol.1, pp.93-96, December