R7521. PWM Controller for Half-Bridge Converters. Features. General Description. Simplified Application Circuit

Transcription

1 PWM Controller for Half-Bridge Converters General Description The is a with PWM controller with supervisor function inside. The controller can be applied on half-bridge converter or push-pull converter, which needs two interleaved gate drivers with 180 degree phase shift. Four multiple outputs can be monitored by and there is a "Power Good" signal to acknowledge the following system. The controller also has remote control pin and fully protection of each output, such as output over voltage, under voltage and over power protection. The pin is applied to detect AC line condition. incorporates over power protection. also contains FC pin to control Fan's speed by voltage variation. The integrated control circuit of provides complete functions and saves the Fan control external circuit of ATX power. Features Two PWM Driver Outputs for Push-Pull and Half- Bridge Converters Built-In Supervisor Saves Cost and Components Voltage Mode PWM Controller Output Over Voltage and Under Voltage Protections of Each Output Remote ON/OFF Power Good Indicator with Adaptive Time Sequence Input Under Voltage Detector and Warning Over Power Protection Adjustable Soft-Start For ATX Power Application Fun Speed Control Simplified Application Circuit 12V -12V 5V V12 V5 FC FAN1-12V FAN2-12V INV RT COMP SS GND PSON OPP 12V -12V 5VSB V33 TL431 PG Transfer to Primary Driver 5V -00 December

2 Ordering Information Package Type N: DIP-16 S: SOP-16 Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Pin Configurations RT FC V12 V33 V5 RT (TOP VIEW) SOP SS INV COMP PSON PG GND SS FC 2 15 INV Marking Information V COMP GS GSYMDNN GS : Product Number YMDNN : Date Code V33 V PSON PG GND 7 10 GN 8 9 RichPower GNYMDNN GN : Product Number YMDNN : Date Code DIP December 2012

3 Functional Pin Description Pin No. SOP-16 DIP-16 Pin Name Pin Function 1 1 RT Reference Current Setting. Connected to an external resistor to set the internal reference current. 2 2 FC Fan Control I/O. 3 3 V12 12V Output Sense Pin. 4 4 V33 3.3V Output Sense Pin. 5 5 V5 5V Output Sense Pin. 6 6 Over Power Sense Pin. 7 7 V AC Input Detector Input. 8 8 Bias of Controller. Source from 5V standby power. 9 9 PWM Driver Output PWM Driver Output GND Ground PG Power Good Signal Output (open collector type.) PSON Remote On/Off Control with 24ms De_bounce Time COMP Error Amplifier Output INV Negative Input of error amplifier SS Soft-Start. SS is as the non-inverting input of error amplifier. Function Block Diagram V33 V5 V12 PG RT FC UVS UVP PG Logic OFF 254ms Delay V BIAS Fan Control PSON 1.4V UVAC S/H OVP 1.9V - 6ms Delay Enable Logic 8µA 24ms 2ms - De_bounce Delay 2.5V - 3.2V - - POR D Q clk QN P C S R Q QN Driver Reset OSC D MAX GND SS INV COMP -00 December

4 Operation The is a PWM controller with supervisor functions. The PWM signal and drive primary-side switching power transistor by transformer, and the supervisor monitors each output. The provides fruitful protection functions that protect system from damage. Each output is protected by OVP, UVP, and OPP. The functions description as follow : Output Over-Voltage Protection The has an output Over-Voltage Protection (OVP) function, which monitors the 3.3V, 5V and 12V output voltages, to prevent power system and loads from damages during one or more output OV condition(s). The OVP starts monitoring the voltages on V33, V5 and V12 at the end of the PSONB de-bounce time. When an Over-Voltage (OV) condition appears at one of the monitored pins for more than the 0.6ms (typical) deglitch time, the PG voltage goes low to indicate one of the output voltages is out of regulation. Meanwhile the disables PWM output and protects the power supply system. The OVP condition is latched until PSON is toggled from low to high or restarts. Output Under-Voltage Protection The provides under voltage protection for the 3.3V, 5V and 12V outputs. The UVP continuously monitors the voltage on V33, V5 and V12. When an Under Voltage (UV) protection condition appears at either one of the monitored pins for more than 2ms (typical) deglitch time, the PG voltage goes low to indicate one of the output voltages is out of regulation. Meanwhile, the disables the PWM output and protects the power supply system. The UVP condition is latched until PSON is toggled from low to high or restarts. Output Over-Power Protection The has an output over-power protection (OPP) function, which monitors total output power. The pin of senses primary-side switching current by current transformer (CT). When over power or output short condition appears, the OPP exceeds the trigger voltage (1.9V) for 6ms (typical), the disables PWM output and protects the power supply system. In addition, the can monitor 12V output voltage, and the OPP condition is latched until PSON is toggled from low to high or restarts. PG Outputs In general, the PG voltage pulled high by an external resistor connected to the 5V output, indicates the status of the outputs. The PG keeps at low state when voltage < UVLO threshold, PSON = H, PGI voltage < 1.2V or one of the faults, including UVP, OVP and OPP, occurs. PSON De-bounce The provides a remote ON/OFF control input pin (PSON) for PC power supply applications. A built-in 24ms (typical) de-bounce circuit performs rising and falling edge noise de-bounce functions to identify valid PSON input signals. The PSON also has a TTL logic-compliant input voltage threshold and a hysteresis design against input noise. Soft-Start The SS offers an internal 8μA (typical) constant current. Connect a capacitor between the SS and GND pins to set the soft-start time. Therefore, the soft-start time is t SS = 8μ x C SS. During soft-start period, the UVP and OPP protection is disabled to prevent wrong UVP, OPP protection December 2012

5 Absolute Maximum Ratings (Note 1) Supply Input Voltage, V I DD mA Power Dissipation, P T A = 25 C SOP W DIP W Package Thermal Resistance (Note 2) SOP-16, θ JA C/W DIP-16, θ JA C/W Lead Temperature (Soldering, 10 sec.) C Junction Temperature C Storage Temperature Range C to 150 C ESD Susceptibility (Note 3) HBM (Human Body Model) kV MM (Machine Model) V Recommended Operating Conditions (Note 4) Supply Input Voltage, V to 6V Frequency kHz Junction Temperature Range C to 125 C Ambient Temperature Range C to 85 C Electrical Characteristics ( = 5V, RT = 62kΩ, TA = 25 C, unless otherwise specified) POR Section Parameter Symbol Test Conditions Min Typ Max Unit DC Supply Voltage V DD V On Threshold Voltage V TH_ON V Off Threshold Voltage V TH_OFF V Operating Supply Current I DD_OP V DD = 5V, V COMP = 2.5V ma Oscillator Section Normal PWM Frequency f OSC R T = 62kΩ khz Maximum Duty Cycle DCY MAX Both for and % Frequency Variation Versus Deviation Frequency Variation Versus Temperature Deviation f DV V DD = 5V % f DT T A = 20 C to 85 C % Ramp of Oscillator V P V Zero Duty Offset V OFFSET V RT Reference Voltage V REF_RT f OSC = 35kHz to 70kHz V -00 December

6 Parameter Symbol Test Conditions Min Typ Max Unit Protection Section OVP of 3.3V Output V OVP_V V OVP of 5V Output V OVP_V V OVP of 12V Output V OVP_V12 (Note 5) V UVP of 3.3V Output V UVP_V V UVP of 5V Output V UVP_V V UVP of 12V Output V UVP_V12 (Note 5) V UVS of 3.3V Output V UVS_V V UVS of 5V Output V UVS_V V UVS of 12V Output V UVS_V12 (Note 5) V Time Delay of OVP T OVP ms Time Delay of UVP T UVP ms Time Delay of UVS T UVS ms Over Power Protection V V Delay ms Cycle Limit V Power Good Section Power Good Time Delay T PG ms Voltage Sense for PG V V PG Output Saturation Level V OL I PG = 5mA V PG Leakage Current I LK V PG = 5V µa Error Amplifier Section Reference Voltage V REF V Open Loop Gain A VOL db Unit Gain Bandwidth BW MHz Power Supply Rejection Ratio PSRR db Remote On/Off Section PSON Threshold Voltage V TH V PSON Sourcing Current I PSON ma PSON De_bounce Time T DEB ON OFF ms Delay Time Between PSON = 1 and PG = 0 T PSOFF (m.o D-FF) ms Soft-Start Section SS Charging Current I SS µa December 2012

7 Fan Control Section Parameter Symbol Test Conditions Min Typ Max Unit Sourcing Current of FC I FC ma Voltage Range of FC V FC V PWM Output Section Rising Time T R V DD = 5V, C L = 1.8nF ns Falling Time T F V DD = 5V, C L = 1.8nF ns R DS_ON of Top and Bottom Leg R DS_ON V DD = 5V Ω Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 25 C on a high effective thermal conductivity four-layer test board per JEDEC Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. The V12 pin must to use divider resistor. Propose setting the ratio is 1/ December

8 Typical Application Circuit L > V AC N > 250V/7A 0.33µF/275V NTC 560k 1/4W 2.2µF LF1 EE-25 T2 EEL-16 (N=1:4) 4.7nF 275V 4.7nF 275V 10R 10R 820µF/220V 820k 1/4W 7N241 SWITCH µF/220V 820k 1/4W 7N241 10N40 10N40 30 HV 1Ts 225J/250V 50Ts 47/5W 102/1kV 103/50V 50Ts 7Ts 7Ts T1 ERL-35-14PIN T4 1K 2K 91K 3Ts 2K 15 1/4W 103/50V 104/ 50V SBL3045P 3Ts PR V -12V 100K V40100P PR /4W 104/50V 4.7 1/4W 104/50V 4.7 1/4W 14Ts 14Ts 6Ts MP1320 SBL3045P µF/16V 470µF/16V 470µF/16V 470µF/10V 470µF/10V µF/10V 2200µF/10V W 510 1/4W 27 3W 12V -12V 5V 10 2W 100 TL V 4.7k 222/50V 1.5k 1% HV 103/50V 750k 750k 1.6 DRAIN2 CS DRAIN1 102k/1kV 1N4007 GND1 GND2 COMP 100k RT 10µF/50V R R 103/50V 1N k T3 EEL-19 PC817C 5VSB_F 1000µF/10V 1k TL µF/10V 104/ 50V 4.7k 5VSB FAN1 12V - FAN2-2.51k 1% 2.49k 1% 12V 2.7k 62k 51k k 2N V 5V 101/50V 5VSB_F /50V 1k 50k RT FC V12 V33 V5 5C6 SS INV COMP PSON PG GND 333/50V 104/50V 103/50V 47k 3.6k 1K 5V 3.3V 5V 12V 10k 22.1k PSON PG 68k 47k 22.1k 153/50V December 2012

9 Typical Operating Characteristics FB & FBS vs. Temperature Frequency vs. Temperature FB 2.49 FBS 60 Voltage (V) Frequency (Hz) Temperature ( C) Temperature ( C) -00 December

10 Application Information Fan Control In order to effectively utilize the fan to disperse heat and reduce acoustic noise, the provides FC pin to control Fan's speed. Figure 1 shows the relationship between FC voltage and load in ATX 300W power supply application. Beside, the has fine over power protection. As Figure 3, total power limit is constant, and won't follow Vin variation. Set the ratio of OPP resistive divider to decide the total limit. Total Power Limit vs. V IN 160% 1.6 FC vs. Load 150% FC Voltage Total Power (%) 140% 130% 120% 110% % The Total Power Limit is constant The FC Initial Voltage is 0.543V 180Vac 230Vac 265Vac V IN 25% 50% 75% 100% Figure 3. Over Power Limit and V IN Relation Curve Load Figure 1. FC Voltage Variation Over Power Protection When ATX power is over power or in output short condition, the will shut down the controller. As shown in Figure 2, if the over power condition appears, voltage exceeds the trigger voltage (1.9V) and exists for 6ms (typical), the PWM output will be latched. VAC Detecting Protection is connected to secondary winding through a resistive divider for V AC input detecting. When V AC fails, the voltage of is lower than 0.5V, and PG signal will be pulled low to indicate V AC power-down. Set the ratio of resistive divider to decide the weight. The bypass capacitor is used to filter the switching noise. 12V R1 R2 C - 0.5V Figure 4. V AC Detecting Circuit Figure 2. Over Power Protection December 2012

11 Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : P D(MAX) = (T J(MAX) T A ) / θ JA where T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θ JA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125 C. The junction to ambient thermal resistance, θ JA, is layout dependent. For SOP-16 package, the thermal resistance, θ JA, is C/ W on a standard JEDEC 51-7 four-layer thermal test board. For DIP-16 package, the thermal resistance, θ JA, is 59.6 C/ W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at T A = 25 C can be calculated by the following formula : Maximum Power Dissipation (W) Four-Layer PCB 1.6 DIP SOP Ambient Temperature ( C) Figure 5. Derating Curve of Maximum Power Dissipation P D(MAX) = (125 C 25 C) / (108.6 C/W) = 0.92W for SOP-16 package P D(MAX) = (125 C 25 C) / (59.6 C/W) = 1.68W for DIP-16 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θ JA. The derating curve in Figure 5 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. -00 December

12 Outline Dimension A H M J B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A B C D F H I J M Lead SOP Plastic Package December 2012

13 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A A b b D E E e L Lead DIP Plastic Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863) Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. -00 December