RT9624B. Single Phase Synchronous Rectified Buck MOSFET Driver. Features. General Description. Applications. Simplified Application Circuit

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1 Single Phase Synchronous Rectified Buck MOSFET Driver General Description The is a high frequency, synchronous rectified, single phase MOSFET driver designed for normal MOSFET driving applications and high performance CPU VR driving capabilities. The can be supplied from 4.5V to 13.2V. The applicable power stage VIN range is from 5V to 24V. The IC also builds in an internal power switch to replace external bootstrap diode. The can support switching frequency efficiently up to 500kHz. The IC has both the and driving circuits for synchronous rectified DC/DC converter applications. The shoot through protection mechanism is designed to prevent shoot through between high side and low side power MOSFETs. The has tri-state input with shutdown function, which can force driver to output low and signals. Features Drive Two N-MOSFETs Shoot Through Protection Embedded Bootstrap Diode Support High Switching Frequency Fast Output Rising Time Tri-State Input for Output Shutdown Small SOP-8, SOP-8 (Exposed Pad) and 8-Lead WDFN Packages RoHS Compliant and Halogen Free Applications Core Voltage Supplies for Desktop, Motherboard CPU High Frequency Low Profile DC/DC Converters High Current Low Voltage DC/DC Converters Core Voltage Supplies for GFX Card The comes in a small footprint with 8-pin packages. The choice of package types includes SOP-8, SOP-8 (Exposed Pad) and WDFN-8L 3x3. Simplified Application Circuit 12V R1 VCC BOOT R2 C5 C6 V IN Controller C1 C BOOT R3 R4 Q1 Q2 L1 R5 C2 + C3 C4 V OUT 1

2 Ordering Information Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Marking Information ZS ZSYMDNN Package Type S : SOP-8 SP : SOP-8 (Exposed Pad-Option1) QW : WDFN-8L 3x3 (W-Type) Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free) ZS : Product Number YMDNN : Date Code Pin Configurations BOOT NC VCC BOOT NC VCC (TOP VIEW) SOP-8 SOP-8 (Exposed Pad) BOOT NC VCC WDFN-8L 3x3 ZSP ZSPYMDNN ZSP : Product Number YMDNN : Date Code ZQW 03 YM DNN 03 : Product Code YMDNN : Date Code 2

3 Function Pin Description SOP-8 Pin No. SOP-8 (Exposed Pad) / WDFN-8L 3x3 Pin Name Pin Function 1 1 BOOT Bootstrap Supply for High Side Gate Drive. 2 2 Signal Input. Connect this pin to the output of the controller. 3 3 NC No Internal Connection. 4 4 VCC Supply Voltage Input , 9 (Exposed Pad) Low Side Gate Driver Output. Connect this pin to the Gate of low side power N-MOSFET. Ground. The exposed pad must be soldered to a large PCB and connected to for maximum power dissipation. Connect this pin to the Source of the high side N-MOSFET and the Drain of the low side N-MOSFET. High Side Gate Drive Output. Connect this pin to the Gate of high side power N-MOSFET. Function Block Diagram VCC Internal VDD POR Bootstrap Control Shoot-Through Protection BOOT Tri-State Detect Turn Off Detection VCC Shoot-Through Protection 3

4 Operation POR (Power On Reset) POR block detects the voltage the VCC pin. When the VCC pin voltage is higher than POR rising threshold, POR block output is high. POR output is low when VCC is not higher than POR rising threshold. When the POR block output is high, and can be controlled by input voltage. If the POR block output is low, both and will be pulled to low. Tri-State Detect When both POR block output and EN pin voltages are high, and can be controlled by input. There are three input modes, which are high, low, and shutdown state. If input is within the shutdown window, both and output are low. When input is higher than its rising threshold, is high and is low. When input is lower than its falling threshold, is low and is high. Turn-Off Detection Turn-off detection block detects whether high side MOSFET is turned off by monitoring pin voltage. To avoid shoot through between high side and low side MOSFETs, low side MOSFET can be turned on only after high side MOSFET is effectively turned off. Shoot-Through Protection Shoot-through protection block implements the dead time when both high side and low side MOSFETs are turned off. With shoot-through protection block, high side and low side MOSFET are never turned on simultaneously. Thus, shoot through between high side and low side MOSFETs is prevented. Bootstrap Control Bootstrap control block controls the integrated bootstrap switch. When is high (low side MOSFET is turned on), the bootstrap switch is turned on to charge the bootstrap capacitor connected to BOOT pin. When is low (low side MOSFET is turned off), the bootstrap switch is turned off to disconnect VCC pin and BOOT pin. 4

5 Absolute Maximum Ratings (Note 1) Supply Voltage, VCC V to 15V BOOT to V to 15V to DC V to 30V < 20ns V to 35V to DC V to (VCC + 0.3V) < 20ns V to (VCC + 0.3V) to DC (V 0.3V) to (V BOOT + 0.3V) < 20ns (V 2V) to (V BOOT + 0.3V) to V to 7V Power Dissipation, P T A = 25 C SOP W SOP-8 (Exposed Pad) W WDFN-8L 3x W Package Thermal Resistance (Note 2) SOP-8, θ JA C/W SOP-8 (Exposed Pad), θ JA C/W SOP-8 (Exposed Pad), θ JC C/W WDFN-8L 3x3, θ JA C/W WDFN-8L 3x3, θ JC C/W Lead Temperature (Soldering, 10 sec.) C Junction Temperature C Storage Temperature Range C to 150 C ESD Susceptibility (Note 3) HBM (Human Body Model) kV Recommended Operating Conditions (Note 4) Supply Voltage, VCC V to 13.2V Input Voltage, (V IN + VCC) < 35V Junction Temperature Range C to 125 C Ambient Temperature Range C to 85 C 5

6 Electrical Characteristics (V CC Power Supply Parameter Symbol Test Conditions Min Typ Max Unit Power Supply Voltage V CC V Power Supply Current I VCC V BOOT = 12V, Input Floating μa Power On Reset (POR) POR Rising Threshold V POR_r V CC Rising V POR Falling Threshold V POR_ f V CC Falling V Input Maximum Input Current I = 0V or 5V μa Floating Voltage V _fl = Open V Rising Threshold V _rth V Falling Threshold V _fth V Timing Rising Time t r 3nF Load ns Falling Time t f 3nF Load ns Rising Time t r 3nF Load ns Falling Time t f 3nF Load ns t pdh V Propagation Delay BOOT V = 12V tpdl See Timing Diagram t pdh See Timing Diagram Propagation Delay tpdl See Timing Diagram Output = 12V, TA = 25 C unless otherwise specified) Drive Source R sr V BOOT V = 12V, I Source = 100mA Ω Drive Sink R sk V BOOT V = 12V, I Sink = 100mA Ω Drive Source R sr I Source = 100mA Ω Drive Sink R sk I Sink = 100mA Ω Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θja is measured at TA = 25 C on a high effective thermal conductivity four-layer test board per JEDEC θjc is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. ns ns 6

7 Typical Application Circuit 12V R1 2.2 Controller C1 1µF VCC BOOT R2 1 C BOOT 1µF R3 2.2 R4 0 Q1 Q2 C5 1000µF x 3 L1 1µH R5 2.2 C2 3.3nF C6 10µF x 4 + C3 2200µF x 2 C4 10µF x 2 V IN 12V V OUT Timing Diagram t pdl 90% 1.5V t pdl 1.5V 90% 1.5V 1.5V t pdh t pdh 7

8 Typical Operating Characteristics Rising Edge Falling Edge (10V/Div) (10V/Div) (20V/Div) (20V/Div) (10V/Div) (10V/Div) (10V/Div) (10V/Div) Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time (5V/Div) (5V/Div) Full Load Full Load Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time (5V/Div) (5V/Div) No Load No Load Time (20ns/Div) Time (20ns/Div) 8

9 Short Pulse (5V/Div) Time (20ns/Div) No Load 9

10 Application Information The is a high frequency, synchronous rectified, single phase dual MOSFET driver containing Richtek's advanced MOSFET driver technologies. The is designed to be able to adapt from normal MOSFET driving applications to high performance CPU VR driving capabilities. Supply Voltage and Power On Reset The can be utilized under both V CC = 5V or V CC = 12V applications which may happen in different fields of electronics application circuits. In terms of efficiency, higher V CC equals higher driving voltage of / which may result in higher switching loss and lower conduction loss of power MOSFETs. The choice of V CC = 12V or V CC = 5V can be a tradeoff to optimize system efficiency. The is designed to drive both high side and low side N-MOSFET through external input control signal. It has power on protection function which held and low before the VCC voltage rises to higher than rising threshold voltage. Tri-state Input After the initialization, the signal takes the control. The rising signal first forces the signal to turn low then signal is allowed to go high just after a non-overlapping time to avoid shoot through current. The falling of signal first forces to go low. When and signal reach a predetermined low level, signal is allowed to turn high. The signal is acted as High if the signal is above the rising threshold and acted as Low if the signal is below the falling threshold. When signal level enters and remains within the shutdown window, the output drivers are disabled and both MOSFET gates are pulled and held low. If the signal is left floating, the pin will be kept around 1.8V by the internal divider and provide the controller with a recognizable level. Internal Bootstrap Power Switch The builds in an internal bootstrap power switch to replace external bootstrap diode, and this can facilitate PCB design and reduce total BOM cost of the system. Hence, no external bootstrap diode is required in real applications. Non-overlap Control To prevent the overlap of the gate drivers during the pull low and the pull high, the non-overlap circuit monitors the voltages at the node and high side gate drive (-). When the input signal goes low, begins to pull low (after propagation delay). Before is pulled high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1V. Once the monitored voltages fall below 1.1V, begins to turn high. By waiting for the voltages of the pin and high side gate driver to fall below 1.1V, the non-overlap protection circuit ensures that is low before pulls high. Also to prevent the overlap of the gate drivers during pull low and pull high, the non-overlap circuit monitors the voltage. When goes below 1.1V, goes high after propagation delay. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When V gs1 or V gs2 is at 12V or 5V, the gate draws the current only for few nano-amperes. Thus once the gate has been driven up to ON level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It is also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. 10

11 V IN d1 Cgd1 V g2 Igd1 Ig1 g1 Igs1 g2 V g1 V +12V s1 12V Cgs1 Ig2 Igd2 Igs2 V Cgd2 Cgs2 Figure 1. Equivalent Circuit and Waveforms (V CC = 12V) In Figure 1, the current I g1 and I g2 are required to move the gate up to 12V. The operation consists of charging C gd1, C gd2, C gs1 and C gs2. C gs1 and C gs2 are the capacitors from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the C gs1 and C gs2 are referred as C iss which are the input capacitors. C gd1 and C gd2 are the capacitors from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as C rss the reverse transfer capacitance. For example, t r1 and t r2 are the rising time of the high side and the low side power MOSFETs respectively, the required current I gs1 and I gs2, are shown as below : dvg1 Cgs1 x 12 Igs1 = Cgs1 = (1) dt tr1 dvg2 Cgs1 x 12 Igs2 = Cgs1 = (2) dt tr2 Before driving the gate of the high side MOSFET up to 12V, the low side MOSFET has to be off; and the high side MOSFET will be turned off before the low side is turned on. From Figure 1, the body diode D 2 will be turned on before high side MOSFETs turn on. d2 s2 L D2 t t V OUT dv 12 I gd1 = C gd1 = C gd1 (3) dt t r1 Before the low side MOSFET is turned on, the C gd2 have been charged to V IN. Thus, as C gd2 reverses its polarity and g 2 is charged up to 12V, the required current is dv VIN + 12 Igd2 = Cgd2 = C gd2 (4) dt t It is helpful to calculate these currents in a typical case. Assume a synchronous rectified Buck converter, input voltage V IN = 12V, V gs1 = 12V, V gs2 = 12V. The high side MOSFET is PHB83N03LT whose C iss = 1660pF, C rss = 380pF, and t r = 14ns. The low side MOSFET is PHB95N03LT whose C iss = 2200pF, C rss = 500pF and t r = 30ns, from the equation (1) and (2) we can obtain I I gs1 gs2 from equation. (3) and (4) the total current required from the gate driving source can be calculated as the following equations. ( ) I = I + I = = (A) (9) g1 gs1 gd1 ( ) I = I + I = = 1.28 (A) (10) g2 gs2 gd x 10 x 12 = = (A) x x 10 x 12 = = 0.88 (A) x x 10 x 12 Igd1 = = (A) x 10 ( ) x 10 x Igd2 = = 0.4 (A) x 10 r2 (5) (6) (7) (8) By a similar calculation, we can also get the sink current required from the turned off MOSFET. Select the Bootstrap Capacitor Figure 2 shows part of the bootstrap circuit of the. The V CB (the voltage difference between BOOT and on ) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance C BOOT has to be selected properly. It is determined by the following constraints. 11

12 Figure 2. Part of Bootstrap Circuit of In practice, a low value capacitor C BOOT will lead to the over charging that could damage the IC. Therefore, to minimize the risk of overcharging and to reduce the ripple on V CB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low-esr capacitor should be used to provide good local de-coupling. It is recommended to adopt a ceramic or tantalum capacitor. Power Dissipation To prevent driving the IC beyond the maximum recommended operating junction temperature of 125 C, it is necessary to calculate the power dissipation appropriately. This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 3 shows the power dissipation test circuit. C L and C U are the and load capacitors, respectively. The bootstrap capacitor value is 1μF. 12V 10 1µF 12 V CC VCC PWN BOOT V IN BOOT C BOOT 1µF C BOOT V CB - Figure 3. Power Dissipation Test Circuit + C L 3nF C U 3nF 2N V 2N Figure 4 shows the power dissipation of the as a function of frequency and load capacitance when V CC = 12V. The value of C U and C L are the same and the frequency is varied from 100kHz to 1MHz. Power Dissipation vs. Frequency Power Dissipation (mw) C U = C L = 2nF 100 VCC = 12V Figure 4. Power Dissipation vs. Frequency The operating junction temperature can be calculated from the power dissipation curves (Figure 4). Assume V CC = 12V, operating frequency is 200kHz and C U = C L = 1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 4, the power dissipation is 100mW. Thus, for example, with the SOP- 8 package, the package thermal resistance θ JA is 120 C/ W. The operating junction temperature is then calculated as : T J = (120 C/W x 100mW) + 25 C = 37 C (11) where the ambient temperature is 25 C. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : P D(MAX) = (T J(MAX) T A ) / θ JA Frequency (khz) CU = CL = 3nF C U = C L = 1nF where T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θ JA is the junction to ambient thermal resistance.

13 For recommended operating condition specifications, the maximum junction temperature is 125 C. The junction to ambient thermal resistance, θ JA, is layout dependent. For SOP-8 package, the thermal resistance, θ JA, is 120 C/W on a standard JEDEC 51-7 four-layer thermal test board. For SOP-8 (Exposed Pad) package, the thermal resistance, θ JA, is 75 C/W on a standard JEDEC 51-7 four-layer thermal test board. For WDFN-8L 3x3 package, the thermal resistance, θ JA, is 70 C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at T A = 25 C can be calculated by the following formulas : P D(MAX) = (125 C 25 C) / (120 C/W) = 0.833W for SOP-8 package P D(MAX) = (125 C 25 C) / (75 C/W) = 1.333W for SOP-8 (Exposed Pad) package P D(MAX) = (125 C 25 C) / (70 C/W) = 1.429W for WDFN-8L 3x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θ JA. The derating curve in Figure 5 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W) 1.6 Four-Layer PCB WDFN-8L 3x SOP-8 (Exposed Pad) SOP Layout Consideration Figure 6 shows the schematic circuit of a synchronous buck converter to implement the. The converter operates from 5V to 12V of input Voltage. For the PCB layout, it should be very careful. The power circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The location of Q1, Q2, L1 should be very close. Next, the trace from, and should also be short to decrease the noise of the driver output signals. signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C1 should be connected to directly. Furthermore, the bootstrap capacitors (C BOOT ) should always be placed as close to the pins of the IC as possible. V IN 12V L2 V CORE + C3 + C5 C6 CBOOT Q1 L1 PHB83N03LT Q2 PHB95N03LT 12V R1 BOOT VCC C1 Figure 6. Synchronous Buck Converter Circuit Ambient Temperature ( C) Figure 5. Derating Curve of Maximum Power Dissipation 13

14 Outline Dimension A H M J B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A B C D F H I J M Lead SOP Plastic Package 14

15 A H M EXPOSED THERMAL PAD (Bottom of Package) J Y X B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A B C D F H I J M Option 1 Option 2 X Y X Y Lead SOP (Exposed Pad) Plastic Package 15

16 D D2 L E E2 1 SEE DETAIL A e b A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A A b D D E E e L W-Type 8L DFN 3x3 Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863) Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. 16