VNH2SP30-E AUTOMOTIVE FULLY INTEGRATED H-BRIDGE MOTOR DRIVER

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1 AUTOMOTIVE FULLY INTEGRATED H-BRIDGE MOTOR DRIVER Table. General Features Figure. Package Type R DS(on) I out V ccmax VNHSP30-E 9 mω max (per leg) 30 A 4 V OUTPUT CURRENT: 30A V LOGIC LEVEL COMPATIBLE INPUTS UNDERVOLTAGE AND OVERVOLTAGE SHUT-DOWN OVERVOLTAGE CLAMP THERMAL SHUT DOWN CROSS-CONDUCTION PROTECTION LINEAR CURRENT LIMITER VERY LOW STAND-BY POWER CONSUMPTION PWM OPERATION UP TO 0 KHz PROTECTION AGAINST: LOSS OF GROUND AND LOSS OF V CC CURRENT SENSE OUTPUT PROPORTIONAL TO MOTOR CURRENT IN COMPLIANCE WITH THE 00/9/EC EUROPEAN DIRECTIVE DESCRIPTION The VNHSP30-E is a full bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic High-Side drivers and two Low-Side switches. The High-Side driver switch is designed using STMicroelectronic s well known and proven proprietary VIPower M0 technology that allows to efficiently integrate on the same die a true Power MOSFET with an intelligent signal/ protection circuitry. MultiPowerSO-30 The Low-Side switches are vertical MOSFETs manufactured using STMicroelectronic s proprietary EHD ( STripFET ) process.the three dice are assembled in MultiPowerSO-30 package on electrically isolated leadframes. This package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. The input signals IN A and IN B can directly interface to the microcontroller to select the motor direction and the brake condition. The DIAG A /EN A or DIAG B / EN B, when connected to an external pull-up resistor, enable one leg of the bridge. They also provide a feedback digital diagnostic signal. The normal condition operation is explained in the truth table on page 4. The CS pin allows to monitor the motor current by delivering a current proportional to its value. The PWM, up to 0KHz, lets us to control the speed of the motor in all possible conditions. In all cases, a low level state on the PWM pin will turn off both the LS A and LS B switches. When PWM rises to a high level, LS A or LS B turn on again depending on the input pin state. Table. Order Codes Package Tube Tape and Reel MultiPowerSO-30 VNHSP30-E VNHSP30TR-E September 004 Rev. /6

2 Figure. Block Diagram V CC OVERTEMPERATURE A O V + U V OVERTEMPERATURE B CLAMP HS A CLAMP HS B HS A DRIVER HSA LOGIC DRIVER HSB HS B CURRENT LIMITATION A CURRENT LIMITATION B OUT A /K /K CLAMP LS A CLAMP LS B LS A DRIVER LSA DRIVER LSB LS B GNDA DIAG A/EN A IN A CS PWM IN B DIAG B/EN B GND B Figure 3. Configuration Diagram (Top View) OUT A Nc V CC Nc IN A EN A /DIAG A Nc PWM CS EN B /DIAG B IN B Nc V CC Nc V CC Heat Slug OUT A Heat Slug3 Heat Slug 6 30 OUT A Nc GND A GND A GND A OUT A Nc V CC Nc GND B GND B GND B Nc /6

3 Table 3. Pin Definitions And Functions Pin No Symbol Function,, 30 OUT A, Heat Slug Source of High-Side Switch A / Drain of Low-Side Switch A,4,7,,4,7,, 4,9 NC Not connected 3, 3, 3 VCC, Heat Slug Drain of High-Side Switches and Power Supply Voltage 6 EN A /DIAG A Status of High-Side and Low-Side Switches A; Open Drain Output IN A Clockwise Input 8 PWM PWM Input 9 CS Output of Current sense IN B Counter Clockwise Input 0 EN B /DIAG B Status of High-Side and Low-Side Switches B; Open Drain Output, 6,, Heat Slug3 Source of High-Side Switch B / Drain of Low-Side Switch B 6, 7, 8 GND A Source of Low-Side Switch A (*) 8, 9, 0 GND B Source of Low-Side Switch B (*) Note: (*) GND A and GND B must be externally connected together Table 4. Pin Functions Description Name V CC GND A GND B OUT A IN A IN B PWM EN A /DIAG A EN B /DIAG B CS Battery connection. Description Power grounds, must always be externally connected together. Power connections to the motor. Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of the bridge in normal operation according to the truth table (brake to V CC, Brake to GND, clockwise and counterclockwise). Voltage controlled input pin with hysteresis, CMOS compatible.gates of Low-Side FETS get modulated by the PWM signal during their ON phase allowing speed control of the motor Open drain bidirectional logic pins.these pins must be connected to an external pull up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a High-Side FET or excessive ON state voltage drop across a Low-Side FET), these pins are pulled low by the device (see truth table in fault condition). Analog current sense output. This output sources a current proportional to the motor current. The information can be read back as an analog voltage across an external resistor. 3/6

4 Table. Block Descriptions (see Block Diagram) LOGIC CONTROL Name OVERVOLTAGE + UNDERVOLTAGE HIGH SIDE AND LOW SIDE CLAMP VOLTAGE HIGH SIDE AND LOW SIDE DRIVER LINEAR CURRENT LIMITER OVERTEMPERATURE PROTECTION FAULT DETECTION Description Allows the turn-on and the turn-off of the High Side and the Low Side switches according to the truth table. Shut-down the device outside the range [.V..6V] for the battery voltage. Protect the High Side and the Low Side switches from the high voltage on the battery line in all configuration for the motor. Drive the gate of the concerned switch to allow a proper R DS(on) for the leg of the bridge. Limits the motor current, by reducing the High Side Switch gate-source voltage when short-circuit to ground occurs. In case of short-circuit with the increase of the junction s temperature, shuts-down the concerned High Side to prevent its degradation and to protect the die. Signalize an abnormal behavior of the switches in the half-bridge A or B by pulling low the concerned ENx/DIAGx pin. Table 6. Absolute Maximum Rating Symbol Parameter Value Unit V CC Supply Voltage + 4 V I max Maximum Output Current (continuous) 30 A I R Reverse Output Current (continuous) -30 A I IN Input Current (IN A and IN B pins) +/- 0 ma I EN Enable Input Current (DIAG A /EN A and DIAG B /EN B pins) +/- 0 ma I pw PWM Input Current +/- 0 ma V CS Current Sense Maximum Voltage -3/+ V Electrostatic Discharge (R=.kΩ, C=00pF) V ESD - CS pin kv - logic pins 4 kv - output pins: OUT A,, V CC kv T j Junction Operating Temperature Internally Limited C T c Case Operating Temperature -40 to 0 C T STG Storage Temperature - to 0 C Figure 4. Current and Voltage Conventions I S V INA I INA I INB I ENA I ENB IN A IN B DIAG A /EN A DIAG B/EN B PWM V CC GND A OUT A CS GND B I OUTA I OUTB ISENSE V SENSE V OUTB V OUTA V CC V INB V ENA V ENB I pw V pw GND I GND 4/6

5 Table 7. Thermal Data See MultiPowerSO-30 Thermal Data section (page ) ELECTRICAL CHARACTERISTICS (V CC =9V up to 6V; -40 C<T j <0 C; unless otherwise specified) Table 8. Power Symbol Parameter Test Conditions Min. Typ. Max. Unit V CC Operating supply voltage. 6 V I S R ONHS R ONLS V f I L(off) I RM Supply Current Static High-Side resistance Static Low-Side resistance High Side Free-wheeling Diode Forward Voltage High Side Off State Output Current (per channel) Dynamic Cross-conduction Current Off state: IN A =IN B =PWM=0; T j = C; V CC =3V IN A =IN B =PWM= µa µa On state: IN A or IN B =V, no PWM 0 ma I OUT =A; T j = C I OUT =A; T j = - 40 to 0 C I OUT =A; T j = C I OUT =A; T j = - 40 to 0 C I f =A 0.8. V T j = C; V OUTX =EN X =0V; V CC =3V T j = C; V OUTX =EN X =0V; V CC =3V I OUT =A (see fig. 8) 0.7 A mω mω mω mω µa µa Table 9. Logic Inputs (IN A, IN B, EN A, EN B ) Symbol Parameter Test Conditions Min. Typ. Max. Unit V IL V IH V IHYST Input Low Level Voltage Input High Level Voltage Input Hysteresis Voltage Normal operation (DIAG X /EN X pin acts as an input pin) Normal operation (DIAG X /EN X pin acts as an input pin) Normal operation (DIAG X /EN X pin acts as an input pin). V 3. V 0. V I IN =ma V V ICL Input Clamp Voltage I IN =-ma V I INL Input Current V IN =. V µa I INH Input Current V IN =3. V 0 µa V DIAG Enable Output Low Level Voltage Fault operation (DIAG X /EN X pin acts as an output pin); I EN =ma 0.4 V /6

6 ELECTRICAL CHARACTERISTICS (continued) Table 0. PWM Symbol Parameter Test Conditions Min Typ Max Unit V pwl PWM Low Level Voltage. V I pwl PWM Pin Current V pw =.V µa V pwh PWM High Level Voltage 3. V I pwh PWM Pin Current V pw =3.V 0 µa V pwhhyst PWM Hysteresis Voltage 0. V V pwcl PWM Clamp Voltage I pw = ma V CC +0.3 V CC +0.7 V CC +.0 V I pw = - ma V C INPWM PWM Pin Input Capacitance V IN =.V pf Table. Switching (V CC =3V, R LOAD =0.87Ω) Symbol Parameter Test Conditions Min Typ Max Unit f PWM Frequency 0 0 khz t d(on) Turn-on Delay Time Input rise time < µs (see fig. 8) 0 µs t d(off) Turn-off Delay Time Input rise time < µs (see fig. 8) 0 µs t r Rise Time (see fig. 7).6 µs t f Fall Time (see fig. 7)..4 µs t DEL Delay Time During Change of Operating Mode (see fig. 6) µs t rr High Side Free Wheeling Diode Reverse Recovery Time (see fig. 9) 0 ns t off(min) PWM Minimum off time 9V<V CC <6V; -40 C<T j <0 C; I OUT =A 6 µs Table. Protection And Diagnostic Symbol Parameter Test Conditions Min Typ Max Unit V USD Undervoltage Shut-down. V Undervoltage Reset 4.7 V V OV Overvoltage Shut-down 6 9 V I LIM High-Side Current Limitation A V CLP Total Clamp Voltage (V CC to GND) I OUT =A V T TSD Thermal Shut-down Temperature V IN = 3. V C T TR Thermal Reset Temperature 3 C T HYST Thermal Hysteresis 7 C 6/6

7 ELECTRICAL CHARACTERISTICS (continued) Table 3. Current Sense (9V<V CC <6V) Symbol Parameter Test Conditions Min Typ Max Unit I OUT =30A ; R SENSE =.kω K I OUT /I SENSE T j = - 40 to 0 C I OUT =8A ; R SENSE =.kω K I OUT /I SENSE T j = - 40 to 0 C dk / K (*) Analog sense current drift I OUT =30A ; R SENSE =.kω T j = - 40 to 0 C % dk / K (*) Analog sense current drift I OUT >8A ; R SENSE =.kω T j = - 40 to 0 C % I SENSEO Analog Sense Leakage I OUT =0A; V SENSE =0V; Current T j = - 40 to 0 C 0 6 µa Note:(*) Analog sense current drift is deviation of factor K for a given device over (-40 C to 0 C and 9V<V CC <6V) with respect to it s value measured at T j= C, V CC=3V. WAVEFORMS AND TRUTH TABLE Table 4. Truth Table In Normal Operating Conditions In normal operating conditions the DIAG X /EN X pin is PWM pin usage: in all cases, a 0 on the PWM pin will considered as an input pin by the device. This pin must be turn-off both LS A and LS B switches. When PWM rises externally pulled high. back to, LS A or LS B turn on again depending on the input pin state. IN A IN B DIAG A /EN A DIAG B /EN B OUT A CS Operating mode H H High Imp. Brake to V CC 0 H L I SENSE =I OUT /K Clockwise (CW) 0 L H I SENSE =I OUT /K Counterclockwise (CCW) 0 0 L L High Imp. Brake to GND 7/6

8 Figure. Typical Application Circuit For Dc To 0khz PWM OperationShort Circuit Protection VCC Reg V + V +V 3.3K VCC 3.3K K DIAG B/EN B DIAGA/ENA K HSA HSB K µc PWM OUTA OUTB K 0K INA CS LSA M LSB IN B > 0uF K 33nF.K GND A GND B 00K G S b) N MOSFET In case of a fault condition the DIAG X /EN X pin is considered as an output pin by the device. The fault conditions are: - overtemperature on one or both high sides (for example if a short to ground occurs as it could be the case described in line and in the table below); - short to battery condition on the output (saturation detection on the Low-Side Power MOSFET). Possible origins of fault conditions may be: OUT A is shorted to ground ---> overtemperature detection on high side A. OUT A is shorted to V CC ---> Low-Side Power MOSFET saturation detection. When a fault condition is detected, the user can know D which power element is in fault by monitoring the IN A, IN B, DIAG A /EN A and DIAG B /EN B pins. In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn-on the respective output (OUT X ) again, the input signal must rise from low to high level. Table. Truth Table In Fault Conditions (Detected On OUT A ) IN A IN B DIAG A /EN A DIAG B /EN B OUT A CS 0 OPEN H High Imp. 0 0 OPEN L High Imp. 0 0 OPEN H I OUTB /K OPEN L High Imp. X X 0 0 OPEN OPEN High Imp. X 0 OPEN H I OUTB /K X 0 0 OPEN L High Imp. Fault Information Protection Action 8/6

9 Table 6. Electrical Transient Requirements ISO T/R Test Level Test Level Test Level Test Level Test Levels 7637/ I II III IV Delays and Impedance Test Pulse -V -0V -7V -00V ms, 0Ω +V +0V +7V +00V 0.ms, 0Ω 3a -V -0V -00V -0V 0.µs, 0Ω 3b +V +0V +7V +00V 0.µs, 0Ω 4-4V -V -6V -7V 00ms, 0.0Ω +6.V +46.V +66.V +86.V 400ms, Ω ISO T/R Test Levels Result Test Levels Result Test Levels Result Test Levels Result 7637/ I II III IV Test Pulse C C C C C C C C 3a C C C C 3b C C C C 4 C C C C C E E E Class C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Reverse Battery Protection Three possible solutions can be thought of: a) a Schottky diode D connected to V CC pin b) a N-channel MOSFET connected to the GND pin (see Typical Application Circuit on page 8) c) a P-channel MOSFET connected to the V CC pin The device sustains no more than -30A in reverse battery conditions because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of VNHSP30-E will be pulled down to the V CC line (approximately -.V). Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If I Rmax is the maximum target reverse current through µc I/Os, series resistor is: V V IOs CC R = I Rmax 9/6

10 Figure 6. Definition Of The Delay Times Measurement V INA, t V INB PWM t t I LOAD t DEL t DEL t Figure 7. Definition Of The Low Side Switching Times PWM t V OUTA, B 90% 80% t f 0% 0% t r t 0/6

11 Figure 8. Definition Of The High Side Switching Times V INA, t D(on) t D(off) t V OUTA 90% 0% t Figure 9. Definition Of Dynamic Cross Conduction Current During A Pwm Operation IN A =, IN B =0 PWM I MOTOR t t V OUTB I CC t I RM t t rr /6

12 Figure 0. Waveforms in full bridge operation DIAG A /EN A DIAG B /EN B IN A IN B PWM NORMAL OPERATION (DIAG A /EN A =, DIAG B /EN B =) LOAD CONNECTED BETWEEN OUT A, OUT A I OUTA -> OUTB CS (*) tdel tdel (*) CS BEHAVIOUR DURING PWM MODE WILL DEPEND ON PWM FREQUENCY AND DUTY CYCLE NORMAL OPERATION (DIAG A /EN A =, DIAG B /EN B =0 and DIAG A /EN A =0, DIAG B /EN B =) LOAD CONNECTED BETWEEN OUT A, DIAG A /EN A DIAG B /EN B IN A IN B PWM OUT A I OUTA -> OUTB CS CURRENT LIMITATION/THERMAL SHUTDOWN or OUT A SHORTED TO GROUND IN A IN B I LIM I OUTA -> OUTB T TSD T TR T j T j > T TR DIAG A /EN A DIAG B /EN B CS normal operation OUT A shorted to ground normal operation /6

13 Figure. Waveforms In Full Bridge Operation (continued) OUT A shorted to V CC and undervoltage shutdown IN A IN B OUT A undefined undefined I OUTA-> OUTB DIAG B /EN B DIAG A/EN A CS V<nominal normal operation OUT A shorted to V CC normal operation undervoltage shutdown 3/6

14 Figure. Half-bridge Configuration The VNHSP30-E can be used as a high power half-bridge driver achieving an On resistance per leg of 9.mΩ. Suggested configuration is the following: V CC IN A IN B DIAG A /EN A DIAG B /EN B PWM IN A IN B DIAG A /EN A DIAG B /EN B PWM OUT A M OUTA GND A GND B GND A GND B Figure 3. Multi-motors Configuration The VNHSP30-E can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. DIAG X /EN X pins allow to put unused half-bridges in high impedance. Suggested configuration is the following: V CC IN A IN B DIAG A/EN A DIAG B/EN B PWM IN A IN B DIAG A /EN A DIAG B /EN B PWM OUT A M OUTA GND A GND B GND A GND B M M 3 4/6

15 Figure 4. On State Supply Current Is (ma) 6 Figure 7. Off State Supply Current Is (µa) Vcc=3V INA or INB=V Vcc=3V Figure. High Level Input Current Iinh (µa) 4. Vin=3.V Figure 8. Input Clamp Voltage Vicl (V) Iin =ma Figure 6. Input High Level Voltage Vih (V) Figure 9. Input Low Level Voltage Vil (V) /6

16 Figure 0. Input Hysteresis Voltage Vihyst (V) Figure 3. High Level Enable Pin Current Ienh (µa) 8.7. Vcc=3V 7 6 Ven=3.V Figure. Delay Time during change of operation mode Figure 4. Enable Clamp Voltage tdel (µs) Vencl (V) Ien=-mA 0 - Figure. High Level Enable Voltage Venh (V) 3.6 Figure. Low Level Enable Voltage Venl (V) Vcc=9V.8.6 Vcc=9V /6

17 Figure 6. PWM High Level Voltage Vpwh (V) Figure 9. PWM Low Level Voltage Vpwl (V) Vcc=9V.4. Vcc=9V Figure 7. PWM High Level Current Ipwh (µa) 8 Figure 30. Overvoltage Shutdown Vov (V) Vcc=9V Vpw=3.V Figure 8. Undervoltage Shutdown Vusd(V) Figure 3. Current Limitation Ilim (A) /6

18 Figure 3. On State High Side Resistance Vs. T case Ronhs (mohm) 40 Figure 3. On State Low Side Resistance Vs. T case Ronls (mohm) Vcc=9V; 6V Iout=A 3 30 Iload=A Vcc=9V; 3V; 8V Tc (ºC) Figure 33. Turn-on Delay Time td(on) (µs) Figure 36. Turn-off Delay Time td(off) (µs) Figure 34. Output Voltage Rise Time tr (µs) Figure 37. Output Voltage Fall Time tf (µs) /6

8mm x 8mm, PCB thickness=mm, Cu thickness=3µm, Copper areas: from minimum pad lay-out to

Chipset Configuration HIGH SIDE CHIP HS AB LOW SIDE CHIP A LS A LOW SIDE CHIP B LS B

19 MultiPowerSO-30 Thermal Data Figure 38. MultiPowerSO-30 PC Board Layout condition of R th and Z th measurements (PCB FR4 area= 8mm x 8mm, PCB thickness=mm, Cu thickness=3µm, Copper areas: from minimum pad lay-out to 6cm ). Figure 39. Chipset Configuration HIGH SIDE CHIP HS AB LOW SIDE CHIP A LS A LOW SIDE CHIP B LS B Figure 40. Auto and mutual R thj-amb Vs PCB copper area in open box free air condition (according to page 0 definitions) C/W RthHS RthLS RthHSLS RthLSLS cm of Cu Area (refer to PCB layout) 9/6

20 Table 7. Thermal Calculation In Clockwise And Anti-clockwise Operation In Steady-state Mode HS A HS B LS A LS B T jhsab T jlsa T jlsb ON OFF OFF ON P dhsa x R thhs + P dlsb x P dhsa x R thhsls + P dlsb x R thhsls + T amb R thlsls + T amb OFF ON ON OFF P dhsb x R thhs + P dlsa x R thhsls + T amb P dhsb x R thhsls + P dlsa x R thls + T amb P dhsa x R thhsls + P dlsb x R thls + T amb P dhsb x R thhsls + P dlsa x R thlsls + T amb Thermal Resistances Definition (values according to the PCB heatsink area) R thhs = R thhsa = R thhsb = High Side Chip Thermal Resistance Junction to Ambient (HS A or HS B in ON state) R thls = R thlsa = R thlsb = Low Side Chip Thermal Resistance Junction to Ambient R thhsls = R thhsalsb = R thhsblsa = Mutual Thermal Resistance Junction to Ambient between High Side and Low Side Chips R thlsls = R thlsalsb = Mutual Thermal Resistance Junction to Ambient between Low Side Chips Single Pulse Thermal Impedance Definition (values according to the PCB heatsink area) Z thhs = High Side Chip Thermal Impedance Junction to Ambient Z thls = Z thlsa = Z thlsb = Low Side Chip Thermal Impedance Junction to Ambient Z thhsls = Z thhsablsa = Z thhsablsb = Mutual Thermal Impedance Junction to Ambient between High Side and Low Side Chips Z thlsls = Z thlsalsb = Mutual Thermal Impedance Junction to Ambient between Low Side Chips Thermal Calculation In Transient Mode (*) T jhsab = Z thhs x P dhsab + Z thhsls x (P dlsa + P dlsb ) + T amb T jlsa = Z thhsls x P dhsab + Z thls x P dlsa + Z thlsls x P dlsb + T amb Pulse Calculation Formula = Z THδ R TH δ + Z THtp ( δ) where δ = t T p (*) Calculation is valid in any dynamic operating condition. P d values set by user. T jlsb = Z thhsls x P dhsab + Z thlsls x P dlsa + Z thls x P dlsb + T amb 0/6

21 Figure 4. MultiPowerSO-30 HSD Thermal Impedance Junction Ambient Single Pulse 00 C/W 0 Z thhs Z thhsls Footprint 4 cm 8 cm 6 cm Footprint 4 cm 8 cm 6 cm tim e (sec) Figure 4. MultiPowerSo-30 LSD Thermal Impedance Junction Ambient Single Pulse 00 0 Z thls Z thlsls Footprint 4 cm 8 cm 6 cm Footprint 4 cm 8 cm 6 cm C/W tim e (sec) /6

22 Figure 43. Thermal fitting model of an H-Bridge in MultiPowerSO-30 Table 8. Thermal Parameter (*) Area/island (cm ) Footprint R=R7 ( C/W) 0.0 R=R8 ( C/W) 0.3 R3 ( C/W) 0. R4 ( C/W).3 R ( C/W).4 R6 ( C/W) R9=R ( C/W) 0. R0=R6 ( C/W) 0.4 R=R7 ( C/W) 0.8 R=R8 ( C/W). R3=R9 ( C/W) 0 R4=R0 ( C/W) R=R=R3 ( C/W) C=C7 (W.s/ C) 0.00 C=C8 (W.s/ C) C3=C=C7 (W.s/ C) 0.0 C4=C3=C9 (W.s/ C) 0.3 C (W.s/ C) 0.6 C6 (W.s/ C) 7 9 C9=C (W.s/ C) C0=C6 (W.s/ C) C=C8 (W.s/ C) 0.07 C4=C0 (W.s/ C) Note: (*) The blank space means that the value is the same as the previous one. /6

23 PACKAGE MECHANICAL Table 9. MultiPowerSO-30 Mechanical Data Symbol millimeters Min. Typ Max. A.3 A.8. A B C D E E e F. 6.0 F 4.6. F L 0.8. N 0deg S 0deg 7deg Figure 44. MultiPowerSO-30 Package Dimensions 3/6

24 Figure 4. MultiPowerSO-30 Suggested Pad Layout 4/6

25 REVISION HISTORY Date Revision Description of Changes Sep First issue. /6

26 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 6/6

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VNH3SP30-E. Automotive fully integrated H-bridge motor driver. Description. Features

VNH3SP30-E. Automotive fully integrated H-bridge motor driver. Description. Features Automotive fully integrated H-bridge motor driver Description Datasheet - production data Features Type R DS(on) I out V ccmax MultiPowerSO-30 45 m max per leg) 30 A 40 V AEC-Q100 qualified Output current: