Utilizing a Digital PWM Controller to Monitor the Health of a Power Supply

Transcription

1 Utilizing a Digital PWM Controller to Monitor the Health of a Power Supply Mark Hagen Systems Engineer Digital Power Group Texas Instruments 13 Oct 008 CEME 1

2 A Digitally Controlled Power Supply Reasons to go digital Programmable start/stop sequencing. (Programmable start/stop delay and voltage ramp rates.) Monitoring of system power and health metrics of the circuit. Ease of adjusting the loop compensation. PC design tool does the math Can be tailored to the system late in the process since it is defined by serial bus commands instead of by RC components. 13 Oct 008 CEME

3 Start/Stop Sequence PMBus Standard supports sequencing commands TON_DELAY TON_RISE TRACKING_MODE Digital controller operation Delay timed digitally. Track desired ramp under closed loop control by slewing Vref setpoint DAC May want separate loop compensation for start/stop ramps Operating modes: Start/stop ramp Regulate Light load ramp rate defined by TON_RISE & VOUT_COMMAND rail# tracks rail#3 Vout follows digitally defined ramp 13 Oct 008 CEME 3

4 V IN Digitally Monitored Parameters (scaled input voltage) I IN (requires dedicated current sense circuit) Shunt resistor: 4-terminal, low TCR type. Current sense amplifier: INA13x, INA19x, INA1x, etc. "READ_IN" PMBus command V OUT PMBus provides for a separate measure of Vout from the control loop voltage sense. I OUT Either shunt sense circuit like Iin or Inductor DCR sense. Amplifier typically internal to controller or driver IC. Temperature duty cycle Ambient temperature measured at controller. Component temperature at each controlled power stage. "READ_DUTY_CYCLE" PMBus command Combined with Vin and Iout measure, forms a efficiency/circuit-health metric. 13 Oct 008 CEME 4

5 Power Supply as a Feedback Controlled System System consists of Plant (Power stage) Sensor network (voltage divider) Setpoint reference (Vref. Typically a DAC in digital PWM controllers.) Error amplifier (fast ADC) Compensator (digital filter) Pulse width modulator (fast digital counter) Delay elements (account for phase loss due to the time it takes to calculate and apply the control effort) 13 Oct 008 CEME 5

6 G(s) Modeling the Loop u[n] G Delay G Plant V out G Div V sense H(s) Example with analog summing junction d[n] e[n] K PWM G Delay 1 G CLA K NLR K EADC K Ve Vr AFE + K DAC ref Open-loop gain Closed-loop gain where K AFE K EADC K NLR G CLA G Delay1 K PWM v v Sense error v Sense ref H s H 1 H G s s s s s G G = analog front end gain in V/V = error ADC gain in LSB/volt = Nonlinear boost gain = Control-law accelerator (digital compensator) gain = Total sampling and CLA computational delay = PWM gain in duty/lsb G Delay G Plant G Div = On-time and any delay to multiple power stages driving V out = Transfer function from d to V out of the power stage = Divider network transfer function in V/V 13 Oct 008 CEME 6

7 u[n] G(s) G Delay G Plant V out G Div Loop Stability Criteria V sense H(s) d[n] e[n] K PWM G Delay 1 G CLA K NLR K EADC K Ve Vr AFE + K DAC ref The frequency response is derived from the average model of the power stage Open-loop gain = H(f) G(f) Stability criteria (same as analog control) Phase margin: Phase distance from 180º at the frequency where gain = 0 db want 45º to 65º Gain margin: Gain at frequency where phase = 180º want > 6 db PM GM 13 Oct 008 CEME 7

8 Power-Stage Model u[n] G(s) G Delay G Plant V out G Div V sense H(s) A (discrete) time model is needed to get accurate estimates of transient performance and stability d[n] e[n] K PWM G Delay 1 G CLA K NLR K EADC K Ve Vr AFE + K DAC ref Define continuous-time state equations (states are i L and v C ) x A xb V and q q g v C xd V out q q g Convert to discrete-time difference equations x[n] ˆ x[n ˆ 1] d[n ˆ 1] and v ˆ [n] Cx[n] ˆ out + V g c(t) DPWM L G(z) R L i L R esr + v c C eadc v ref R Hv o H=1 Design software such as Spice or the Fusion Digital Designer integrates difference equations for each interval to simulate the power stage 13 Oct 008 CEME 8

9 Define the Plant (power stage) Resulting transfer function for the plant Enter component parameter values Gain elements Vin and duty (from Vout) Series elements L, DCR, RDS(on) Parallel elements C, ESR, ESL Lump like components together 13 Oct 008 CEME 9

10 Divider-Network Model u[n] G(s) G Delay G Plant V out G Div V sense H(s) Divider scales Vout to error-adc input range. With Cp, forms anti-alias low-pass for error-adc. Set RC lowpass corner frequency at 35% to 45% of error-adc sample frequency. Continuous model R RCs KDiv 1 z 1 GDiv s KDiv R R K R C C s1 1 Digital power-design software creates a discrete model from continuous circuit description. Apply discrete transform to continuous model evaluated at each error-adc sample time Div 1 z p d[n] e[n] K PWM G Delay 1 G CLA K NLR K EADC K Ve Vr AFE + K DAC ref R 1 R G Div (f) C z C p V out V sense 13 Oct 008 CEME 10

11 Define the divider network Set the divider gain (attenuation) Set nominal Vout at ~75% of error-adc dynamic range headroom for margining, over-voltage detection. Communicated to device by PMBus commands VOUT_SCALE_LOOP VOUT_SCALE_MONITOR Define capacitors to set pole (or zero) Good idea to roll off high frequency at 70% to 90% of Nyquist frequency. (35% tp 45% of switching frequency.) 13 Oct 008 CEME 11

12 Model the Compensator POL applications require nd-order compensation Two zeros and a pole at zero Hz This is a classical PID controller (Proportional, Integral, Derivative) Discrete form: duty(z) b01z b11zb1 GCLA z u[n] e(z) z 1 G(s) G Delay G Plant V out H(s) G Div d[n] e[n] K PWM G Delay 1 K NLR K EADC K Ve Vr G CLA AFE + K DAC ref pole at origin zeros V sense Additional poles improve effect of error-voltage quantization by smoothing the CLA output: duty(z) b01z b11zb zeros 1 GCLA z e(z) z a za poles 11 1 To model in discrete time, the design software evaluates the compensator difference equation: 1 b01 b11z b1z d(z) e(z) 1 1a z a z 11 1 dn b en b en 1 b en a dn 1 a dn Oct 008 CEME 1

13 Types of Compensator Realizations nd-order table look-up (UCD911) dz Kz 0 Kz 1 K ez z1 Direct-form digital filter (UCD940) dz b z b z b ez z a z a e[n] PID-form digital filter (conceptual) e[n] Numerator K 0N K 1N K N K 01 K 11 K 1 K 00 K 10 K 0 z 1 z 1 e[n ] Numerator z 1 z 1 b 0 e[n 1] b 1 e[n ] b z 1 Denominator d[n 1] Denominator d[n] z 1 d[n] a 1 a d[n 1] d[n ] z 1 d z z z1 KP KI KD e z z1 z K K K z K 1 K K z K K P I D P I D P D z 1 z e[n] z 1 K P K l K D z 1 d [n] P d[n] l d [n] D d[n] Proportional Integral Derivative e[n 1] z 1 13 Oct 008 CEME 13

14 Choosing the Compensation u[n] G(s) G Delay G Plant V out G Div H(s) V sense d[n] e[n] K PWM G Delay 1 K NLR K EADC K Ve Vr G CLA AFE + K DAC ref Choose continuous time parameters to shape the Bode-plot loop gain to achieve desired phase and gain margin s s s s DC gain K DC d s z1 z Zeros ω z1 ω r rq z K DC or KDC Poles: origin, ω es p s s s 1 s p p Then transform the continuous-time polynomial in s to a discrete-time polynomial in z. This is typically done by the design software TI Fusion Digital Power Designer performs the transformation by: 1. Apply the bilinear transformation by substituting s into the above polynomial:. Then solve for discrete-time polynomial coefficients: Fs d z b z b z b e z z a z a s z1 z1 13 Oct 008 CEME 14

15 Define the compensation Center zeros on nd order plant pole Spreading the zeros either side of the plant pole improves the output impedance of the system In above example I reduced the nd order zero frequency a bit to buy some phase margin. Define the compensator poles Integrator function defines 1st pole at the origin. Set nd pole above 0 db cross-over to increase gain margin. 13 Oct 008 CEME 15

16 Effect of locating zeros perfect cancellation Perfectly canceling plant nd order pole does not result is lowest possible closed loop output impedance Results in increased load transient settle time. 13 Oct 008 CEME 16

17 Effect of locating zeros, cont. zeros spread Spreading zeros minimizes output impedance Lower output impedance improves load transient settle time. 13 Oct 008 CEME 17

18 Adding Nonlinear gain to the compensation Strictly linear compensation flat gain Transient response 13 Oct 008 CEME 18

19 Adding Nonlinear gain to the compensation Reduce gain for quiescent cond. where v error near 0. gain high for transient, gain low at around zero. Improves steady state voltage, peak error reduced. 13 Oct 008 CEME 19

20 Nonlinear Boost Scope traces with and without nonlinear boost pk-pk rms RMS Error Parameter Peak-to- Peak Output Excursion During Quiescent Operation Uniform gain of 1X mv 5. mv Gain boosted 3X for mv 5.0 mv v err > 5 Gain boosted 4X for 88.4 mv 5.0 mv v err > 5 V out (V) no boost 3X boost 4X boost load current Time (µs) 13 Oct 008 CEME 0

21 System Identification (Transfer Function) Digital PWM controllers offer the opportunity to identify the system dynamics (System-ID) by measuring the transfer function of the system in situ (in place). No external test equipment No auxiliary circuits or probes To do this we need to: Generate an excitation signal Inject that signal at a summing junction Capture the response of the system to the excitation From this response, calculate the open loop gain From the open loop gain determine key performance metrics of bandwidth, gain margin and phase margin. For a digitally controlled system the logical location to make the measurement is just before or just after the digital compensator. 13 Oct 008 CEME 1

22 PWM u d u' Possible Measurement Locations G(s) power stage digital controller x x 1 H(z) digital compensator Inject a sinewave at r, x 1 or x Measure response at node y, e, c, d or u Solve for GH c y' e ADC y - r Given the following basic system equations: y Gu u d c e x e r y 13 Oct 008 CEME d Hc x 1 The closed loop response at each node is: GH GH G y r x1 x 1 GH 1 GH 1 GH H H 1 u r x1 x 1 GH 1 GH 1 GH H H GH d r x1 x 1 GH 1 GH 1 GH 1 1 G c r x1 x 1 GH 1 GH 1 GH 1 GH G e r x1 x 1 GH 1 GH 1 GH

23 Calculate the open-loop gain from the closedloop response Solution of G(f)H(f) for various injection and measurement nodes: Loop gain G(f)H(f) inject at: r x 1 x y r y y x y 1 Hy x Hy Measure response at: y u d c e H r r 1 1 r H 1 u d c x x 1 1 x H 1 H u d c x d Hc 1 u x d x Hc Note that the formula for calculating open loop gain contains the compensator gain H(f) if the system is excited before the compensator and measured after, or vice-a-versa. This is not a big problem since a digital compensator is completely deterministic. Its frequency response can be calculated as: H f z exp meas b0z b1z b z a z a 13 Oct 008 CEME 3 r e 1 x 1 1 e e x e jπf T cosπf T j sinπf T meas s 1 (for a nd order compensator) T s is the compensator sample period meas s meas s

24 Type of Excitation to use for System-ID sinewave white noise # of frequencies per measurement 1 N/ Needed dynamic range narrow (few bits) wide (many bits) Needed memory (RAM) words 1k words or more Max meas. interval 1 M samples* limited by available memory Measurement signal to noise high medium Accurate Fast * 1 bit samples, 3 bit accumulator 13 Oct 008 CEME 4

25 Use table look-up technique Sinewave Generation Digital controllers such as the UCD940 or TMS30C801, have a build-in sinewave table in ROM. For each sample, step through the table with a step size defined as step N tablelen F F meas samplerate then generate the excitation signal as: phase = phase + step; index = phase >> PHASEINDEX; sine_signal = sine_table(index); // use MSB bits for sine table index // lookup excitation signal value in table When the end of the table is reached, wrap to the beginning of the table by subtracting the table length from the index. By maintaining the fractional part of the table index and rounding to determine the table entry, very high frequency resolution can be obtained. 13 Oct 008 CEME 5

26 Response Measurement The definition of a Discrete Fourier Transform (DFT) is: K k N 1 n0 v n e jπnk / N N 1 k k v n cos n j sin n n0 N N This says that we can calculate the real and imaginary magnitudes of the kth harmonic of a signal by multiplying that signal by a sine and cosine sequence and summing. Since we've already generated a sinewave to inject into the loop as the excitation signal, the response measurement is simply: cossum += d*xcos; // Accumulate cosine sum // for measurement node d sinsum -= d*xsin; // Accumulate sine sum // for measurement node d (Note that since a sine is shifted by π/ from a cosine, the cosine sequence is easily generated by adding an offset to the sine table index of 1/4 the table length.) 13 Oct 008 CEME 6

27 Example Calculation of G(f)H(f) Inject at r measure at d u' G(s) power stage y' PWM d digital controller H(z) digital compensator e ADC y - x r CPU x cos x sin z -1 z -1 cossum sinsum serial bus to host Return cossum and sinsum for each injected excitation frequency. Calculate open loop gain as follows: N X r cos Gain 1 openloop G f H f H f hr f jhi f d cossum j sinsum 1 Where Xcos is the base to peak amplitude of the excitation and N is the # samples the response is summed over. Then plot magnitude and phase of G(f)H(f) to determine phase margin, gain margin and bandwidth. 13 Oct 008 CEME 7

28 Practical Auto-ID measurements Windowing The definition for the DFT produces the response just at harmonic frequencies. These frequencies produce an integer number of cycles in the measurement interval. At other frequencies you need to do something to reduce "leakage". 1. Window the measurement data. A raised cosine or triangle window are popular options.. Modify the measurement interval so that an integer number of cycles are measured. (What we implemented.) Settling We want just the forced response, so the controller needs to wait some number of samples for the natural response to decay. 13 Oct 008 CEME 8

29 Power Stage Transfer Function The compensation in a digital PWM controller is deterministic No gain or offset error Poles and zeros concisely defined. So divide measured loop gain by known compensator TF. Then use this measured response instead of modeled plant to choose compensation. Note that the measured TF is more damped than the modeled TF. Measurement takes into account losses not included in plant model. Losses show up as effective increase in resistance, which adds damping. 13 Oct 008 CEME 9

30 Monitor power system health DC/low frequency measurements Vin, Iin Iout, Vout Temperature of each power stage AC measurements Automatic Identification of the system transfer function Use linear (average) model of the plant to estimate component values Look for a change in monitored parameter Use statistical process control techniques to decide if it has changed. 13 Oct 008 CEME 30

31 Statistical Process Control Many techniques Mean & Range charts Mean & Sigma charts Key concepts Average a set (sample) of measurements. This guarantees normally distributed measurement error based on central limit theorem. Compare sample average to a confidence interval to decide if the mean has changed. 13 Oct 008 CEME 31

32 Confidence Interval Given k where σ is the expected population standard deviation, n z n is the sample size and is the probability that the sample mean is within the confidence interval. Then the interval is k, k Example z During product development μ, σ of open loop bandwidth were found to be to be μ = 55.0 khz σ = khz. Last 4 measurements of BW using Auto-ID are 56, 58, 53, 55 khz. = 55.5 khz x z for 90% confidence is 1.96 So confidence interval is [ , ] Therefore we can say with 95% confidence that the mean has not changed. sigma (z α /) double sided probability (%) event ppm k k k k k k k k ppb 13 Oct 008 CEME 3

33 "Health" metrics Transfer function based measures open loop bandwidth, phase margin, gain margin Power stage Q Compare to expected values Don't have to measure full frequency range. One freq may be sufficient. Lossy components cause Q to be reduced. Input power vs. output power efficiency = Average duty cycle (see next slide). Temperature Power stage balance v v i IN IN OUT il UCD940 allows closed loop control of temperature balance Power stage vs ambient (measured at controller IC.) 13 Oct 008 CEME 33

34 Average Duty Cycle Capture duty cycle at output of digital compensator. At DC Then v OUT V D R OUT R Load Load IN R Rsi V L S D V IN FET switchs R SW(LOSS) R DS(ON) R S R DCR L 1 C C R C R LOAD R S D V Monitor R S and compare to SPC control limits IN V i L OUT duty in % series resistance in mohms inductor current in Amps Oct 008 CEME duty in % 34

35 Conclusion Digital PWM Controllers now offer: Programmable start/stop sequencing. Ability to Monitor power and health metrics. Power stage voltages and currents Temperature Duty cycle Complete control of compensation gain, zeros and poles. In situ measurement of system dynamics. Enables measurement at other than the lab bench. (For instance, on factory floor or installed in end equipment.) Use monitored parameters to assist in predicting failure Apply statistical confidence limits to decide if the parameter has changed. If a mean shift is indicated, issue a warning to the host system. Design tools for Digital Power: Pull together sequencing, monitoring and control configuration in one place. Allow sophisticated, accurate frequency and time simulation of the target system. Automatic System Identification of the power supply dynamics. Automatic tuning of the loop compensation. 13 Oct 008 CEME 35