Load Switch with Level-Shift

Transcription

1 Si86DDL Load Switch with Level-Shift PRODUCT SUMMARY V IN (V DS ) (V) R DS(on) ( ) Max. I D (A).8 to DESCRIPTION. at V IN =. V..3 at V IN =. V.9.8 at V IN =.8 V.7 The Si86DDL includes a p- and n-channel MOSFET in a single SC7-6 package. The low on-resistance p-channel TrenchFET is tailored for use as a load switch. The n-channel, with an external resistor, can be used as a levelshift to drive the p-channel load-switch. The n-channel MOSFET has internal ESD protection and can be driven by logic signals as low as. V. The Si86DDL operates on supply lines from.8 V to V, and can drive loads up to. A. FEATURES Low R DS(on) TrenchFET.8 V to V Input. V to 8 V Logic Level Control Low Profile, Small Footprint SC7-6 Package V ESD Protection On Input Switch, V ON/OFF Adjustable Slew-Rate Material categorization: For definitions of compliance please see /doc?999 APPLICATIONS Load Switch with Level-Shift Slew-rate Control Portable/Consumer Devices APPLICATION CIRCUITS V IN R 6 Si86DDL Q, 3 6 C V OUT. 7 I L = A C i = µf C o = µf ON/OFF Q C o LOAD 3. R C i R GND 6 8 Switching Variation R at V IN =. V, R = k COMPONENTS R Pull-Up Resistor Typical k to M a R Optional Slew-Rate Control Typical to k a C Optional Slew-Rate Control Typical pf Note: a. Minimum R value should be at least x R to ensure Q turn-on. The Si86DDL is ideally suited for high-side load switching in portable applications. The integrated n-channel level-shift device saves space by reducing external components. The slew rate is set externally so thaise-times can be tailored to different load types. Document Number: 6888 S3-68-Rev. B, 3-Dec-3 For technical questions, contact: pmostechsupport@vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

2 Si86DDL FUNCTIONAL BLOCK DIAGRAM R D SC7-6 6 R, C ON/OFF Marking Code VD XXX Lot Traceability and Date Code S Si86DDL Q, 3 6 D R, C D 3 S Part # Code ON/OFF Q Ordering Information: Si86DDL-T-GE3 (Lead (Pb)-free and Halogen-free) R ABSOLUTE MAXIMUM RATINGS (T A = C, unless otherwise noted) Parameter Symbol Limit Unit Input Voltage V IN (V DS ) On/Off Voltage V ON/OFF 8 V Load Current Continuous a, b ±. I L Pulsed b, c ± A Continuous Intrinsic Diode Conduction a I S -.3 Maximum Power Dissipation a P D.37 W Operating Junction and Storage Temperature Range T J, T stg - to C ESD Rating, MIL-STD-883D Human Body Model ( pf, ) ESD kv THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambient (continuous current) a R thja 9 3 Maximum Junction-to-Foot (Q) R thjf 3 C/W SPECIFICATIONS (T J = C, unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit Off Characteristics Reverse Leakage Current I FL V IN = V, V ON/OFF = V µa Diode Forward Voltage V SD I S = -.8 A V On Characteristics Input Voltage Range V IN.8 V On-Resistance (P-Channel) R DS(on) V ON/OFF =. V, V IN =. V, I D =.9 A..3 V ON/OFF =. V, V IN =. V, I D =. A.6. V ON/OFF =. V, V IN =.8 V, I D =. A On-State (P-Channel) Drain-Current I D(on) Notes: a. Surface mounted on FR board. b. V IN = V, V ON/OFF = 8 V, T A = C. c. Pulse test: pulse width 3 µs, duty cycle %. V IN-OUT. V, V IN = V, V ON/OFF =. V V IN-OUT.3 V, V IN = 3 V, V ON/OFF =. V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. A For technical questions, contact: pmostechsupport@vishay.com Document Number: 6888 S3-68-Rev. B, 3-Dec-3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

3 Si86DDL TYPICAL CHARACTERISTICS ( C, unless otherwise noted) I D - Drain Current (A) 3 V GS = V thru 3 V V GS =.V V GS =V V GS =.8V V DROP (V).8..9 V ON/OFF =. V to 8 V T J = o C V GS =. V. T J = o C.. V DS - Drain-to-Source Voltage (V) I L (A) Output Characteristics V DROP vs. I L at V IN =. V.. V ON/OFF =. V to 8 V T J = o C.. V ON/OFF =. V to 8 V T J = o C V DROP (V).9.6 V DROP (V).3..3 T J = o C. T J = o C I L (A) I L (A) V DROP vs. I L at V IN =. V V DROP vs. I L at V IN =.8 V V DROP (V)..3.. I L = A V ON/OFF =. V to 8 V T J = C T J = C R DS(on) - On-Resistance (Normalized) I L = A V ON/OFF =. V to 8 V V GS =. V V GS =. V V GS =.8 V 6 8 V IN - (V) V DROP vs. V IN at I L = A T J - Junction Temperature ( C) Normalized On-Resistance vs. Junction Temperature Document Number: 6888 S3-68-Rev. B, 3-Dec-3 For technical questions, contact: pmostechsupport@vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

4 Si86DDL TYPICAL CHARACTERISTICS ( C, unless otherwise noted). I L = A V ON/OFF =. V to 8 V R DS(on) - On-Resistance (Ω).3.. T J = C T J = C I S - Source Current (A) T J = C T J = C 6 8 V GS - Gate-to-Source Voltage (V) On-Resistance vs. Input Voltage V SD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage 8 3. I L = A C i = µf C o = µf. I L = A C i = µf C o = µf Switching Variation R at V IN =. V, R = k Switching Variation R at V IN =. V, R = k I L = A C i = µf C o = µf 9 6 I L = A C i = µf C o = µf Switching Variation R at V IN =.8 V, R = k Switching Variation R at V IN =. V, R = 3 k For technical questions, contact: pmostechsupport@vishay.com Document Number: 6888 S3-68-Rev. B, 3-Dec-3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

5 Si86DDL TYPICAL CHARACTERISTICS ( C, unless otherwise noted) I L = A C i = µf C o = µf 3 8 I L = A C i = µf C o = µf td(on) 6 8 Switching Variation R at V IN =. V, R = 3 k Switching Variation R at V IN =.8 V, R = 3 k Limited by R DS(on) * μs I D - Drain Current (A). ms ms ms T A = C Single Pulse s DC, s BVDSS Limited.. V DS - Drain-to-Source Voltage (V) * V GS > minimum V GS at which R DS(on) is specified Safe Operating Area, Junction-to-Foot Normalized Effective Transient Thermal Impedance t Duty Cycle =.. Notes:.. P DM. t t. Duty Cycle, D = t.. Per Unit Base = R thja = 3 C/W 3. T JM - T A = P DM Z (t) thja Single Pulse. Surface Mounted..... Square Wave Pulse Duration (s) maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?6888. Document Number: 6888 S3-68-Rev. B, 3-Dec-3 Normalized Thermal Transient Impedance, Junction-to-Ambient For technical questions, contact: pmostechsupport@vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9

6 Package Information 6 3 e b e D E E -B- -A- A A c L Dim Min Nom Max Min Nom Max A A.. A b c.... D E E e.6bsc.6bsc e L Nom 7 Nom A ECN: S-396 Rev. B, 9-Jul- DWG: Document Number: 7 6-Jul-

7 AN8 Dual-Channel LITTLE FOOT SC-7 6-Pin MOSFET Recommended Pad Pattern and Thermal Performance INTRODUCTION This technical note discusses the pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for dual-channel LITTLE FOOT power MOSFETs in the SC-7 package. These new devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around ma) need to be switched, either directly or by using a level shift configuration. Vishay provides these devices with a range of on-resistance specifications in 6-pin versions. The new 6-pin SC-7 package enables improved on-resistance values and enhanced thermal performance. PIN-OUT Figure shows the pin-out description and Pin identification for the dual-channel SC-7 device in the 6-pin configuration. SOT-363 SC-7 (6-LEADS) applications for which this package is intended. For the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of % when using a -inch square with full copper on both sides of the printed circuit board (PCB). EVALUATION BOARDS FOR THE DUAL SC7-6 The 6-pin SC-7 evaluation board (EVB) measures.6 inches by. inches. The copper pad traces are the same as described in the previous section, Basic Pad Patterns. The board allows interrogation from the outer pins to 6-pin DIP connections permitting test sockets to be used in evaluation testing. The thermal performance of the dual SC-7 has been measured on the EVB with the results shown below. The minimum recommended footprint on the evaluation board was compared with the industry standard -inch square FR PCB with copper on both sides of the board. S G D 3 Top View FIGURE. For package dimensions see outline drawing SC-7 (6-Leads) ( BASIC PAD PATTERNS See Application Note 86, Recommended Minimum Pad Patterns With Outline Drawing Access for MOSFETs, ( for the 6-pin SC-7. This basic pad pattern is sufficienor the low-power 6 D G S THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the dual SC-7 6-pin package measured as junction-to-foot thermal resistance is 3 C/W typical, 3 C/W maximum. The foot is the drain lead of the device as it connects with the body. Note that these numbers are somewhat higher than other LITTLE FOOT devices due to the limited thermal performance of the Alloy lead-frame compared with a standard copper lead-frame. Junction-to-Ambient Thermal Resistance (dependent on PCB size) The typical Rθ JA for the dual 6-pin SC-7 is C/W steady state. Maximum ratings are 6 C/W for the dual. All figures based on the -inch square FR test board. The following example shows how the thermal resistance impacts power dissipation for the dual 6-pin SC-7 package at two different ambient temperatures. Document Number: 737 -Dec-3

8 AN8 SC-7 (6-PIN) Room Ambient C Elevated Ambient 6 C Dual EVB P D T J(max) T A R JA P D o C o C o C W P D 3 mw P D T J(max) T A R JA P D o C 6 o C o C W P D mw NOTE: Although they are intended for low-power applications, devices in the 6-pin SC-7 will handle power dissipation in excess of. W. Thermal Resistance (C/W) 3 Square FR PCB Testing Time (Secs) To aid comparison further, Figure illustrates the dual-channel SC-7 thermal performance on two different board sizes and two different pad patterns. The results display the thermal performance out to steady state. The measured steady state values of Rθ JA for the dual 6-pin SC-7 are as follows: LITTLE FOOT SC-7 (6-PIN) ) Minimum recommended pad pattern (see Figure ) on the EVB of. inches x.6 inches. ) Industry standard square PCB with maximum copper both sides. 8 C/W 3 C/W FIGURE. Comparison of Dual SC7-6 on EVB and Square FR PCB. The results show that if the board area can be increased and maximum copper traces are added, the thermal resistance reduction is limited to %. This fact confirms that the power dissipation is restricted with the package size and the Alloy leadframe. ASSOCIATED DOCUMENT Single-Channel LITTLE FOOT SC-7 6-Pin MOSFET Copper Leadframe Version, REcommended Pad Pattern and Thermal Performance, AN8, ( Document Number: 737 -Dec-3

9 Application Note 86 RECOMMENDED MINIMUM PADS FOR SC-7: 6-Lead.67 (.7) APPLICATION NOTE.96 (.38). (.3).6 (.68).6 (.6).6 (.68). (.) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index Document Number: 76 8 Revision: -Jan-8

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