Load Switch with Level-Shift

Transcription

1 Si869DH Load Switch with Level-Shift PRODUCT SUMMARY V DS (V) R DS(on) ( ) I D (A).8 to.6 at V IN =. V ±.. at V IN =. V ±..33 at V IN =.8 V ±.7 DESCRIPTION The Si869DH includes a p- and n-channel MOSFET in a single SC7-6 package. The low on-resistance p-channel TrenchFET is tailored for use as a load switch. The n-channel, with an external resistor, can be used as a levelshift to drive the p-channel load-switch. The n-channel MOSFET has internal ESD protection and can be driven by logic signals as low as. V. The Si869DH operates on supply lines from.8 V to V, and can drive loads up to. A. FEATURES Halogen-free According to IEC 69-- Definition TrenchFET Power MOSFETs:.8 V Rated ESD Protected: V On Input Switch, V ON/OFF 6 m Low R DS(on).8 to V Input. to 8 V Logic Level Control Low Profile, Small Footprint SC7-6 Package Adjustable Slew-Rate Compliant to RoHS Directive /9/EC APPLICATIONS Level Shifor Portable Devices APPLICATION CIRCUITS Si869DH 3 V IN R 6 Q, 3 6 C V OUT 3 I L = A C i = μf C o = μf ON/OFF C i Q C o LOAD td(on) 6 8 R R GND Note: For R switching variations with other V IN /R combinations see Typical Characteristics R at V IN =. V, R = k COMPONENTS R Pull-Up Resistor Typical k to M * R Optional Slew-Rate Control Typical to k * C Optional Slew-Rate Control Typical pf * Minimum R value should be at least x R to ensure Q turn-on. The Si869DH is ideally suited for high-side load switching in portable applications. The integrated n-channel level-shift device saves space by reducing external components. The slew rate is set externally so thaise-times can be tailored to different load types. Document Number: 739 S-79-Rev. C, -Apr-

2 Si869DH FUNCTIONAL BLOCK DIAGRAM R D D SC7-6 Top View 3 6 R, C ON/OFF S Marking Code VC XX YY Lot T raceability and Date Code S ON/OFF Si869DH Q Q, 3 6 D R, C Part # Code Ordering Information: Si869DH-T-E3 (Lead (Pb)-free) Si869DH-T-GE3 (Lead (Pb)-free and Halogen-free) R ABSOLUTE MAXIMUM RATINGS T A = C, unless otherwise noted Parameter Symbol Limit Unit Drain-Source Voltage (D-S) V DS - Input Voltage V IN V ON/OFF Voltage V ON/OFF 8 Load Current Continuous a, b ±. I L Pulsed b, c ± 3 A Continuous Intrinsic Diode Conduction a I S -. Maximum Power Dissipation a P D. W Operating Junction and Storage Temperature Range T J, T stg - to C ESD Rating, MIL-STD-883D Human Body Model ( pf, ) ESD kv THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambient (Continuous Current) a R thja C/W Maximum Junction-to-Foot (Q) R thjf SPECIFICATIONS T J = C unless otherwise noted Parameter Symbol Test Conditions Min. Typ. Max. Unit On-Resistance (P-Channel) at A R DS(on) OFF Characteristics Reverse Leakage Current I FL V IN = 8 V, V ON/OFF = V μa Diode Forward Voltage V SD I S = -. A..6. V ON Characteristics Input Voltage Range V IN.8 Drain to Source Breakdown Voltage V DS V GS = V, I D = - μa - V V ON/OFF =. V, V IN =. V, I D =. A.77. V ON/OFF =. V, V IN =. V, I D =. A.3.6 V ON/OFF =. V, V IN =.8 V, I D =.7 A..33 V IN-OUT. V, V IN = V, V ON/OFF =. V On-State (P-Channel) Drain-Current I D(on) V IN-OUT.3 V, V IN = 3 V, V ON/OFF =. V A Notes: a. Surface mounted on FR board. b. V IN = V, V ON/OFF = 8 V, T A = C. c. Pulse test: pulse width 3 μs, duty cycle %. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 739 S-79-Rev. C, -Apr-

3 Si869DH TYPICAL CHARACTERISTICS C, unless otherwise noted.6.6. V ON/OFF =. V to 8 V. V ON/OFF =. V to 8 V.. (V) V DROP.3. T J = C T J = C (V) V DROP.3. T J = C T J = C I L (A) V DROP vs. I L at V IN =. V I L (A) V DROP vs. I L at V IN =. V.6.. V ON/OFF =. V to 8 V. V ON/OFF =. V to 8 V (V) V DROP..3. T J = C T J = C (V) V DROP.3. T J = C.. T J = C I L (A) V DROP vs. I L at V IN =.8 V. 3 6 V IN (V) V DROP vs. V IN at I L =.7 A V DROP Variance (V) I L =.7 A V ON/OFF =. V to 8 V V IN =.8 V V IN =. V - On-Resistance (Ω) R SS(on) T J = C I L =.7 A V ON/OFF =. V to 8 V T J = C T J - Junction Temperature ( C) V DROP Variance vs. Junction Temperature. 3 6 V IN (V) On-Resistance vs. Input Voltage Document Number: 739 S-79-Rev. C, -Apr- 3

4 Si869DH TYPICAL CHARACTERISTICS C, unless otherwise noted.6. I L =.7 A V ON/OFF =. V to 8 V V IN =. V 6 R DS(on) - On-Resistance (Normalized).. V IN =.8 V μs) ( Time 8 I L = A C i = μf C o = μf T J - Junction Temperature ( C) Normalized On-Resistance vs. Junction Temperature t d(on) 6 8 R at V IN =. V, R = k 3 3 I L = A C i = μf C o = μf 8 6 I L = A C i = μf C o = μf td(on) 6 8 R at V IN =. V, R = k t d(on) 6 8 R at V IN =.8 V, R = k I L = A C i = μf C o = μf I L = A C i = μf C o = μf t d(on) 6 8 R at V IN =. V, R = 3 k t d(on) 6 8 R at V IN =. V, R = 3 k Document Number: 739 S-79-Rev. C, -Apr-

5 Si869DH TYPICAL CHARACTERISTICS C, unless otherwise noted I L = A C i = μf C o = μf t d(on) t r 6 8 R at V IN =.8 V, R = 3 k Normalized Effective Transient Thermal Impedance Duty Cycle =.. Notes:. P. DM. t t. t. Duty Cycle, D = t. Per Unit Base = R thja = C/W 3. T JM - T A = P DM Z (t) thja Single Pulse. Surface Mounted Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance. Duty Cycle =..... Single Pulse Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg? Document Number: 739 S-79-Rev. C, -Apr-

6 Package Information 6 3 e b e D E E -B- -A- A A c L Dim Min Nom Max Min Nom Max A A.. A b c.... D E E e.6bsc.6bsc e L Nom 7 Nom A ECN: S-396 Rev. B, 9-Jul- DWG: Document Number: 7 6-Jul-

7 AN86 Dual-Channel LITTLE FOOT 6-Pin SC-7 MOSFET Copper Leadframe Version Recommended Pad Pattern and Thermal Performance INTRODUCTION 6 (mil) 87 (mil) The new dual 6-pin SC-7 package with a copper leadframe enables improved on-resistance values and enhanced thermal performance as compared to the existing 3-pin and 6-pin packages with Alloy leadframes. These devices are intended for small to medium load applications where a miniaturized package is required. Devices in this package come in a range of on-resistance values, in n-channel and p-channel versions. This technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for the dual-channel version. 96 (mil) 7 (mil) 3 (mil) 6 8 (mil) 6 (mil) 3 PIN-OUT Figure shows the pin-out description and Pin identification for the dual-channel SC-7 device in the 6-pin configuration. Both n-and p-channel devices are available in this package the drawing example below illustrates the p-channel device.. (mil) 8 (mil) 6 (mil) 6 (mil) SOT-363 SC-7 (6-LEADS) FIGURE. SC-7 (6 leads) Dual S G 6 D G EVALUATION BOARD FOR THE DUAL- CHANNEL SC7-6 D 3 Top View FIGURE. S The 6-pin SC-7 evaluation board (EVB) shown in Figure 3 measures.6 in. by. in. The copper pad traces are the same as described in the previous section, Basic Pad Patterns. The board allows for examination from the outer pins to the 6-pin DIP connections, permitting test sockets to be used in evaluation testing. For package dimensions see outline drawing SC-7 (6-Leads) ( BASIC PAD PATTERNS See Application Note 86, Recommended Minimum Pad Patterns With Outline Drawing Access for MOSFETs, ( for the SC-7 6-pin basic pad layout and dimensions. This pad pattern is sufficienor the low-power applications for which this package is intended. Increasing the drain pad pattern (Figure ) yields a reduction in thermal resistance and is a preferred footprint. The thermal performance of the dual 6-pin SC-7 has been measured on the EVB, comparing both the copper and Alloy leadframes. This test was then repeated using the -inch PCB with dual-side copper coating. A helpful way of displaying the thermal performance of the 6-pin SC-7 dual copper leadframe is to compare it to the traditional Alloy version. Document Number: 7 -Dec-3

8 AN86 Front of Board SC7-6 Back of Board SC7-6 S G D SC7 6 DUAL D G S vishay.com FIGURE 3. THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) COOPER LEADFRAME Room Ambient C Elevated Ambient 6 C Thermal performance for the dual SC-7 6-pin package is measured as junction-to-foot thermal resistance, in which the foot is the drain lead of the device as it connects with the body. The junction-to-foot thermal resistance for this device is typically 8 C/W, with a maximum thermal resistance of approximately C/W. This data compares favorably with another compact, dual-channel package the dual TSOP-6 which features a typical thermal resistance of 7 C/W and a maximum of 9 C/W. P D T J(max) T A R JA P D o C o C o C W P D 8 mw P D T J(max) T A R JA P D o C 6 o C o C W P D mw Although they are intended for low-power applications, devices in the 6-pin SC-7 dual-channel configuration will handle power dissipation in excess of. W. Power Dissipation The typical R JA for the dual-channel 6-pin SC-7 with a copper leadframe is C/W steady-state, compared to 3 C/W for the Alloy version. All figures are based on the -inch FR test board. The following example shows how the thermal resistance impacts power dissipation for the dual 6-pin SC-7 package at varying ambient temperatures. Alloy Leadframe ALLOY LEADFRAME Room Ambient C P D T J(max) T A R JA P D o C o C 3 o C W P D 33 mw Elevated Ambient 6 C P D T J(max) T A R JA P D o C 6 o C 3 o C W P D 8 mw TESTING To further aid the comparison of copper and Alloy leadframes, Figures and illustrate the dual-channel 6-pin SC-7 thermal performance on two different board sizes and pad patterns. The measured steady-state values of R JA for the dual 6-pin SC-7 with varying leadframes are as follows: LITTLE FOOT 6-PIN SC-7 ) Minimum recommended pad pattern on the EVB board (see Figure 3). ) Industry standard -inch PCB with maximum copper both sides. Alloy 8 C/W 3 C/W Copper 3 C/W C/W The results indicate that designers can reduce thermal resistance ( JA) by 3% simply by using the copper leadframe device as opposed to the Alloy version. In this example, a 7 C/W reduction was achieved without an increase in board area. If an increase in board size is feasible, a further C/W reduction can be obtained by utilizing a -inch. PCB area. The Dual copper leadframe versions have the following suffix: Dual: Compl.: Si9xxEDH SixxEDH Document Number: 7 -Dec-3

9 AN86 Thermal Resistance (C/W) 3 Alloy Copper Thermal Resistance (C/W) 3 Alloy Copper Time (Secs) Time (Secs) FIGURE. Dual SC7-6 Thermal Performance on EVB FIGURE. Dual SC7-6 Comparison on -inch PCB Document Number: 7 -Dec-3 3

10 Application Note 86 RECOMMENDED MINIMUM PADS FOR SC-7: 6-Lead.67 (.7) APPLICATION NOTE.96 (.38). (.3).6 (.68).6 (.6).6 (.68). (.) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index Document Number: 76 8 Revision: -Jan-8

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