SC560. Dual Output Low Noise LDO Linear Regulator. POWER MANAGEMENT Features. Description. Applications. Typical Application Circuit

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1 POWER MANAGEMT Features Input voltage range.v to.v Output voltage ranges.v to.v (each LDO) Maximum output current ma (both LDOs) Dropout at ma load mv max. Quiescent supply current μa (both LDOs enabled) Shutdown current na (typ) Output noise < μv RMS (SCA and fixed output versions) PSRR < -db at khz (SCA and fixed output versions) Over-temperature protection Short-circuit protection Under-voltage lockout Power good monitor for output A (SCC and fixed output versions) Independent enable/disable for LDOB (SCB and fi x ed output versions) MLPQ-UT,.mm x.mm x.mm package Lead-free and halogen-free Applications PDAs and cellular phones GPS devices Palmtop computers and handheld instruments TFT/LCD applications Wireless handsets Digital cordless phones and PCS phones Personal communicators Wireless LAN Description SC Dual Output Low Noise LDO Linear Regulator The SC is a family of dual output, ultra-low dropout linear voltage regulators designed for use in battery powered wireless applications. The SCA, SCB, and SCC provide adjustable output voltages that can be set using two external resistors. Fixed output voltages are also available (see ordering information for available combinations). Fixed output devices provide the powergood monitor, independent enable pins, and a bypass pin for low-noise operation All members of the SC family require an input voltage level between.v and.v. Output voltages for the adjustable versions can vary between.v and.v. Fixed output voltage options are also chosen from this range. The SCA provides superior low-noise performance by using an external bypass capacitor connected to pin to filter the bandgap reference. The SCB uses pin as a separate enable pin for the second regulator output so the two outputs can be controlled independently. The SCC uses this pin to provide a output to hold a processor in reset when the voltage on is not in regulation. All other versions provide all three functions with fixed output voltages (no feedback pins are provided). The device also provides protection circuitry such as current limiting, under-voltage lockout, and thermal protection to prevent device failures. Stability is maintained by using µf capacitors on the output pins. The MLPQ-UT package and ceramic capacitors minimize the required PCB area. Typical Application Circuit SCD B B C IN.µF GND B YP C BYP nf C µf C µf Rev.. Semtech Corporation

2 Pin Configuration Ordering Information Device Package SCxULTRT ()()() MLPQ-UT.. TOP VIEW SCxEVB () Evaluation Board Notes: () Available in tape and reel only. A reel contains, devices. () Available in lead-free package only. Device is WEEE and RoHS compliant and halogen-free. () The device variant is denoted by the x. MLPQ-UT-;.x., LEAD θ JA = C/W Marking Information Pinout and Voltage Options Device Pin Options Output Voltage Options Pin Pin Pin V LDOA V LDOB Part No. Code SCA FBA BYP FBB ADJ ADJ A SCB FBA B FBB ADJ ADJ B n yw SCC FBA FBB ADJ ADJ C SCD B BYP.V.V D SCE B BYP.V.V K SCF B BYP.V.V L SCG B BYP.V.V U SCH B BYP.V.V S SCL B BYP.V.V Z n = Part No. Code See Pinout and Voltage Options Table for details yw = Datecode

3 Absolute Maximum Ratings (V) to +., B (V) to ( +.) (V) to ( +.) Pin Voltage All Other Pins (V) to ( +.), Short Circuit Duration Continuous ESD Protection Level () (kv) Recommended Operating Conditions Ambient Temperature Range ( C) < T A < + (V) < <. V, V (V) < V OUT <. Thermal Information Thermal Resistance, Junction to Ambient () ( C/W)... Maximum Junction Temperature ( C) Storage Temperature Range ( C) to + Peak IR Reflow Temperature (s to s) ( C) Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: () Tested according to JEDEC standard JESD-A-B. () Calculated from package in still air, mounted to x. (in), layer FR PCB with thermal vias under the exposed pad per JESD standards. Electrical Characteristics Unless otherwise noted =.V, C IN =.μf, C = C = μf, V = V B =, T A = - to + C. Typical values are at T A = C. All specifications apply to both LDOs unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Input Supply Voltage Range.. V Output Voltage V OUTx > V OUTx +.V.. V Output Voltage Accuracy ΔV OUTx =.V to.v, I OUTx = to ma, > VOUTx +.V - % Maximum Output Current I MAX ma Dropout Voltage () V D I OUTx = ma, V OUTx =.V mv I OUTx = ma, V OUTx =.V to.v mv Shutdown Current I SD T A = C. μa Quiescent Current I Q I = I = ma, T A = C μa Load Regulation ΔV LOAD I OUTx = ma to I MAX mv Line Regulation ΔV LINE I OUTx = ma - mv Feedback Regulation Voltage () V FB.9. V Current Limit I LIM ma

4 Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units =.V, I OUTx = ma, Hz < f < khz, C BYP = nf μv RMS Noise () e N =.V, I OUTx = ma, Hz < f < khz μv RMS Power Supply Rejection Ratio () PSRR =.V, I OUTx = ma, f = khz, C BYP = nf =.V, I OUTx = ma, f = khz db Delay () t DELAY ms Threshold () V TH- Percentage of nominal output, V falling 9 % Start-Up Time t SU From OFF to % V OUTx, I OUTx = ma, C BYP = nf () ms Power Up Delay Between LDOA and LDOB () t DELAY Delay between V and V start-ups μs Under Voltage Lockout V UVLO Rising... V UVLO Hysteresis V UVLO-HYS mv Over Temperature Protection Threshold T OT Temperature Rising C Over Temperature Hysteresis T OT-HYS C Digital Inputs Logic Input High Threshold V IH =.V. V Logic Input Low Threshold V IL =.V. V Logic Input High Current I IH =.V μa Logic Input Low Current I IL =.V μa Digital Outputs Output voltage Low V OL I SINK = μa, =.V mv Notes: () Dropout voltage is defined as - V OUTx, when V OUTx is mv below the value of V OUTx at = V OUTx +.V. () SCA, SCB and SCC only () Except SCB and fixed output versions () Except SCA and SCB () SCA and SCC only

5 Typical Characteristics V =.V, =.V Load Regulation LDOA V =.V, =.V Load Regulation LDOB Output Voltage Variation (mv) T A= C T A= C T A=- C Output Voltage Variation (mv) T A= C T A= C T A=- C Output Current (ma) Output Current (ma) Line Regulation LDOA Line Regulation LDOB V =.V, I = ma V =.V, I = ma. Output Voltage Variation (mv).. T A= C T A= C T A=- C Output Voltage Variation (mv).. T A= C T A=- C T A= C Input Voltage (V) Input Voltage (V) V =.V, I = ma Dropout Voltage LDOA V =.V, I = ma Dropout Voltage LDOB - VOUT (mv) T A= C - VOUT (mv) T A= C T A= C T A=- C T A= C T A=- C Input Voltage (V) Input Voltage (V)

6 Typical Characteristics (continued) PSRR vs. Frequency (Both LDOs) PSRR vs. Frequency (Both LDOs) V OUT =.V, Io=mA, C BYP=nF V OUT =.V, IO = ma, no CBYP PSRR (db) - - PSRR (db) Frequency (Hz) - Frequency (Hz) Output Noise vs. Load Current (Both LDOs) Output Noise vs. Load Current (Both LDOs) V OUT =.V, =.V, C BYP=nF V OUT =.V, =.V, no CBYP Output Voltage Noise (µv) T= C T= C T=- C Output Voltage Noise (µv) T A= C T A= C T A=- C Output Current (ma) Output Current (ma) Load Transient Response Rising Edge (Both LDOs) =.V, V OUT =.V Load Transient Response Falling Edge (Both LDOs) =.V, V OUT =.V I OUT =ma to ma (ma/div) I OUT =ma to ma (ma/div)) V OUT (mv/div) V OUT (mv/div) μs/div μs/div

7 Typical Characteristics (continued) SCA Noise Spectrum = V, FB = kω//.μf+kω, by pass=nf, C OUT =μf SCA PSRR vs. Frequency (Both LDOs) = V, FB = kω//.μf+kω, Load=mA, by pass=nf, C OUT =μf 9 Noise (nv/rthz) PSRR (db).. Frequency (khz). Frequency (khz) Pin Configurations and Descriptions Pin # SCA SCB SCC SC Fixed Output Pin Name Pin Function Output for LDOB Input supply voltage terminal Output for LDOA FBA Feedback sense pin for LDOA Connect this pin to an external resistor divider to set V GND Analog and digital ground Logic input active HIGH enables both LDOs for the SCA and SCC, or LDOA for all other variants. must be active in the SCB and the fixed output variants before B can be activated. BYP LDO bypass output Bypass with a nf capacitor B FBB Logic input active HIGH enables LDOB for SCB and the fixed voltage variants. Power Good output monitors the level of LDOA, switches low when the output drops out of regulation ( is open drain). Feedback sense pin for LDOB Connect this pin to an external resistor divider to set V

8 Block Diagrams VREF UVLO O /T Power- ON Logic LDOB LDOA GND B FBB FBA SCB VREF UVLO O /T Power- ON Logic LDOB LDOA GND BYP FBB FBA SCA

9 Block Diagrams (continued) SCC VREF UVLO Logic GND O /T LDOA FBA Power- ON Logic LDOB FBB SC Fixed Output Versions VREF BYP UVLO Logic GND O /T LDOA B Power- ON Logic LDOB 9

10 Detailed Application Circuits SCA and SCB R R C.µF R R GND FBA SCA FBB B YP C µf C µf C nf R R B A C.µF A GND B SCB BYP C nf C µf C µf V CC

11 Detailed Application Circuits SCC and SC Fixed Output Versions R R C.µF GND FBA SCC FBB C µf C µf V CC R R B A C.µF A GND B SC () BYP C nf C µf C µf V CC Note: () SCD through SCL

12 Applications Information General Description The SC is a family of dual output linear regulator devices intended for applications where low dropout voltage, low supply current, and low output noise are critical. Each device provides a very simple, low cost solution for two separate regulated outputs. Very little PCB area is required due to the miniature package size and the need for only four external capacitors. The linear regulators LDOA and LDOB are powered from a single input supply rail, and each provides ma of output current. The SC can provide output voltages in the range.v to.v. The output voltages for the SCA, SCB and SCC are set by connecting external resistor dividers to the feedback pins of each LDO. All other versions of the SC have fi x ed output voltage values shown in the Pinout and Voltage Options table on page. Refer to the previous two pages for detailed application circuits for each version. Power On Control The SCA and SCC devices have a single enable pin () that controls both LDO outputs. Pulling this pin low causes the device to enter a low power shutdown mode where it typically draws na from the input supply. When transitions high, the output of LDOA is enabled. After a delay of μs, the output of LDOB is enabled. In the SCC, when the output voltage of LDOA reaches % of its regulation point, the delay timer starts and the signal transitions high after a delay of ms. The power up/down sequence is shown in the timing diagram in Figure. The SCB and the fixed output variants provide a separate enable pin for LDOB which allows LDOA and LDOB to be enabled independently. The pin controls the LDOA output and the B provides the same functionality relative to the LDOB output. The table shown below lists the effect of the polarity of the and B signals on the outputs of LDOA and LDOB. Note from the table that LDOB can only be enabled when LDOA is already active. Since LDOB can be enabled separately, there is no timing relationship between the two outputs at startup. B LDOA LDOB Low Low Off Off Low High Off Off High Low On Off High High On On The SCC and the fixed output variants have a signal which monitors the output of LDOA and transitions high ms after LDOA has reached % of its regulation point. This can be used to hold a processor in reset when the output voltage is out of regulation. Note that when LDOA drops out of regulation and is forced low, LDOB is also disabled until is reset. Output Voltage Selection The output voltage of each LDO for the SCA, SCB, and SCC version is set independently using external resistor dividers. Figure illustrates the proper connection for LDOA. FBA % % ms R µs R Figure Timing Diagram Figure Output Voltage Feedback Circuit

13 Applications Information (continued) The values of the resistors in the voltage divider network can be calculated using the equation: V OUT V REF R R R where V REF = V. The value of R should be kω or less to ensure noise performance and stability. Values significantly less than kω will impact the quiescent current. Protection Features The SC family provides the following protection features to ensure that no damage is incurred in the event of a fault condition: Under-Voltage Lockout Over-Temperature Protection Short-Circuit Protection Under-Voltage Lockout The Under-Voltage Lockout (UVLO) circuit protects the device from operating in an unknown state if the input voltage supply is too low. When the drops below the UVLO threshold, the LDOs are disabled and is held low (SCC and fixed output variants only). When is increased above the hysteresis level, the LDOs are re-enabled into their previous states, provided has remained high. When powering up with below the UVLO threshold, the LDOs remain disabled and is held low (SCC and fixed output variants only). Short-Circuit Protection Each output has short-circuit protection. If the output current exceeds the current limit, the output voltage will drop and the output current will be limited until the load current returns to a specified level. If a short-circuit occurs on the output of LDOA, the output of LDOB will also be disabled until the fault is removed and the load current returns to a specified level. Component Selection A capacitance of μf or larger on each output is recommended to ensure stability. Ceramic capacitors of type XR or XR should be used because of their low ESR and stable temperature coeffi c ients. It is also recommended that the input be bypassed with a.μf, low ESR XR or XR capacitor to minimize noise and improve transient response. Note: Tantalum and YV capacitors are not recommended. The BYP pin on the SCD and the fixed output versions must have a minimum of nf connected to ground to meet all noise-sensitive requirements. Increasing the capacitance to nf will further improve PSRR and output noise. Over-Temperature Protection An internal Over-Temperature (OT) protection circuit is provided that monitors the internal junction temperature. When the temperature exceeds the OT threshold as defined in the Electrical Characteristics section, the OT protection disables both LDO outputs and holds the signal low. When the junction temperature drops below the hysteresis level, the LDOs are re-enabled into their previous states and transitions high after a ms delay, provided has remained high (SCC and fixed output variants only).

14 Applications Information (continued) Thermal Considerations Although each of the two LDOs in the SC can provide ma of output current, the maximum power dissipation in the device is restricted by the miniature package size. The graphs in Figure and Figure can be used as a guideline to determine whether the input voltage, output voltages, output currents, and ambient temperature of the system result in power dissipation within the operating limits are met or if further thermal relief is required. Maximum Total Output Current (A) Maximum Power Dissipation (W) Vo=.V Vo=.V. T A=+ C, P D (MAX)=.W T A=+ C, P D (MAX)=.W.... Input Voltage (V) Figure Safe Operating Limit T J(Max)= C T J(Max)= C Maximum Recommended Input Voltage The following procedure can be followed to determine if the thermal design of the system is adequate. The junction temperature of the SC can be determined in known operating conditions using the following equation: T J = T A +(P D x θ JA ) where T J = Junction Temperature ( C) T A = Ambient Temperature ( C) P D = Power Dissipation (W) θ JA = Thermal Resistance Junction to Ambient ( C/W) Example An SCD is used to provide outputs of.v, ma from LDOA and.v, ma from LDOB. The input voltage is.v, and the ambient temperature of the system is C. and P D =.(..) +.(..) =.9W T J = + (.9 x ) =. C Figures and show that the junction temperature would be within the maximum specification of C for this power dissipation. This means that operation of the SC under these conditions is within the specified limits and the device would not require further thermal relief measures. - - Ambient Temperature ( o C) Figure Maximum P D vs. T A

15 Applications Information (continued) Layout Considerations While layout for linear devices is generally not as critical as for a switching application, careful attention to detail will ensure reliable operation. The diagram below illustrates proper layout of a circuit using the SCA. For variants that don t require current setting resistors, these devices can be omitted from the layout. Attach the part to a large copper footprint, to enable better heat transfer from the device on PCBs where there are internal power and ground planes. Place the input, output, and bypass capacitors close to the device for optimal transient response and device behavior. Connect all ground connections directly to the ground plane whenever possible to minimize ground potential differences on the PCB. Ensure that the feedback resistors are placed as close as possible to the feedback pins. C R R C U C C R R U = SCA

16 Outline Drawing MLPQ-UT PIN INDICATOR (LASER MARK ) A D B E A DIMSIONS DIM INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX A A A (.) (.) b D.9 BSC. BSC E.9 BSC. BSC e. BSC. BSC L N aaa.. bbb.. aaa C A SEATING PLANE A C LxN e... N bxn bbb C A B NOTES:. CONTROLLING DIMSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

17 Land Pattern MLPQ-UT Z DIMSIONS G DIM INCHES MILLIMETERS C (.) (.) G.. X (C ) X P (G ) (Z) P R.... X Y.... Z.. R Y NOTES:. CONTROLLING DIMSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).. THIS LAND PATTERN IS FOR REFERCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO SURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.

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