UNIVERSITY OF CALGARY. Behavioral Modeling of Mixerless Three-Way Amplitude Modulator-Based Transmitter. Jatin Chatrath A THESIS

Transcription

1 UNIVERSITY OF CALGARY Behavioral Modeling of Mixerless Three-Way Amplitude Modulator-Based Transmitter by Jatin Chatrath A THESIS SUBMITTED TO THE FACULTY OF GRADUATE STUDIES IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE GRADUATE PROGRAM IN ELECTRICAL AND COMPUTER ENGINEERING CALGARY, ALBERTA APRIL, 217 Jatin Chatrath 217

2 Abstract With an enormous rise in the application of smartphones, the need for highly efficient radio architectures has increased significantly. Modern communication systems will be adopting a 5 th Generation (5G) standard for meeting the demands of the users efficiently. Analog mixers are a vital component of any transmitter and perform the necessary task of up-converting a signal. However, there are certain limitations associated with mixers including energy inefficiency. To eliminate these effects, three-way mixerless transmitter (TWMT) architecture has been proposed in the literature. Existing behavioral model for such an architecture make use of the digital splitters and combiners. In this thesis, we propose a Triadic Complex Memory Polynomial based model for the forward and inverse modeling of TWMT using analog combiners and splitters leading to a realistic scenario. Extensive simulations and measurements have been used to validate their performance. The model meet the desired design criteria concerning NMSE and ACLR. ii

3 Acknowledgements I would like to take this opportunity to acknowledge people who have contributed immensely towards the completion of my thesis. Firstly, I would extend my deep sense of gratitude to my supervisor, Dr. Mohamed Helaoui for his guidance, support and maintaining patience throughout my degree. Without his excellent supervision and constructive inputs, my thesis would not have been successfully completed. I am grateful to my professor Dr. Fadhel M. Ghannouchi for letting me utilize his research space and for providing me with excellent facilities and atmosphere for the completion of this thesis. Furthermore, I would like to thank my committee member Dr. Rushi Vyas for his valuable comments and advice on the thesis work. I extend sincere thanks to my mentors Suhas Illath Veetil and Mohsin Aziz Baig for the stimulating discussions and for helping me troubleshoot the experiments whenever needed. I would also like to thank Chris Simon for his technical support and the entire iradio Lab for their friendships and for sustaining positive atmosphere in the lab. Mom and Dad, thank you for keeping me sane, for always encouraging me to do my best, for always believing in me and supporting me along the way. I would also like to thank Kanika Nagpal for providing me constant support and motivation even though you are thousands of miles away. Last but certainly not the least, I would like to thank my friends Rosy Dabas, Piyush Rawat, Prithvi Tiwari, and Tushar Sharma for their continuous support, unparalleled love, and for the wonderful times. This journey would not have been possible without your contributions. Finally, a big thank you to everyone who has been a part of my journey and helped me to complete my degree! iii

4 Dedication To my friends and family iv

5 Table of Contents Abstract...ii Acknowledgements... iii Dedication... iv Table of Contents... v List of Tables... viii List of Figures and Illustrations... ix List of Symbols, Abbreviations and Nomenclature...xii Chapter One: Introduction Conventional direct conversion transmitters Introduction Distortion in mixers Parameters for performance analysis of a transmitter Linearity Adjacent channel power ratio Normalized mean square error Goals and objectives Thesis outline Chapter Two: State of the Art Introduction Polar Transmitters Implementation of phase modulator section in polar transmitters Envelope and phase signal recombination techniques v

6 2.2.3 Mixerless polar modulator-based transmitter Summary of transmitter architectures Variable gain amplifier Variable gain amplifier as an amplitude modulator Imperfections in VGA VGA calibration Mixerless three-way amplitude modulator-based transmitter Introduction Three-way decomposition algorithm Architecture of mixerless three-way amplitude modulator based transmitter Calibration Technique Implementation of transmitter architecture Measurement results Conclusion Chapter Three: Forward Behavioral Modeling Introduction Extended three-way signal decomposition algorithm Expressions for x in,1, y in,1 and z in,1 as a function of S 1, S 2 and S 3 when S in1 lies in Expressions for x in,1, y in,1 and z in,1 as a function of S 1, S 2 and S 3 when S in1 lies in Expressions for x in,1, y in,1 and z in,1 as a function of S 1, S 2 and S 3 when S in1 lies in vi

7 3.3 Forward model for mixerless three-way amplitude modulator-based transmitter Mathematical analysis for Mathematical analysis for Mathematical analysis for Model Extraction Algorithm Implementation of mixerless three-way amplitude modulator-based transmitter Measurement results Conclusion Chapter Four: Reverse Behavioral Modeling Introduction Digital predistortion (DPD) Reverse model for mixerless three-way amplitude modulator-based transmitter Triadic complex memory polynomial calibration Implementation of the DPD system Measurement results Conclusion Chapter Five: Conclusion and Future Work Contributions Future work References... 8 vii

8 List of Tables Table 2.1 Summary of architectures Table 2.2 VGA ADL533 Specifications Table 2.3 Summary of performance evaluation Table 3.1 Expressions for x in,1, y in,1 and z in,1 when S 1 lies in three different tridants Table 3.2 Expressions for S 1, S 2 and S 3 in three different tridants Table 3.3 Expressions of constants in different tridants... 5 Table 3.4 Summary of performance for digital combining and proposed analog combining Table 4.1 Summary of performance evaluation of the proposed model viii

9 List of Figures and Illustrations Figure 1.1. Ideal software defined radio architecture Figure 1.2. Conventional analog transmitter Figure 1.3. Conventional direct conversion transmitter Figure 1.4. The circuitry of switching mixer Figure 1.5. Two-tone test representation Figure 2.1. Polar transmitter Figure 2.2. Block diagram of mixerless polar modulator-based transmitter Figure 2.3. Variable Gain Amplifier (Analog Devices ADL533) Figure 2.4. VGA as an amplitude modulator Figure 2.5. Characteristics of VGA: (a) AM-PM, (b) AM-AM Figure 2.6. Three coordinate based signal decomposition when S in1 lies in -12 tridant Figure 2.7. Representation of law of sines Figure 2.8. Three coordinate based signal decomposition when S in1 lies in tridant Figure 2.9. Three coordinate based signal decomposition when S in1 lies in tridant Figure 2.1. Mixerless three-way transmitter architecture with digital combining ix

10 Figure Block schematic of mixerless three-way amplitude modulator-based transmitter, digital combining architecture with signal processing Figure Approximation employed in linearization technique [39] Figure Mixerless three-way amplitude modulator-based transmitter implementation Figure 3.1. High level block schematic of mixerless three-way amplitude modulator based transmitter with analog combining and splitting Figure 3.2. Expressing a point, S in1 in Figure 3.3. Expressing a point, S in1 in Figure 3.4. Expressing a point, S in1 in Figure 3.5. Block schematic of mixerless three-way amplitude modulator-based transmitter, analog combining architecture with signal processing Figure 3.6. Implementation of mixerless three-way amplitude modulator-based transmitter Figure 3.7. Hardware implementation of the mixerless three-way amplitude modulator-based transmitter Figure 3.8. Characteristics of modeled and measured output signals for digital combining architecture: (a) AM-PM, (b) AM-AM Figure 3.9. Characteristics of modeled and measured output signals for analog combining architecture: (a) AM-PM, (b) AM-AM x

11 Figure 3.1. Spectral response of modeled and measured output along with error signal for the three-way transmitter implementation with digital combining Figure Spectral response of modeled and measured output along with error signal for the three-way transmitter implementation with analog combining Figure 4.1. Block schematic for the operation of digital predistorter based on indirect learning. 67 Figure 4.2. Predistortion and linearization Figure 4.3. Forward model of the mixerless three-way amplitude modulator-based transmitter.. 7 Figure 4.4. Reverse model of mixerless three-way amplitude modulator-based transmitter Figure 4.5. LTE signal spectrum comparison between input signal, output signal before DPD and output signal after DPD Figure 4.6. Wideband spectral response of the proposed architecture xi

12 List of Symbols, Abbreviations and Nomenclature Symbol Definition 3 GPP 3 rd Generation Partnership Project 3G 4G 5G ACLR ACPR ADC ADS AM AM-AM AM-PM CW DAC DC DCO DPA DPD DSP DUT EER EVM Third Generation Fourth Generation Fifth Generation Adjacent Channel Leakage Ratio Adjacent Channel Power Ratio Analog to Digital Converter Advanced Design System Amplitude Modulation Amplitude to Amplitude Modulation Amplitude to Phase Modulation Continuous Wave Digital to Analog Converter Direct Current Digitally Controlled Oscillator Digital Power Amplifier Digital Predistortion Digital Signal Processing Device Under Test Envelope Elimination and Restoration Error Vector Magnitude xii

13 FIR FPGA I IF K LO LTE LTE-A LUT M MP NMSE PA PLL PM PM-AM PM-PM PSA PWM Q QPSK RF SDR Finite Impulse Response Field Programmable Gate Array In-Phase Intermediate Frequency Nonlinearity Local Oscillator Long Term Evolution Long Term Evolution Advanced Look Up Table Memory Depth Memory Polynomial Normalized Mean Square Error Power Amplifier Phase Locked Loop Phase Modulation Phase Modulation to Amplitude Modulation Phase Modulation to Phase Modulation Power Signal Analyzer Pulse Width Modulation Quadrature Quadrature Phase Shift Keying Radio Frequency Software Defined Radio xiii

14 TC-MP Tridant TWMT VGA VSA WCDMA WLAN Triadic Complex Memory Polynomial There is no such word in the English dictionary which refers to one third of a plane. However, in this thesis, tridant is proposed to get a more accurate appellation to refer one third of a plane. Tridant is derived from the Latin prefix tri- and suffix ant- like quadrant, which refers to quarter of a plane. Three-Way Mixerless Transmitter Variable Gain Amplifier Vector Signal Analyzer Wireless Code Division Multiple Access Wireless Local Area Network xiv

15 Chapter One: Introduction Evolution in the wireless communication industry has been extreme in the last 25 years. A sheer tool of conversation and exchange of information has become an unavoidable part of our day-today lives [1]. For a very long time, being the biggest market segment, wireless communication has only been associated with cellular telephony. However, modern wireless communication has applications in many fields including medicine, military, and engineering [2]. Vast development in the integrated circuit industry has been noticed which resulted in doubling the number of transistors on a single chip every second year as predicted by Moore s law. The increasing number of transistors has thus resulted in smartphones with better signal processing power and data rates. Moreover, reduced cost of production in the semiconductor industry has also enhanced the production of reliable and cheap priced communication devices. Combined, these developments led to designing and manufacturing of smartphones with continuously increasing processing power. To fully exploit high processing power of smartphones, signal modulation schemes should be developed with high data rates and efficiency [3]. Therefore, the need for very high-speed communication systems gave rise to new communication protocols and standards. A variety of communication standards, such as Wireless Local Area Network (WLAN) and Wireless Code Division Multiple Access (WCDMA), should be supported by new smartphones. With the invention of 3 rd Generation Partnership Project (3GPP) communication signals, a milestone in the communications industry has been achieved [4]. The 3GPP standard offers higher data rates and complex modulation schemes. Another breakthrough in the communication industry was witnessed with the invention of Long Term Evolution (LTE) signal standard. It is based on Orthogonal Frequency Division Multiplexing (OFDM) and operated in different bandwidths and modulation schemes. Therefore, the LTE signal required high-performance transceiver systems. 1

16 With the passing time, communication standards have continuously evolved to integrate higher data rate and efficiency. The recent development of Long Term Evolution Advanced (LTE-A) from LTE allows to deploy bandwidths up to 1 MHz [5]. With the evolution of wireless communication standards and signals, it was of prime importance to either upgrade or replace the existing radio hardware. One of the vital features of this new radio hardware should be the compatibility with the devices which still work on older communication schemes. Tx Rx DAC ADC Microprocessor Microprocessor Figure 1.1. Ideal software defined radio architecture. In recent years, researchers from all over the world have been trying to develop transceivers which can cater to the needs of different standards. The development of transceivers would facilitate bringing the digital domain of the hardware as close as possible to the antenna to realize Software- Defined Radio (SDR) [6, 7]. An ideal SDR supports any waveform by modifying the firmware or software, keeping the hardware unchanged. Hereby, the term waveform refers to a signal with a specific value for all parameters such as carrier frequency, data rate, modulation, coding, sampling frequency, etc. The ideal SDR is shown in Fig The microprocessor maps the user data into the desired waveform. The Digital-To-Analog Converter (DAC) converts the digital samples to a Radio Frequency (RF) signal which is further sent to the transmitting antenna. The transmitted signal enters the receiver through the receiver s antenna, followed by sampling and digitization by 2

17 an Analog-To-Digital converter (ADC). The sampled signal is finally processed in real time by a general-purpose microprocessor to obtain the user data. It is extremely challenging to develop such an ideal and sophisticated SDR. The quest of developing an ideal SDR has just started. The performance of these systems is gravely affected by the various impairments associated with the different blocks in the transceiver. Modeling and moderation of these impairments is a major step towards the realization of an optimal SDR platform [7]. 1.1 Conventional direct conversion transmitters Introduction Transmitter and receiver are the two vital blocks of any radio. In this thesis, the primary focus will be on the transmitter block. Frequency up-conversion, digital modulation, and amplification are some of the crucial functions performed by the transmitter. The amplified signal is then transmitted through an antenna to a distant receiver. A block diagram of a conventional analog transmitter is shown in Fig Components like RF power amplifier, anti-aliasing filter, and band-pass filter are frequency selective, which means they work over a certain frequency range, and therefore they limit the bandwidth of the transmitter. However, filtering the signal at different stages of the transmitter reduces the unwanted signals and spurs, therefore, is essential to meet the spectrum mask requirements in conventional transmitter design. Since these filters limit the RF bandwidth of the transmitter architecture, designing broadband and multi-standard transmitters is a challenging task. Multi-standard transmitters are often designed using multiple parallel transmitter chains, each for a different standard. This approach results in high hardware complexity, high cost, and is not reconfigurable for future standards. Therefore, transmitters that are reconfigurable and 3

18 can accommodate multiple standards are needed. To build such architectures, frequency selective filters which are band limiting and hard to integrate should be eliminated from the transmitter design. Antenna Anti-aliasing Filter Variable Gain Amplifier Mixer Band Pass Filter RF Power Amplifier DSP DAC Local Oscillator (LO) Figure 1.2. Conventional analog transmitter. Evidently, there are mainly three main topologies of transmitter architectures: super-heterodyne, low Intermediate Frequency (IF) and, direct conversion [8]. Direct conversion architecture is the most frequently used topology in multi-band and multi-standard applications due to its ease in design and low implementation complexity [9]. Fig. 1.3 represents an analog quadrature RF transmitter, which is based on direct conversion topology. The DACs are fed with digital baseband In-Phase (I) and Quadrature (Q) data. The Nyquist criterion is satisfied by the DACs which in turn moves the DAC replicas away from the desired band. Reconstruction filters that are placed after the DACs remove the aliasing replicas. Variable Gain Amplifiers (VGAs) adjust the gain in the I and Q paths. The signal in the form of I and Q is then fed to a quadrature modulator. To up-convert the signal to the desired carrier frequency and generate the complex modulated signal, the in-phase (I) component is multiplied with a Local Oscillator (LO) signal having phase shift while the quadrature (Q) component is multiplied with an LO signal having 9 phase shift. The two 4

19 multiplied signals are summed together to generate the complex modulated signal at the desired RF frequency. Band-pass filters are used to suppress the out-of-band emissions produced by the mixers of the quadrature modulator while the RF Power Amplifier (PA) is used to adjust the power level of the RF signal. The desired RF signal is then transmitted through the antenna. I DAC Re-construction Filter Variable Gain Amplifier Mixer ` Band Pass Filter Antenna DSP LO 9 Q DAC RF Power Amplifier Re-construction Filter Variable Gain Amplifier Mixer Figure 1.3. Conventional direct conversion transmitter. However, several off-chip components like filters and power amplifiers limit the bandwidth of the transmitter. Multiple filtering is involved in suppressing out-of-band distortions produced by switching mixers and to meet spectral mask requirements. This, in turn, reduces the RF bandwidth of the complete transmitter Distortion in mixers One of the significant components of conventional direct conversion topology is the switching mixer. Fig. 1.4 shows the diagram of ideal switching mixer that is commonly used in direct conversion architectures. Such mixers implement polarity switching function in response to the LO input while maintaining the low noise and high linearity objectives. 5

20 Amplitude Amplitude Baseband Input x(t) +1 Switching x(t).lo Output Frequency (f) -1 f LO f LO 3f LO Frequency (f)... 5f LO f LO Frequency (f) 3f LO 5f LO... Figure 1.4. The circuitry of switching mixer. In switching mixers, LO signal is a square wave which can be expressed using Fourier series as, LO sin(2 flot) sin(6 flot) sin(5 flot) (1.1) where f LO is the frequency of the LO. Then, the output of the switching mixer can be represented as, 4 1 Output A( t) cos(2 fbbt ( t))sin(2 flot) cos(2 fbbt ( t))sin(6 flot)... 3 (1.2) where f BB is the frequency of baseband signal. This equation can be further simplified and represented as, sin(2 ( fbb flo) t ( t)) sin(2 ( fbb flo) t ( t)) 2 Output A () t 1 1 sin(2 ( fbb 3 flo) t ( t)) sin(2 ( fbb 3 flo) t ( t)) (1.3) where f RF and f LO are the baseband and LO frequency, respectively. The equation (1.3) shows that switching mixers are responsible for producing harmonics at different frequencies of LO. These harmonic distortions are generated by switching function of the mixer and not by nonlinear gain. Therefore, these distortions cannot be compensated with 6

21 linearization techniques [1]. Hence, filtering at different stages of the conventional direct conversion topology cannot be avoided. Consequently, this thesis emphasizes on the behavioral modeling and impairment compensation of a re-configurable mixerless transmitter for SDR applications. It aims at implementing a broadband mixerless transmitter in the analog domain and developing forward and reverse mathematical models to imitate the system performance and mitigate the nonlinear and linear distortion effects in this transmitter architecture. Once linearized, this transmitter will not require any band-limiting RF filtering before the power amplifier. This transmitter design would be suitable for integration, and for multi-standard and multi-band reconfigurability. Therefore, mixerless transmitters are suitable candidates for SDR topologies. 1.2 Parameters for performance analysis of a transmitter Linearity Linearity is a crucial requirement of a transmitter as nonlinearity in the transmission system causes degradation in the signal quality, which makes the information detection and demodulation difficult at the receiver. A transmitter is said to be linear if and only if the corresponding output is directly proportional to its input. Off-chip linear and nonlinear components like power amplifiers and band-pass filters, generally degrade the signal quality in the transmitter by introducing linear and nonlinear distortions. To achieve high quality signals, the transmitter should be equalized and linearized to suppress these distortions. The nonlinear distortions in the transmitter generate intermodulation products in the band of the signal and harmonic products at multiples of the carrier frequency [11]. A two-tone test or a modulated signal test can be used to measure these harmonics [12]. Fig. 1.5 shows how intermodulation products are generated when a two-tone signal is fed to 7

22 a nonlinear system. When a signal is supplied to a nonlinear system it generates even and odd order products such as second order and third order. The even-order nonlinearities lie away from the desired band and are often filtered out at the output of the nonlinear system using RF bandpass filters. Odd order nonlinearities generate intermodulation distortion close to fundamental frequency resulting in in-band distortion and cannot be filtered out. Non-Linear System Third-Order Distortion Product 2f 1 -f 2 2f 2 -f 1 Second-Order Distortion Product { 2f 1 2f 2 f 1 f 2 3f 1-2f 2 f 1 f 2 3f 2-2f 1 f1+f 2 Fifth-Order Distortion Product Figure 1.5. Two-tone test representation. Conventionally, linearization techniques such as digital and analog predistortion [13] are used to compensate for these nonlinear effects. A very low power of the intermodulation product (2f 1 -f 2 and 2f 2 -f 1 ) as compared to the power of fundamental tones (f1 and f 2 ) depicts a highly linear transmitter architecture and minimum in-band distortion to the signal. The in-band distortion can be quantified using a figure of merit called Normalized Mean Square Error (NMSE) while the outof-band distortion is quantified using a figure of merit called Adjacent Channel Power Ratio (ACPR). 8

23 1.2.2 Adjacent channel power ratio In case of modulated signals, nonlinearity in the device results in intermodulation products, which leads to spectral regrowth. This regrowth, in turn, may cause interference in the adjacent channels [11]. To avoid the interference, nonlinearity in the devices must be modeled and mitigated. ACPR is an important figure of merit for evaluating the performance of a transmitter in the presence of nonlinearity. It quantifies the spectral regrowth in nonlinear systems and devices. ACPR can be defined as the difference between the out-of-band power spectral density measured at certain offset channel in dbm, P offset (dbm), and the in-band power spectral density in dbm, P inband (dbm) [12]. ACPR( dbc) P ( dbm) P ( dbm) (1.4) offset Adjacent Channel Leakage Power Ratio (ACLR) is the term used instead of ACPR for LTE signal waveform format. inband Normalized mean square error Normalized Mean Square Error (NMSE) is an important metric for evaluating the in-band performance of a forward and reverse behavioral model of a nonlinear system such as the transmitter. NMSE is an estimator of the overall deviations between modeled and measured values. It gives a measure of the difference between the value that is estimated by the model and the value that is measured. The NMSE [14] can be mathematically represented as, 2 N 1 Ymeas ( n) Ymod ( n) NMSE( db) 1log1 2 N n1 Ymeas ( n) (1.5) where, Y meas (n) and Y mod (n) are the output waveforms measured and estimated from the model, respectively. N is the number of discrete time samples of the signal considered in the calculation. 9

24 1.3 Goals and objectives The primary aim of this thesis work is to implement a wideband mixerless transmitter architecture that is suitable for multi-band, multi-standard, and SDR applications. The primary aim will be reached through various steps. First, this work targets the hardware implementation of the RF front-end of a Mixerless threeway amplitude modulation-based transmitter with all the passive components such as three-way power splitter/combiner and phase shifters in the analog domain. Additionally, this thesis aims at understanding and modeling the type and nature of distortion generated by this topology. A behavioral forward model, triadic complex memory polynomial (TC-MP), which models the amplitude response of all the three VGAs as a single block, will be proposed. The linear distortion in passive components such as phase shifters and power combiners/splitters will also be considered in this modeling exercise. The accuracy of the model will be decided by calculating the difference in terms of NMSE, between the model output and the actual hardware measured output. Finally, once a sound understanding of the nature and characteristics of distortions is obtained, which further will be mitigated by proposing a reverse model. The proposed reverse model will be used as a predistorter or precompensator for the mixerless transmitter. The predistorted transmitter will be measured to show the effectiveness of the reverse model by compensating the linear and nonlinear distortions. Both in-band and out-of-band distortion will be quantified in terms of NMSE and ACPR, respectively. Additionally, the power of the harmonic distortions will be measured to prove that this topology does not need any RF band-pass filtering. 1

25 1.4 Thesis outline The thesis is described as follows: The fundamentals of a radio transmitter for wireless communication is presented in chapter one. Herein, the key parameters and the performance metrics of a radio transmitter are discussed. Additionally, the chapter introduces the objectives and methodology of this thesis work. In chapter two, different mixerless architectures that are proposed in literature are introduced. Specifically, the advantages of mixerless polar transmitters and mixerless three-way amplitude modulator-based transmitters are discussed. Limitations and challenges in implementing mixerless three-way amplitude modulator-based transmitters, such as signal combining and splitting and digital predistortion implementation are listed and explained. Finally, this chapter concludes by highlighting the need to model the responses of the full transmitter, including the three amplitude modulators and other passive components, in a single box. In chapter three, the three-way amplitude modulator-based transmitter front-end is implemented fully in hardware for the first time. The transmitter translates the baseband signal to RF domain without using mixers. The responses of the VGAs and the other passive components are measured by proposing a new black box behavioral forward modeling technique for the complete three-way amplitude modulator-based transmitter. Finally, the chapter is concluded with implementation details and measurement results. In chapter four, a new reverse model is proposed to be used for digital predistortion of the mixerless transmitter. The implementation details, measurement results and the performance evaluation of the architecture are also provided at the end of this chapter. Finally, the thesis is concluded in chapter 5, with a summary of the significant contributions achieved in this work. A proposal for future work direction is also presented. 11

26 Chapter Two: State of the Art 2.1 Introduction In chapter one, the concerns with the existing mixer-based conventional direct conversion architecture were discussed. Also, the need of mixerless transmitter architecture which is more suitable for integration and reconfigurabilty was justified. The current chapter discusses the stateof-the-art attempts to realize the mixerless transmitter topologies. 2.2 Polar Transmitters The direct conversion transmitter architecture is the most frequently used topology. However, there are certain drawbacks related to the direct conversion architecture such as distortions in mixers, In-Phase and Quadrature (I/Q) modulator impairments, Direct Current (DC) offset, a Local Oscillator (LO) leakage and quantization noise as explained in [15 16]. Additionally, due to separate I and Q branches, direct conversion architectures suffer from different timing misalignment, which also results in signal quality degradation and affects the accuracy of the time delay estimation in behavioral modeling and predistortion function estimation. Many research groups have previously addressed these limitations by proposing new designing techniques and modulator architectures, suggesting signal processing algorithms to compensate for the impairments, or by testing new homodyne transmitter topologies that avoid the use of quadrature modulators and mixers. Another promising candidate for direct digital transmitters is polar transmitters, which is inspired by Envelope Elimination and Restoration (EER) technique by Kahn [17]. In polar transmitters, unlike conventional transmitters, modulation of baseband signal occurs in the amplitude and phase domain rather than I and Q components. 12

27 Amplitude I IΦ Mixer Band Pass Filter Antenna DSP LO 9 PA Q QΦ Mixer Figure 2.1. Polar transmitter. Fig. 2.1 shows the block diagram of a polar transmitter architecture in which digital baseband signal IQ is decomposed into amplitude A(t) and phase Φ(t) by, 2 2 A( t) I ( t) Q ( t) (2.1) 1 Qt () ( t) tan It () (2.2) where, I and Q are the in-phase and quadrature components of the complex IQ signal. As seen from Fig. 2.1, the phase signal Φ(t) is passed through quadrature modulator and converted in Radio Frequency (RF) domain from baseband. The phase modulated RF signal, having constant envelope is recombined with envelope signal A(t) to generate complex RF signal. High-efficiency switch mode Power Amplifier (PA) is used to recombine the envelope signal and the phasemodulated RF signal [18]. Having greater power efficiency means less DC power consumption. Also, better carrier suppression can be achieved with the polar transmitter as compared to conventional IQ architectures. However, there are certain integral challenges with the polar transmitter such as nonlinear decomposition results in bandwidth expansion. Also, delay adjustments should be precise between 13

28 the amplitude and phase paths. To satisfy spectrum mask requirements of the wireless standards, recombination of the envelope and phase signals should be done after proper delay adjustments [19] Implementation of phase modulator section in polar transmitters There are different techniques by which the phase modulator segment can be implemented such as quadrature up-converters [2, 21], external signal generators [22], vector modulators [23, 24] and Phase Lock Loop (PLL) circuits [25, 26]. The phase modulators, when realized with quadrature up-converters, have problems that are mutual to mixer based circuits. Mixer based circuits use mixers and quadrature up-converters to translate the baseband phase signal to RF domain. Such circuits suffer from mixer spurs and distortions. To eliminate these distortions, imperfect bulky filters are incorporated into the design, which further reduces the ability of integration. Besides, these filters are frequency components that limit the transmitter bandwidth. PLL circuit can be used as an exceptional phase modulator. In such circuits, phase modulation is directly applied to the synthesized RF carrier signal [16]. Apparently, it eliminates the use of IQ up-converters which in turn reduces the problem of spurious emissions. By using a digital PLL circuit, bandwidth constraints can be eradicated [27]. By decomposing IQ baseband digital signal, the phase signal is obtained which can be differentiated to obtain the frequency deviations. To generate the phase modulated carrier signal, the differentiated phase signal is supplied to the Digitally Controlled Oscillator (DCO) based modulator. In this technique, it is therefore critical to maintain the tuning range of the oscillator. However, a PLL-based architecture also holds certain challenges such as the bandwidth limitations, phase noise and the requirement of a precompensation techniques like digital filtering [27]. 14

29 2.2.2 Envelope and phase signal recombination techniques During the same tenure, significant advancements were made in the envelope and phase signal recombination techniques of polar transmitters. The most common and frequently used recombination technique is the supply or drain modulation as shown in Fig. 2.1 and explained in [2, 21]. Phase of I and Q signals are provided to the input of quadrature modulator to obtain phase modulated RF signal. The received signal is then further supplied to the input of the RF PA. Furthermore, amplitude information is inserted by varying the PA s supply voltage. The insertion of the amplitude information can either be achieved by using a switching regulator with good efficiency or by using a DC to DC converter. To achieve high efficiency, switch mode PAs can be used in saturation as input to the PA is constant envelope signal. However, switch mode PAs are nonlinear devices and often introduce distortion to the signal. Therefore, architectures that use switch mode PAs require filtering and predistortion. Hence, a trade-off between efficiency and linearity exists in such architectures due to which careful designing of supply modulators is required. Modeling techniques that are used to compensate for the distortions introduced by the switch mode PAs are detailed in [28]. Moreover, envelope conditioning methods that are used to address the issue of feed through capacitance are explained in [29, 3]. In another technique [23], Pulse-Width Modulation (PWM) is employed to realize polar transmitter architecture. To drive multiple class C amplifiers, multiphase pulse-width modulated signal is used which eventually increases the sampling frequency leading in reduction of out-ofband emissions and further minimizing the filtering requirements. This work employs vector modulator to realize phase modulation circuitry. Similarly, interleaved PWM have also been used to reduce spurs and relieve filtering requirements [24]. Additionally, to increase the efficiency of PWM, switch mode amplifiers were used as PAs. 15

30 Additional techniques such as Digital Power Amplifiers (DPAs) have also been employed for envelope and phase signal recombination without using supply modulation [22, 31, 32, 33]. Although, n number of unit amplifiers which are basically switched as per digital amplitude bits are supplied with phase modulated RF signal with constant envelope. Complex RF signal is attained by combining the outputs of these PAs. Also, to reduce the spectral images, oversampling and interpolation are applied [32]. However, the nonlinearity and power combing challenges are faced with these architectures [33]. Class D -1 PAs array based polar transmitter architecture has been implemented in [34]. Here, transformer-based power combining is employed. Initial processing has been performed in Field- Programmable Gate Array (FPGA). Primary and secondary windings of the transformer are coupled in series for power combining, whereas, the output of each PA is given to primary winding. High-efficiency PAs produce distortions to the signal, which makes the system nonlinear. To mitigate nonlinear effects, Look-Up Table (LUT)-based predistortion and oversampling is used which reduces the out-of-band noise while the phase modulator section comprises of external Digital-To-Analog (DAC) and modulator. In recent studies, Variable Gain Amplifiers (VGAs) have been used for envelope and phase signal recombination [25, 26]. Amplitude Modulated (AM) signal, also called envelope signal is generated digitally at the baseband and then fed in to the gain control port of the VGA while the RF input port of the VGA is fed with the Phase Modulated (PM) signal which has constant envelope. Thus, by changing the gain as per the gain control signal, the VGA will reconstruct the amplitude modulation. However, challenges like update rate of the VGA and dynamic range are faced by such architectures [26]. 16

31 In [35], modified Gilbert cell is used to integrate the phase path with polar transmitter. Unit amplifiers such as Class D -1 PAs, comprise the amplitude path. Primary and secondary windings of the transformer are coupled in series for power combining. To achieve higher efficiency, the impedance is varied and IQ phase interpolator is used to implement the phase modulator. Highefficiency PAs produce distortions to the signal, which makes the system nonlinear. To mitigate nonlinear effects, LUT-based predistortion is used. To deal with spurs and noise, Finite Impulse Response (FIR) interpolation filters and high sampling rate is employed Mixerless polar modulator-based transmitter Recently, a mixerless polar modulator-based transmitter architecture that uses analog RF VGA and analog phase shifter was proposed and implemented [38, 39]. The mixerless polar modulatorbased transmitter architecture is shown in Fig I Q Phase Digital Signal Processing Envelope LO Phase Shifter (Phase Modulator) Variable Gain Amplifier (VGA) (Amplitude Modulator) RF Output Figure 2.2. Block diagram of mixerless polar modulator-based transmitter. The term mixerless is used because it translates the baseband phase signal directly to RF without using mixers and up-converter circuits. Thus, spurs and distortions that are associated with typical 17

32 analog mixer and up-converters are absent. Furthermore, imperfect bulky filters which limit the bandwidth of the transmitter are eliminated in this architecture. This, in turn, makes the transmitter design reconfigurable and more suitable for integration. In this topology, baseband IQ signal is decomposed into envelope and phase components by using equations (2.1) and (2.2). The VGA maps the amplitude or the envelope to gain control voltage, while the phase shifter maps the phase component into phase control voltage. The gain control voltage drives the VGA while the phase control voltage drives the phase shifter. Furthermore, the RF Continuous Wave (CW) signal with desired frequency and power level is fed to RF input port of the phase shifter. Apparently, the output of the phase shifter now has phase modulated RF signal with constant envelope. The RF phase-modulated signal at the output port of the phase shifter is then fed to RF input port of the VGA. Through the gain control port of the VGA, the amplitude information is inserted to the phase modulated RF signal to generate the complex RF signal at the output of the VGA. The polar modulator-based transmitter topology exhibits good performance for Long Term Evolution (LTE) signal [38 39]. However, the phase shifter used in the topology has issues with noise and affects the quality of the RF output signal. The phase shifter is driven by constant control phase voltage. Over a period, phase shifter exhibits phase variations when constantly driven by control voltage. These variations were not modeled and compensated by the modified memory polynomial model proposed by the author. This unconventional behavior is not correlated with the signal, which makes them appear as phase noise at the output of the transmitter. Furthermore, at the output of the transmitter architecture, these distortions due to the phase shifter affects the overall quality of the RF signal. 18

33 2.3 Summary of transmitter architectures The various architectures of polar transmitter as well as phase modulation that are explained in section 2.2 are summarized in Table 2.1. Drain Modulation DPA VGA Quadrature upconverter Gilbert cells Table 2.1 Summary of architectures POLAR TRANSMITTER ARCHITECTURE Limited bandwidth (spectrum growth) Limited bandwidth (spectrum growth) Limited bandwidth (spectrum growth) Nonlinearity issues Nonlinearity issues Nonlinearity issues Mismatch of delay between amplitude and phase path Mismatch of delay between amplitude and phase path Mismatch of delay between amplitude and phase path PHASE MODULATION ARCHITECTURES Wide bandwidth Wide bandwidth Noise and emissions Noise and emissions Supply modulator bandwidth Power combining Filtering requirements Filtering requirements Update rate of VGA PLL Low bandwidth Noise Filtering requirements MIXERLESS POLAR ARCHITECTURE Mixerless polar modulator-based architecture Wide bandwidth Phase noise and emissions No filtering requirements 19

34 2.4 Variable gain amplifier In the VGA, the gain can be set to a required level simply by adjusting the external control voltage settings [36, 37]. The VGAs can operate over a wide frequency range from dc to gigahertz (GHz). VGAs are generally used to control signals exhibiting wide dynamic range of the mobile phone receivers. Depending on the distance between the base-station and the cellular device, the power level of the received signal varies drastically. Therefore, a VGA in a mobile phone receiver can control the level of the signal coming into the device. VGAs are also commonly used to match the level of input signal to full scale input of a device such as Analog-To-Digital converters (ADCs). Apart from a wide range of applications in communication systems, VGAs can be useful in industrial, medical and scientific sectors in measurement equipment. In this work, VGAs are used as an amplitude modulator. Gain Control Port Input Port Output Port Figure 2.3. Variable Gain Amplifier (Analog Devices ADL533). 2

35 There are mainly two types of VGAs, analog and digital and either one can be used based on the type of application. In this thesis work, an analog VGA is used. The gain of the analog VGA (in db) is the linear function of the gain control voltage and can be represented mathematically as, Gain( db) slope ( vctrl intercept ) (2.3) where, vctrl is the gain control voltage, intercept is the gain of the VGA when vctrl is volts and slope is given as db/volt. In this thesis, three VGA evaluation boards from Analog Devices, part number ADL533 are used. Fig. 2.3 shows the picture of the VGA s used while the specifications of ADL533 are given in Table 2.2. Table 2.2 VGA ADL533 Specifications SPECIFICATION Operating frequency Gain range Bandwidth on the gain control pin Control voltage range Linear-in-Db gain control function OIP 3 VALUE 1 MHz to 3GHz 6 db 3 MHz -1.4 V 2 mv/db 31dBm In this Table, one can see that the OIP 3 of the VGA is 31 dbm which results in the P 1dB to be approximately 2 dbm. From this information, we can conclude that the linear operating range of the VGA is from dbm to 1 dbm. During our experimentation, the VGA was operated in this range to avoid its nonlinear behavior. However, as depicted in Fig. 2.5, the AM-AM and AM-PM 21

36 curves show nonlinear characteristics. This is because the baseband signal provided to the gain control pin of the VGA has a variation in its amplitude which leads to an overall nonlinear system Variable gain amplifier as an amplitude modulator VGA can be used as an amplitude modulator as shown in Fig. 2.4, where the gain control input acts as a modulating signal [38, 39]. A CW signal with required frequency and amplitude is fed into the RF input port of the VGA. The modulating signal at the gain control port of the VGA is mapped to voltage based on the slope and the intercept of the VGA. According to this voltage, the gain of the VGA is varied and modulated signal is then attained at the RF output port of the VGA. Mathematically, it can be represented as [38, 39], V t v t e (2.4) 2 ( ) Re ( ) j ft in in j 2 ft Vout ( t) Re m vin ( t) e (2.5) m v () t s (2.6) c where, v c (t) and s are the gain control signal and sensitivity of the VGA, respectively, while V in (t) and V out (t) are the complex RF signals at the input and output of the VGA, respectively. Gain Control Local Oscillator VGA Amplitude Modulated RF Signal Figure 2.4. VGA as an amplitude modulator. 22

37 Envelope information can be expressed in terms of in-phase and quadrature (IQ) signals by the equation, 2 2 env I Q (2.7) Therefore, mapping from envelope to gain control voltage can be represented mathematically as, vctrl 2 alog ( env) b (2.8) 1 where, vctrl is the gain control voltage, env is the envelope signal obtained using (2.7) and the values of constants a and b are obtained from the DC gain response of the VGA Imperfections in VGA For an ideal VGA, the gain of the device varies linearly with the control voltage. As the signal propagates through the amplifier, the phase of the RF signal should remain constant. However, due to the circuit inaccuracy, nonlinearity in phase and gain responses of the VGA are observed. (a) (b) Figure 2.5. Characteristics of VGA: (a) AM-PM, (b) AM-AM 23

38 The nonlinearity in phase and gain responses of the VGA can be seen in Fig. 2.5 and [39]. It depicts that VGA has both Amplitude Modulation to Phase Modulation (AM-PM) and Amplitude Modulation to Amplitude Modulation (AM-AM) responses. Like PAs, VGA too exhibits memory effects [4, 41]. This means that the output of the VGA depends on present and previous input values. Therefore, these nonlinearity and memory effects affect the quality of the RF modulated signal at the output of the VGA. Thus, calibration and modeling of the VGA to mitigate the imperfections is of prime importance VGA calibration As mentioned in the previous section, the VGA exhibits similar memory effects, and nonlinear gain and phase responses to that of a RF PA. Therefore, memory polynomial [42] can be used to model and mitigate these effects. A conventional memory polynomial with positive real coefficients can be represented as, M K mk k 1 (2.9) m K1 y( n) a x( n 1) x( n m) where, a mk is the real predetermined calibration constant. K is the nonlinearity order and M is the memory depth of the memory polynomial. Whereas, x(n) and y(n) represent the input and output envelope signals, respectively. This memory polynomial models the memory effects and nonlinearity of the VGA in a single step. Least squares technique is used to extract the model coefficients [45]. These coefficients are used to model the response of the VGA. Here, input to the forward model is the actual envelope signal and output is the envelope of complex signal captured at the output of the VGA. However, reverse model of the VGA is obtained by swapping the input and the output envelopes with each other. This reverse model can be used to estimate the input of 24

39 the VGA from the output. Therefore, DPD coefficients are extracted through this reverse model coefficients. Hence, the DPD created through a reverse model is also a memory polynomial model. Also, modeling and linearization of the gain response of the VGA using memory polynomial is represented in [38, 39]. The validation was done on the amplitude of the signal where no phase nonlinearity is considered. Performance of the VGA in [39] is authenticated by using an LTE signal sampled at a rate of 3.72 Msamples/s. CW or LO signal is kept at 2.2 GHz and has a power level of -1 dbm. Whereas, LTE signal of 1.4 MHz of bandwidth was used. The Normalized Mean Square Error (NMSE) before and after Digital Predistortion (DPD) was observed to be db and -5.4 db, respectively. Adjacent Channel Leakage Ratio (ACLR) before and after DPD was observed to be dbc and dbc, respectively, while keeping nonlinearity order of 5 and memory depth of 2. The measurement results from [39] shows that the VGA can be used to implement a highly linear amplitude modulator. 2.5 Mixerless three-way amplitude modulator-based transmitter Introduction Another mixerless transmitter topology was developed in [39]. In this work, the baseband IQ signal is translated to RF domain without mixers, frequency up-converters and phase modulator circuits such as phase shifters and PLLs. This new transmitter topology, called The mixerless three-way amplitude modulation-based transmitter, is based upon the decomposition of the complex envelope of the signal into three envelope components using three-coordinate decomposition algorithm. To translate the baseband signal to a carrier frequency, three VGAs act as envelope modulators for the three decomposed components. Since, the transmitter is free from phase modulator circuit, thus, it avoids any issues related to it. 25

40 2.5.2 Three-way decomposition algorithm The original S in1 (IQ) signal can be written in polar format (r, θ 1 ) as re jθ1 where, r is the magnitude and θ 1 is the angle. Equations (2.1) and (2.2) represent r and θ 1, respectively. The three-coordinate decomposition consists of mapping any IQ signal from the two-axis complex plane to a plane of three positive coordinates, where, each axis is 12º/24º shifted from the other axes. To illustrate the concept, an example of a complex point, S in1 (I+jQ), is shown in Fig. 2.6 along with the threecoordinate (x, y, z) plane. For this point, there is a positive value for the x in,1 component, and a positive value for y in,1 component, while the z in,1 component is equal to zero. These three vectors when added result in a vector that represents the complex envelope of the signal. This algorithm also ensures that the components x in,1, y in,1 and z in,1 are non-negative. The x in,1, y in,1 and z in,1 components are further mapped to control voltages by using equation (2.8). Y 12 -θ 1 y in,1 θ 1 r S in1 (I+jQ) 6 x in,1 X Z Figure 2.6. Three coordinate based signal decomposition when Sin1 lies in -12 tridant. 26

41 C ψ c b θ ϕ A a B Figure 2.7. Representation of law of sines. To better comprehend the decomposition algorithm used in [39], consider triangle ABC with length of the sides as a, b and c and angles as θ, ϕ and ψ as shown in Fig As per law of sines, relation between different components can be expressed as, From the above relation, value of a can be obtained as, b a c (2.1) sin( ) sin( ) sin( ) a csin( ) sin( ) (2.11) Therefore, when S in1 lies in tridant 1-12, values of x in,1, y in,1 and z in,1 components in Fig. 2.6 can be represented as, x r sin(12 1) in,1 (2.12) sin(6 ) 1 There is no such word in the English dictionary which refers to one third of a plane. However, in this thesis, tridant is proposed to get a more accurate appellation to refer one third of a plane. Tridant is derived from the Latin prefix tri- and suffix ant- like quadrant, which refers to quarter of a plane. 27

42 y rsin( ) sin(6 ) (2.13) 1 in,1 In this tridant, the value z in,1 is zero. Thus, value of z in,1 can be calculated when θ 1 is greater than 12. Similarly, as seen from Fig. 2.8, values of x in,1, y in,1 and z in,1 components when S in1 lies in tridant are, y r sin(12 ') sin(6 ) 1 in,1 (2.14) z r sin( ') sin(6 ) (2.15) 1 in,1 where, θ 1ʹ = θ The value of x in,1 component is zero in tridant. Y 6 y in,1 S in1 (I+jQ) r θ 1 ' θ 1 X z in,1 Z Figure 2.8. Three coordinate based signal decomposition when Sin1 lies in tridant

43 Likewise, as seen from Fig. 2.9, values of x in,1, y in,1 and z in,1 components when S in1 lies in tridant are, z x r sin( ") sin(6 ) (2.16) 1 in,1 r sin(12 1") in,1 (2.17) sin(6 ) where, θ 1ʹʹ = θ The value of y in,1 component is zero in tridant. Y θ 1 x in,1 z in,1 θ 1 '' r X Z 6 S in1 (I+jQ) Figure 2.9. Three coordinate based signal decomposition when Sin1 lies in tridant Therefore, a complex envelope, S in1 =re jθ1, can be decomposed into three positive real components x in,1, y in,1 and z in,1 with a phase difference of 12º between them as, S x y e z e (2.18) j12 j24 in1 in,1 in,1 in,1 29

44 2.5.3 Architecture of mixerless three-way amplitude modulator based transmitter The high level schematic diagram of the three-way transmitter architecture is shown in Fig The control voltages act as modulating signal to the LO. The LO signal is fed to RF input port of each VGA, while control voltages, namely, X voltage, Y voltage and Z voltage are fed into gain control port of each VGAx, VGAy and VGAz, respectively. To avoid impairments such as gain and phase imbalance and delay misalignment between the three branches, the outputs from each VGA are captured one by one using a Vector Signal Analyzer (VSA). These three outputs, X out, Y out and Z out are then processed and added digitally. The processing and combining operation is implemented in the digital domain to allow for accurate phase rotation of, 12 and 24 for X out, Y out and Z out, respectively, avoiding any phase imbalance. Before combining, the captured signals from the VSA are also aligned in amplitude to avoid any amplitude imbalance and aligned in delay to avoid any delay mismatch. Because of this ideal combining in the digital domain, the measurement results showed excellent linearity performance in [39]. I Q DSP Digital Splitting Z voltage Y voltage X voltage VGA X VSA Signal Alignment Local Oscillator 12 VGA Y VSA Signal Alignment Digital Combining RF Output 24 VGA Z VSA Signal Alignment Figure 2.1. Mixerless three-way transmitter architecture with digital combining. 3

45 Fig shows the block schematic of the transmitter architecture using digital combining along with digital signal processing blocks. As mentioned earlier, the measurement is taken for each branch separately by using only a single DAC. In [39], splitting of LO and combining output from VGAx, VGAy and VGAz are performed digitally as shown in Fig. 2.1 and Fig The author does not use any analog splitter, phase shifter and analog combiners. This is not a practical solution to the problem as the objective is to combine the three signals to generate a RF modulated output in the analog domain. Moreover, the digital combination is ideal and ignores the gain and phase imbalance and delay misalignment impairments that exist in practical implementations. I in Q in Decomposition,12,24 Phase Mapping Φ x,φ y,φ z Decomposition + Φ x 12 + Φ y 24 + Φ z Filtering and Compensation xe jφx ye jφy ze jφz VGAx DPD VGAy DPD VGAz DPD x y z Voltage Mapping Local Oscillator DAC V x,y,z VGA x/y/z I in_x/y/z Q in_x/y/z I out Q out Digital Combining S out = x+ye j12 +ze j24 Time Delay Adjustment and Phase Compensation I out_x/y/z Q out_x/y/z VSA (Agilent E444A) Digital Demodulator ADC Frequency Down-convertor Figure Block schematic of mixerless three-way amplitude modulator-based transmitter, digital combining architecture with signal processing. 31

46 2.5.4 Calibration Technique As explained in previous section, VGA exhibits nonlinear gain response and memory effects. To model the nonlinear gain response and memory effects exhibited by the VGA, author uses a conventional memory polynomial [39] for each of the three branches, which can be represented as, M K k 1 mk in,1 in,1 (2.19) m k1 y( n) a x ( n m) x ( n m) where, a mk is the complex model coefficient that can be predetermined from a training signal. K is the nonlinearity order and M is the memory depth of the memory polynomial model. y(n) represents the output signal while x in,1 (n) represents the input signals of the VGA. To model the nonlinearity and memory effects of the VGA, a conventional memory polynomial can be used. A training sequence of 1, samples is used to extract model coefficients. Least squares technique is employed to extract these coefficients [45]. Therefore, by using the original input signal and extracted coefficients, the complex output signal is estimated. To evaluate the performance of the model, the measured output signal of the VGA is compared with the estimated output signal using the NMSE metric. Linearization of the system is achieved by generating reverse model. To obtain the reverse model of the VGA the input and output signals are swapped. Thus, for the reverse model, the input is complex and has both the magnitude and phase information, while the output is real and has only the magnitude component. This predistortion technique, which uses three digital predistorters to model and mitigate the nonlinear amplitude and phase response of the three VGAs, requires to have the information of the input as well as the output of each VGA, which is not feasible in practical implementation when the signals are combined in analog. Moreover, as seen from Fig (b) the input signal to the 32

47 forward model has real values while the measured output signal is complex. To obtain the reverse model of the single VGA the input and output signals are swapped. x Input DUT x'e jφx Output (a) x Forward Model x'e jφx est (b) x'e jφx Reverse Model x est (c) xe jφx Predistorter x'' VGA (d) Output Figure Approximation employed in linearization technique [39]. Thus, as seen from Fig (c) input to the reverse model is complex and output is real and has only the magnitude component. Since the input to the predistorter block should be complex, therefore the x, y and z component is multiplied with the measured phase error of VGAx, VGAy and VGAz, respectively as shown in Fig (d). This complex signal is multiplied with the reverse model coefficients. At the output of the predistorter block, ideally we should obtain a real valued signal. However, there is some residual phase present. This residual phase is approximated to zero and only magnitude is considered, since the modulating signal can only have real values. 33

48 Due to this approximation, small portion of the phase information of the input signal is lost. Therefore, the modeling approach results in limited accuracy Implementation of transmitter architecture Fig shows the implementation of mixerless three-way amplitude modulator based transmitter carried out in [39], where the combining of the three branches are done using an ideal phase splitting and signal combining blocks in the digital domain. In this setup, the three VGAs are operated separately. The three voltages are generated in MATLAB and fed to the gain control pin of the VGAs one after the other. LO is given to the RF input port of the VGAs. The RF output of each VGA is captured separately using power spectrum analyzer and digitized using VSA software. Time alignment is carried out distinctly on each branch using maximum correlation technique. Finally, phase rotation and the power combining operations are performed in digital domain. DSP Data In (x in /y in /z in ) Data Out (x out /y out /z out ) V x/y/z ESG 4438C ADL 533 VSA E44A ESG 4438C (Local Oscillator) Figure Mixerless three-way amplitude modulator-based transmitter implementation. 34

49 2.5.6 Measurement results To validate the proposed transmitter architecture and calibration technique, the author in [39] uses an LTE signal with Quadrature Phase Shift Keying (QPSK) constellation. The signal is oversampled by the factor of 16 and the baseband signal consists of 1, samples. This complex signal is decomposed into three gain control voltages. The LO frequency is set to 2.2 GHz with power level of -5 dbm. The measurement results are summarized in Table 2.3. Measurement results show that the calibration technique works well for the tested architecture. However, the test has been done with an ideal combiner implemented digitally without considering any gain and phase imbalance nor any delay misalignment distortions found in a more realistic implementation. Table 2.3 Summary of performance evaluation SPECIFICATION VALUE Signal bandwidth NMSE before digital predistortion NMSE after digital predistortion ACLR before digital predistortion ACLR after digital predistortion 1.4 MHz db db 3.83 dbc dbc This thesis takes the work done in [39] closer to realistic implementation by including the hardware implementation of the analog combing and splitting circuits, which are performed in analog domain. New forward modeling and digital predistortion approaches are also proposed, which mitigates the amplitude responses of all the three VGA s in a single step in addition to the distortions introduced by the analog combiner, splitter, and phase shifters. 35

50 2.6 Conclusion In this chapter, the state-of-the-art research work on polar transmitters is summarized. A comparison of the different polar architectures, their advantages and drawbacks are given in this chapter. Also, the need of a mixerless frequency up-converter that is more suitable for integration and reconfigurability is vindicated. Techniques highlighting state-of-the-art attempts to propose solutions for these needs using mixerless three way architectures are reviewed profoundly. It was concluded that a more realistic implementation that considers imbalance and delay misalignment impairments is needed along with a single step modeling algorithm to consider not only the amplitude modulators nonlinearity but also the analog combining impairments as well. 36

51 Chapter Three: Forward Behavioral Modeling 3.1 Introduction In the previous chapter, key components of mixerless three-way amplitude modulator-based transmitter and the disadvantages associated with the linearization of a non-realistic implementation of this topology using digital power splitting and combining were detailed. In this chapter, along with a complete implementation of a wideband mixerless three-way amplitude modulator-based transmitter ranging from 5 MHz to 3 GHz, integrated with all passive components, a new model, Triadic Complex Memory Polynomial (TC-MP) is proposed to mimic the magnitude and phase non-linearities introduced in all the three branches by three VGAs in a single block. The performance of the modified memory polynomial is tested using Long Term Evolution (LTE) signal of 1.4 MHz bandwidth. I Q DSP Z voltage Y voltage X voltage VGA X Local Oscillator Analog splitter Analog Phase shifter (12 ) VGA Y Analog Combiner RF Output PA Analog Phase shifter (24 ) VGA Z Figure 3.1. High level block schematic of mixerless three-way amplitude modulator based transmitter with analog combining and splitting. High level block diagram of three-way mixerless amplitude modulator based transmitter with analog combining and splitting is shown in Fig As seen from the figure, power amplifier (PA) 37

52 will be required to amplify the RF signal produced at the output of the mixerless transmitter. However, impairments introduced by PA are not included in this work as the aim is to model and mitigate the impairments introduced by the three-way amplitude modulator based system. A lot of work exists on PA s impairment modeling and the analysis of the three-way amplitude based transmitter s modeling, including the PA s nonlinear effects, is straight forward. Multi-standard signals are subject to various distortions when passed through different stages of the transmitter due to the imperfections in the various components of the transmitter. Several block-based behavioral models such as Wiener Hammerstein, Augmented Weiner, Augmented Hammerstein, and Memory Polynomial (MP) were proposed for modeling the nonlinear distortions in the transmitters [46-52]. These methods, however, do not consider the impairments introduced by the modulator such as In-Phase/Quadrature (I/Q) imbalance and Direct Current (DC) offset and only lessen the nonlinear distortions introduced by Power Amplifiers (PAs). In literature, several models such as Volterra series based model, Neural Networks based model, and variations of memory polynomial models have been proposed to successfully model and alleviate the impairments introduced by the modulator and the PA [53-58]. However, in this thesis, a new TC-MP is proposed for modeling of all the three VGA s amplitude and phase response in a single step. 3.2 Extended three-way signal decomposition algorithm As discussed in section 2.5.2, any complex point with a magnitude r and an angle θ 1 can be decomposed into x in,1, y in,1 and z in,1 components. Thus, a complex envelope of a signal is represented by the addition of three vectors that are obtained by out phasing x in,1, y in,1 and z in,1 components by, 12 and 24, respectively. The aim of extended three-way decomposition 38

53 algorithm is to express x in,1, y in,1 and z in,1 as functions of S in1, S in1 e j12 and S in1 e j24 to further help us in generating a black box model for modeling and mitigation of the mixerless transmitter impairments. Also, to simplify the equations, S in1, S in1 e j12 and S in1 e j24 are represented as S 1, S 2 and S 3, respectively. Here, S 1 can be represented in polar format as re jθ1, S 2 can be represented in polar format as re jθ2 while S 3 can be represented in polar format as re jθ3. From section 2.5.2, we can identify the values of x in,1, y in,1 and z in,1 when S 1 lies in -12, and 24-36, respectively. The values of S 1 are summarized in Table 3.1. Table 3.1 Expressions for xin,1, yin,1 and zin,1 when S1 lies in three different tridants x r sin( 1") xin,1 xin,1 sin(6 ) sin(6 ) r sin(12 1) in,1 S1 (Sin1) y rsin( ) sin(6 ) 1 in,1 y r sin(12 ') sin(6 ) 1 in,1 yin,1 zin,1 z r sin( ') sin(6 ) 1 in,1 z r sin(12 1") in,1 sin(6 ) The aim is to find the expressions for S 2 (x in,2, y in,2 and z in,2 ) and S 3 (x in,3, y in,3 and z in,3 ) when S1 lies in -12 tridant as shown in Fig 3.2. Deriving these expressions will further assist us to derive the expressions for x in,1, y in,1 and z in,1 as functions of S 1, S 2 and S 3. From Table 3.1 we can derive the expressions for S 2 and S 3 in -12. Since all the expressions are in linear combination, thus, x in,2, y in,2 and z in,2 in -12 will be identical to x in,1, y in,1 and z in,1 in Thus, x in,2, y in,2 and z in,2 in -12 can be represented as, 39

54 y rsin(12 ') sin6 2 in,2 (3.1) z r sin( ') sin 6 (3.2) 2 in,2 As we can see from Table 3.1, expression for x in,1 in is thus expression for x in,2 in - 12 will be. Y S 2 (S in1 e j12 ) y in,1 S 1 (S in1 ) θ 3 θ 2 r θ 1 6 x in,1 X Z S 3 (S in1 e j24 ) Figure 3.2. Expressing a point, Sin1 in -12. From Fig. 3.2, we observe that θ 2 = θ As mentioned in chapter two expressions for θ 1ʹ = θ Similarly, θ 2ʹ can be written as θ 2ʹ = θ Therefore, θ 2ʹ = θ 1. Hence, equations (3.1) and (3.2) can be written in terms of θ 1. Henceforth, x in,2, y in,2 and z in,2 in -12 are depicted in Table 3.2. Similarly, since all the expressions are in linear combination, thus, x in,3, y in,3 and z in,3 in -12 will be identical to x in,1, y in,1 and z in,1 in Thus, x in,3, y in,3 and z in,3 in -12 can be represented as, 4

55 z x rsin( ") sin(6 ) (3.3) 3 in,3 r sin(12 3") in,3 (3.4) sin(6 ) As seen from Table 3.1, expression for y in,1 in is, thus, the expression for y in,3 in - 12 will also be. From Fig. 3.2, we can observe that θ 3 = θ We know that θ 1ʹʹ = θ Similarly, θ 3ʹʹ can be written as θ 3ʹʹ = θ Therefore, θ 3ʹʹ = θ 1. Hence, equations (3.3) and (3.4) can be written in terms of θ 1. Henceforth, x in,3, y in,3 and z in,3 in -12 are depicted in Table 3.2. Likewise, expressions can be derived for S 2 and S 3 in and when S 1 lies in and 24-36, respectively. All the expressions for S 1, S 2 and S 3 are depicted in Table

56 Table 3.2 Expressions for S1, S2 and S3 in three different tridants x r sin(12 1) in,1 x in,1 = sin(6 ) x r sin( ") sin(6 ) 1 in,1 S1 (Sin1) y rsin( ) sin(6 ) 1 in,1 y r sin(12 ') sin(6 ) 1 in,1 y in,1 = z in,1 = z r sin( ') sin(6 ) 1 in,1 z r sin(12 1") in,1 sin(6 ) x in,2 = x rsin( ') sin(6 ) 1 in,2 x r sin(12 1") in,2 sin(6 ) S2 (Sin1e j12 ) y r sin(12 1) in,2 y in,2 = sin(6 ) y rsin( '') sin(6 ) 1 in,2 z rsin( ) sin(6 ) 1 in,2 z r sin(12 ') sin(6 ) 1 in,2 z in,2 = x rsin( ) sin(6 ) 1 in,3 x r sin(12 ') sin(6 ) 1 in,3 x in,3 = S3 (Sin1e 24 ) y in,3 = y rsin( ') sin(6 ) 1 in,3 y r sin(12 1 '') sin(6 ) in,3 z r sin(12 1) in,3 z in,3 = sin(6 ) z r sin( ") sin(6 ) 1 in,3 42

57 3.2.1 Expressions for xin,1, yin,1 and zin,1 as a function of S1, S2 and S3 when Sin1 lies in -12. Consider a point S in1 (I+jQ) in -12 tridant as shown in Fig As mentioned earlier, our aim is to decompose a point S in1 into x in,1, y in,1 and z in,1 components as functions of S 1, S 2 and S 3. Thus, x in,1, y in,1 and z in,1 components can be written as functions of S 1, S 2 and S 3 as, xin,1 a1s1 b1s 2 c1s 3 (3.5) yin,1 a2s1 b2s 2 c2s3 (3.6) zin,1 a3s1 b3s 2 c3s3 (3.7) where, a 1, b 1, c 1, a 2, b 2, c 2, a 3, b 3 and c 3 are constants which needs to be derived. Let us consider equation (3.5) and find out the values for a 1, b 1 and c 1. Component xin,1 can be derived by summing all the components corresponding to S 1, S 2 and S 3 in -12. The expressions for x in,1, y in,1, z in,1, x in,2, y in,2, z in,2, x in,3, y in,3 and z in,3 in -12 are characterized in Table 3.2. Summing these components can be represented as, a1r sin(12 1) c1r sin( 1) xin,1 sin(6 ) sin(6 ) a1r sin( 1) b1r sin(12 1) a1s1 b1s 2 c1s 3 yin,1 sin(6 ) sin(6 ) b1r sin( 1) c1r sin(12 1) zin,1 sin(6 ) sin(6 ) (3.8) Since there are three constants and three equations, we need to set any one constant to 1. For the time being let a 1 equals to 1. Hereby, to find the value of component x in,1, equate components y in,1 and z in,1 to. By setting components y in,1 and z in,1 to and a 1 to 1, the values of constants b 1 and c 1 can be calculated as, 43

58 sin( ) b sin( 12 ) c sin ( 1) sin ( 12 ) (3.9) (3.1) Henceforth, to compensate for the assumption of setting a 1 to 1, let us consider another constant α which can be represented as, x xin,1( 12 ) in,1 c1 xin,3 ( 12 ) ( 12 ) (3.11) where components x in,1 ( -12 ) and x in,3 ( -12 ) are represented in Table 3.2, while c 1 is represented in equation (3.1). The expression for α can be represented as, sin ( 12 ) sin ( 12 ) sin ( ) (3.12) Therefore, expression of α is multiplied with a 1, b 1 and c 1 to get new constants A 1, B 1 and C 1, respectively. These constants can be represented as, 3 sin ( 1 12 ) A B C sin ( 12 ) sin ( ) 2 sin ( 112 )sin( 1) sin ( 12 ) sin ( ) sin( 12 )sin ( ) sin ( 12 ) sin ( ) (3.13) (3.14) (3.15) Hence, component x in,1 can be characterized as, xin,1 A1 S1 B1S 2 C1S3 (3.16) 44

59 Similarly, expression for component yin,1 can be estimated by summing all the components corresponding to S 1, S 2 and S 3 in -12. New constants are considered to avoid confusion. Let these constants be a 2, b 2 and c 2. The expressions for x in,1, y in,1, z in,1, x in,2, y in,2, z in,2, x in,3, y in,3 and z in,3 in -12 are characterized in Table 3.2. Summing these components can be represented as, x a b c y z a r sin(12 ) c r sin( ) sin(6 ) sin(6 ) a r sin( ) b r sin(12 ) sin(6 ) sin(6 ) b r sin( ) c r sin(12 ) sin(6 ) sin(6 ) in, S1 2 S2 2 S3 in, in,1 (3.17) Again, for the time being let b 2 equals to 1. Hereby, to find the value of component y in1, equate components x in,1 and z in,1 to. By setting components x in,1 and z in,1 to and b 2 to 1, the values of constants a 2 and c 2 can be calculated as, a 2 sin ( 1) c sin ( 12 ) sin( ) sin( 12 ) (3.18) (3.19) Henceforth, to compensate for the assumption of setting b 2 to 1, let us consider another constant β which can be represented as, y yin,1( 12 ) in,2 a2 yin,1 ( 12 ) ( 12 ) (3.2) where components y in,1 ( -12 ) and y in,2 ( -12 ) are represented in Table 3.2, while a 2 is represented in equation (3.18). The expression for β can be represented as, 45

60 sin ( 12 )sin( ) sin ( 12 ) sin ( ) (3.21) Therefore, expression of β is multiplied with a 2, b 2 and c 2 to get new constants A 2, B 2 and C 2, respectively. These constants can be represented as, A B C 3 sin ( 1) sin ( 12 ) sin ( ) 2 sin ( 112 )sin( 1) sin ( 12 ) sin ( ) sin( 12 )sin ( ) sin ( 12 ) sin ( ) (3.22) (3.23) (3.24) Therefore, y in,1 can be characterized as, yin,1 A2 S1 B2S2 C2S3 (3.25) The expression of component zin,1 in -12 tridant is. Hence, the values of constants A 3, B 3 and C 3 are also Expressions for xin,1, yin,1 and zin,1 as a function of S1, S2 and S3 when Sin1 lies in Consider a point S in1 (I+jQ) in tridant as shown in Fig The components x in,1, y in,1 and z in,1 can be represented as, xin,1 A4 S1 B4S2 C4S3 (3.26) yin,1 A5 S1 B5S 2 C5S3 (3.27) zin,1 A6 S1 B6S 2 C6S3 (3.28) 46

61 Z S 2 (S in1 e j12 ) z in,1 S 1 (S in1 ) θ 3 θ 2 r θ 1 y in,1 6 Y X S 3 (S in1 e j24 ) Figure 3.3. Expressing a point, Sin1 in The expressions for x in,1 is when S 1 (S in1 ) lies in Therefore, values of A 4, B 4 and C 4 correspond to. Whereas, expressions for A 5, B 5, C 5, A 6, B 6 and C 6 can directly be derived from A 1, B 1, C 1, A 2, B 2 and C 2. From Table 3.2, we can see that expression for x in,1 in -12 correspond to expression for y in,1 in Also, expression for y in,1 in -12 correspond to expression for z in,1 in From Fig. 3.3 we can see that S 1, S 2 and S 3 lies in 12-24, and -12, respectively. Then constants A 1, B 1, C 1 will correspond to constants C 5, A 5 and B 5, respectively. Similarly, constants A 2, B 2, C 2 will correspond to constants C 6, A 6 and B 6, respectively. Therefore, A 5, B 5, C 5, A 6, B 6 and C 6 can be expressed in terms of θ 1ʹ as, A 2 sin ( 1' 12 )sin( 1') sin ( ' 12 ) sin ( ') (3.29) 47

62 B C A B C sin( ' 12 )sin ( ') sin ( ' 12 ) sin ( ') sin ( 1 ' 12 ) sin ( ' 12 ) sin ( ') 2 sin ( 1' 12 )sin( 1') sin ( ' 12 ) sin ( ') sin( ' 12 )sin ( ') sin ( ' 12 ) sin ( ') sin ( 1 ') sin ( ' 12 ) sin ( ') (3.3) (3.31) (3.32) (3.33) (3.34) where, θ 1ʹ= θ By substituting this value of θ 1ʹ in above equations, new expression for A 5, B 5, C 5, A 6, B 6 and C 6 are derived and represented in Table 3.3. X S 2 (S in1 e j12 ) x in,1 S 1 (S in1 ) θ 3 θ 2 r θ 1 z in,1 6 Z Y S 3 (S in1 e j24 ) Figure 3.4. Expressing a point, Sin1 in

63 3.2.3 Expressions for xin,1, yin,1 and zin,1 as a function of S1, S2 and S3 when Sin1 lies in Consider a point S in1 (I+jQ) in tridant as shown in Fig The components x in,1, y in,1 and z in,1 can be represented as, xin,1 A7 S1 B7S 2 C7S3 (3.35) yin,1 A8 S1 B8S 2 C8S3 (3.36) zin,1 A9 S1 B9S 2 C9S3 (3.37) Similarly, the expression for y in,1 is when S 1 (S in1 ) lies in Therefore, values of A 8, B 8 and C 8 correspond to. Similar to section 3.2.2, expressions for A 7, B 7, C 7, A 9, B 9 and C 9 can directly be derived from A 1, B 1, C 1, A 2, B 2 and C 2. These expressions can be represented as, A B C A B C sin( '' 12 )sin ( '') sin ( '' 12 ) sin ( '') sin ( 1 '') sin ( '' 12 ) sin ( '') 2 sin ( 1'' 12 )sin( 1'') sin ( '' 12 ) sin ( '') sin( '' 12 )sin ( '') sin ( '' 12 ) sin ( '') sin ( 1 '' 12 ) sin ( '' 12 ) sin ( '') sin ( '' 12 )sin( '') sin ( '' 12 ) sin ( '') (3.38) (3.39) (3.4) (3.41) (3.42) (3.43) where, θ 1ʹʹ= θ By substituting this value of θ 1ʹʹ in above equations, new expression for A 7, B 7, C 7, A 9, B 9 and C 9 are derived and represented in Table

64 Table 3.3 Expressions of constants in different tridants VALUES OF CONSTANTS IN DIFFERENT TRIDANTS Values of Constants when S in1 lies in sin ( 1 12 ) A B C sin ( 12 ) sin ( ) 2 sin ( 112 )sin( 1) sin ( 12 ) sin ( ) sin( 12 )sin ( ) sin ( 12 ) sin ( ) A B C 3 sin ( 1) sin ( 12 ) sin ( ) 2 sin ( 112 )sin( 1) sin ( 12 ) sin ( ) sin( 12 )sin ( ) sin ( 12 ) sin ( ) A3 B3 C3 Values of Constants when S in1 lies in A4 A 2 sin ( 1 24 )sin( 112 ) sin ( 24 ) sin ( 12 ) A 2 sin ( 1 24 )sin( 112 ) sin ( 24 ) sin ( 12 ) B4 C4 B C sin( 24 )sin ( 12 ) sin ( 24 ) sin ( 12 ) sin ( 1 24 ) sin ( 24 ) sin ( 12 ) B C sin( 24 )sin ( 12 ) sin ( 24 ) sin ( 12 ) sin ( 1 12 ) sin ( 24 ) sin ( 12 ) Values of Constants when S in1 lies in A sin( 36 )sin ( 24 ) sin ( 36 ) sin ( 24 ) A8 A sin( 36 )sin ( 24 ) sin ( 36 ) sin ( 24 ) B 3 sin ( 1 24 ) sin ( 36 ) sin ( 24 ) B8 B 3 sin ( 1 36 ) sin ( 36 ) sin ( 24 ) C 2 sin ( 1 36 )sin( 1 24 ) sin ( 36 ) sin ( 24 ) C8 C 2 sin ( 1 36 )sin( 1 24 ) sin ( 36 ) sin ( 24 ) 5

65 3.3 Forward model for mixerless three-way amplitude modulator-based transmitter As discussed in chapter two, the three-way transmitter architecture consists of three VGAs. Each VGA has a gain and phase response, which needs to be modeled accurately. Moreover, there are some limitations associated with the model proposed in [39] for e.g., the use of digital combining does not compensate for gain and phase imbalance. Furthermore, the residual phase in the modeling technique utilizes approximation to get real signals at the output of each DPD. In contrast, the proposed one-box model, the TC-MP, accounts for the above-mentioned limitations. Briefly, the proposed model compensates for the gain and phase imbalance and accounts for all the types of distortions in the mixerless three-way amplitude modulator-based transmitter without making any approximations Mathematical analysis for -12 We know, that the output of a single VGAx, VGAy and VGAz can be accurately modeled with a memory polynomial in the following manner [39], K M out k, m in,1 k (3.44) k1 m x h ( x ( n m)) K M out k, m in,1 k (3.45) k1 m y h ( y ( n m)) K M out k, m in,1 k (3.46) k1 m z h ( z ( n m)) where, h k,m is the complex model coefficients. x out, y out and z out are the outputs of the VGAx, VGAy and VGAz, respectively. While, x in,1, y in,1 and z in,1 components are the inputs to the model. K and 51

66 M are nonlinearity order and memory depth, respectively. From the previous section, we can conclude that the value of x in,1, y in,1 and z in,1 components, in -12 tridant can be represented as, j12 j24 in,1 1 in1 1 in1 1 in1 o x A S B S e C S e (3.47) y A S B S e C S e (3.48) j12 j24 in,1 2 in1 2 in1 2 in1 z A S B S e C S e (3.49) j12 j24 in,1 3 in1 3 in1 3 in1 where, A 1, B 1, C 1, A 2, B 2, C 2, A 3, B 3 and C 3 are the constants whose values can be occupied from Table 3.3 and S in1 is the complex input signal. For simplicity, in further equations, values of S in1, S in1 e j12 and S in1 e j24 are replaced by S 1, S 2 and S 3, respectively. Values of x in,1, y in,1 and z in,1 are applied in equation (3.44), (3.45) and (3.46), respectively. The resultant equations are then subjected to binomial theorem and can be represented as, K M x h A B C S S S x i1 i2 i3 i1 i2 i3, (3.5) out k m i i i k1 mi i i k K M y h A B C S S S y i1 i2 i3 i1 i2 i3, (3.51) out k m i i i k1 mi i i k K M z h A B C S S S z i1 i2 i3 i1 i2 i3, (3.52) out k m i i i k1 mi i i k Value of S out can be derived by substituting values of x out, y out and z out in equation (2.18) and can be represented as, x i1 i2 i3 H k, m, i1i 2i A 3 1 B1 C1 K M y i1 i2 i3 j12 i1 i2 i3 k, m, i1i 2i (3.53) Sout H A B C e S S S k1 mi1 i2 i3 k z i1 i2 i3 j24 H k, m, i1i 2i A 3 3 B3 C3 e 52

67 x y where, H k,m,i1 i 2 i 3, H k,m,i1 i 2 i 3 α i1 i 2 i 3, β i1 i 2 i 3 and γ i1 i 2 i 3, respectively. z and H k,m,i1 i 2 i 3 are the complex model coefficients which incorporates As seen from Table 3.3, we know that B 1 =-B 2 and C 1 =-C 2, while values of A 1 and A 2 are distinct. We also know that values of A 3, B 3 and C 3 are for this tridant. Therefore, equation (3.53) can be represented as, K M i2 i3 x i1 i2 i3 i1 12 i1 i2 i3 1 1,, ( 1) y j,, (3.54) S B C H A H A e S S S out k m i i i k m i i i k1 mi i i k Now, by substituting the vales of A 1, A 2, B 1 and C 1 from Table 3.3, Sout D S S S x i2 2i3 3i1 2i2 i3 K M H k, m, i1i 2i sin ( 3 1)sin ( 1 12 ) k i1 i2 i3 (3.55) 1 k y 3i i2 2i3 2i2 i3 j12 k1 mi1 i2 i3 k ( 1) Hk, m, i sin ( 1i2i 3 1)sin ( 1 12 ) e where, D 1 represents the denominator in -12, and can be represented as, D sin ( 12 ) sin ( ) (3.56) Ultimately, the modified memory polynomial for º-12º can be deduced as, K M j1 j2 sin ( 1)sin ( 112 ) k k m j1 j (3.57) k S ( n) G' S ( n m) out,,, in1 k1 m j j 3k (sin ( 112 ) sin ( 1)) 1 2 x where, G k,m,j1, j 2 are the complex predetermined model coefficients which incorporates H k,m,i1 i 2 i 3, y H k,m,i1 i 2 i 3, constants and all the phase rotations. S in1 (n) and S out (n) are the complex input and output signals, respectively. M is the memory depth and K is the nonlinearity order of the modified memory polynomial. 53

68 3.3.2 Mathematical analysis for Similarly, for 12º-24º, the forward behavioral model can be derived. In this tridant value of S out can be represented as, x y where, H k,m,i1 i 2 i 3, H k,m,i1 i 2 i 3 x i1 i2 i3 H k, m, i1i 2i A 3 4 B4 C4 K M y i1 i2 i3 j12 i1 i2 i3 k, m, i1i 2i (3.58) Sout H A B C e S S S k1 mi1 i2 i3 k z i1 i2 i3 j24 H k, m, i1i 2i A 3 6 B6 C6 e α i1 i 2 i 3, β i1 i 2 i 3 and γ i1 i 2 i 3, respectively. z and H k,m,i1 i 2 i 3 are the complex model coefficients which incorporates For this tridant, we know that A 5 =-A 6 and B 5 =-B 6, while values of C 5 and C 6 are distinct. We also know that values of A 4, B 4 and C 4 are for this tridant. Therefore, equation (3.58) can be represented as, K M i1 i2 y i3 j 12 i1 i2 i3 24 i1 i2 i3 5 5,, ( 1) z j,, (3.59) S A B H C e H C e S S S out k m i i i k m i i i k1 mi i i k Now, by substituting the vales of A 5, B 5, C 5 and C 6 from Table 3.3, y 2i1 i2 3i3 i1 2i2 j12 K M Hk, m, i1i 2i sin ( )sin ( 1 12 ) e k i1 i2 i3 Sout D 2 S 1 S2 S3 k z 2i1 i2 i1 2i2 3i3 j24 k1 mi1 i2 i3 k ( 1) Hk, m, i sin ( 1i2i )sin ( 1 12 ) e (3.6) where, D 2 represents the denominator in 12-24, and can be represented as, D sin ( 24 ) sin ( 12 ) (3.61) Ultimately, the modified memory polynomial for 12º-24º can be deduced as, K M j1 j2 sin ( 112 )sin ( 124 ) k,, 1, in1 (3.62) S ( n) G'' S ( n m) out k m j j k k1 m j j 3k (sin ( 1 24 ) sin ( 112 ))

69 where, G k,m,j1, j 2 are the complex predetermined model coefficients which incorporates H k,m,i1 i 2 i 3, z H k,m,i1 i 2 i 3, all the constants and phase rotations. S in1 (n) and S out (n) are the complex input and output signals, respectively. M is the memory depth and K is the nonlinearity order of the modified memory polynomial. y Mathematical analysis for Similarly, for 24-36º, the forward behavioral model can be derived. In this tridant value of S out can be represented as, x y where, H k,m,i1 i 2 i 3, H k,m,i1 i 2 i 3 x i1 i2 i3 H k, m, i1i 2i A 3 7 B7 C7 K M y i1 i2 i3 j12 i1 i2 i3 k, m, i1i 2i (3.63) Sout H A B C e S S S k1 mi1 i2 i3 k z i1 i2 i3 j24 H k, m, i1i 2i A 3 9 B9 C9 e α i1 i 2 i 3, β i1 i 2 i 3 and γ i1 i 2 i 3, respectively. z and H k,m,i1 i 2 i 3 are the complex model coefficients which incorporates For this tridant, we know that A 9 =-A 7 and C 9 =-C 7, while values of B 7 and B 9 are distinct. We also know that values of A 8, B 8 and C 8 are for this tridant. Therefore, equation (3.63) can be represented as, K M i1 i3 x i2 i1 i3 i2 24 i1 i2 i3 9 9,, ( 1) z j,, (3.64) S A C H B H B e S S S out k m i i i k m i i i k1 mi i i k Now, by substituting the vales of B 7, A 9, B 9 and C 9 from Table 3.3, Sout D S S S x 2i1 3i2 i3 i1 2i3 k K M H k, m, i1i 2i sin ( )sin ( 1 36 )( 1) k i1 i2 i3 (3.65) 3 z 2i i3 i1 3i2 2i3 j24 k1 mi1 i2 i3 k Hk, m, i sin ( 1i2i )sin ( 1 36 ) e where, D 3 represents the denominator in 24-36, and can be represented as, 55

70 D sin ( 36 ) sin ( 24 ) (3.66) Ultimately, the modified memory polynomial for 24º-36º can be deduced as, K M j1 j2 sin ( 124 )sin ( 136 ) k,, 1, in1 (3.67) S ( n) G''' S ( n m) out k m j j k k1 m j j 3k (sin ( 1 36 ) sin ( 1 24 )) 1 2 x where, G k,m,j1,j 2 are the complex predetermined model coefficients which incorporates H k,m,i1 i 2 i 3, z H k,m,i1 i 2 i 3, all the constants and phase rotations. S in1 (n) and S out (n) are the complex input and output signals, respectively. As mentioned earlier, M is the memory depth and K is the nonlinearity order of the modified memory polynomial. The number of coefficients required to generate this model can be given by: N t (K (M + 1) (3K + 1)) where N t is the number of tridants. In our case, as there are three tridants N t = 3, K is 3 and M is 2. This leads to the total number of coefficients being 27. DSP Local Oscillator I in Q in x Decomposition + Φ y Voltage x V VGA Decomposition x y 12 Mapping DAC,12,24 Phase + Φ y Mapping 24 + Φ z z 12 o Φ x,φ y,φ z Filtering and V DAC z VGA y Compensation DAC V x o 24 o VGA z S out I est Q est Forward Model I out_ta Q out_ta Time Delay Adjustment I out Q out VSA (Agilent E444A) Digital Demodulator ADC Frequency Down-convertor Figure 3.5. Block schematic of mixerless three-way amplitude modulator-based transmitter, analog combining architecture with signal processing. 56

71 Fig. 3.5 shows the block schematic of the transmitter architecture using analog combining along with the digital signal processing blocks. Training sequence of 1k samples is used to extract the coefficients using least square technique [45]. Coefficients are then applied to the whole input sequence of 1k samples to estimate the output. The normalized mean square error (NMSE) between estimated and measured output is calculated to evaluate the performance of the model. The NMSE is calculated by using equation (1.5). 3.4 Model Extraction Algorithm This section describes the steps involved in the calibration technique adopted for modeling all the impairments of mixerless three-way amplitude modulator based transmitter. The triadic complex memory polynomial mentioned in equation (3.57) for tridant -12 can be written as, t t S S G' (3.68) 1 1 out in 1 t Where S 1 in1 can be represented in matrix form as, S j1 j2 j1 j2 j1 j2 sin ( 1)sin ( 1 12 ) 1 sin ( 1)sin ( 1 12 ) 1 sin ( 1)sin ( 1 12 ) K S 1 in1( n)... S 1 in1( n m) Sin 1( n m) K D1 D1 D 1 j1 j2 j1 j2 j1 j2 sin ( 1)sin ( 1 12 ) 1 sin ( 1)sin ( 1 12 ) 1 sin ( 1)sin ( 112 ) K S 1 in1( n 1)... S 1 in1( n 1 m) Sin 1( n 1 m) K D1 D1 1 t D in j1 j2 j1 j2 j1 j2 sin ( 1)sin ( 1 12 ) 1 sin ( 1)sin ( 1 12 ) 1 sin ( 1)sin ( 1 12 ) K S 1 in1( n L)... S 1 in1( n L m) Sin 1( n L m) K D1 D1 D 1 (3.69) t Here, S 1 in1 refers to the input samples and L refers to the training length. t Coefficient vector, Gʹ and output matrix S 1 out for -12 can be represented as, ' G... G G G (3.7) 1,, j, j 1, M, j, j K, M, j, j T 57

72 S t 1 S ( n )... S ( n 1) S ( n L ) T (3.71) out out out out t Similarly, S 2 in1 for t tridant and S 3 in1 matrix for tridant can be obtained. After obtaining Sin1 matrix for each tridant, the general expression for the complete triadic complex memory polynomial can be written as, This equation can be represented in matrix form as, S = S G (3.72) out in1 t1 t1 S out Sin1 G' t 2 t2 S out = S in1 G'' t 3 t 3 Sout Sin1 G''' (3.73) Using the Least Squares Estimation technique, the coefficient vector G is obtained as, G S S (3.74) LS in1 out where, S in1 is the Moore-Penrose pseudoinverse of Sin1. The coefficients thus obtained is multiplied with the complete input signal as shown in equation (3.73) to get estimated output, S out,est S S G (3.75) out,est in1 LS This estimated output is then compared to actual or measured output to evaluate the model performance. 3.5 Implementation of mixerless three-way amplitude modulator-based transmitter The Mixerless three-way amplitude modulator based transmitter is implemented using three analog VGAs (ADL533). The specifications of ADL533 are given in Table 2.2. The evaluation of all 58

73 the three boards are depicted in Fig All the VGAs are powered by a 5V DC supply. Advanced Design System (ADS) is used to generate complex baseband I/Q data. This complex baseband I/Q signal is decomposed into three envelopes using three-coordinate decomposition algorithm and then mapped to control voltages in MATLAB as described earlier. The three control voltages are then downloaded to two different signal generators (ESG4438C) as each signal generator has only two baseband outputs. Therefore, one signal generator (ESG-1) is used for generation of control voltages V x and V y while the second signal generator (ESG-2) is used for generation of control voltage V z. Both signal generators are operated in synchronization. Another signal generator (ESG4438C) is used as a Local Oscillator (LO). The signal generators and the LO are triggered in synchronization. The analog gain control voltage V x at the analog baseband output of ESG-1 is fed to the gain control pin of VGAx. Similar procedure is used for VGAy and VGAz respectively. The LO signal is fed to the input of a three-way power-divider (MACOM PN ) which has loss of 7dB in each of the three branches and has frequency range from.5 GHz to 18 GHz. The LO at the first output port of the power-divider is fed to the RF input port of VGAx. The LO at the second output port of the power-divider is fed to a first phase shifter (ARRA 9428A) with frequency range from DC-18 GHz, which rotates the LO by 12º. The output is then fed to the RF input port of VGAy. The LO at the third output port of the power-divider is fed to a second phase shifter (ARRA 9428A) which rotates the LO by 24º. The output of the second phase shifter is fed to RF input port of VGAz. Finally, the RF outputs X out, Y out and Z out are summed together using power-combiner (MACOM PN ) to obtain the desired complex modulated RF signal, which is captured and digitized using Power Spectrum Analyzer (PSA E444A) and VSA software, respectively. The time alignment is carried out using maximum correlation technique [59]. To retrieve I/Q data from the captured signal, further signal processing is carried out in 59

74 MATLAB. Fig. 3.7 depicts the hardware implementation of mixerless three-way amplitude modulator-based transmitter. Figure 3.6. Implementation of mixerless three-way amplitude modulator-based transmitter. Figure 3.7. Hardware implementation of the mixerless three-way amplitude modulatorbased transmitter. 6

75 3.6 Measurement results A LTE signal of 1.4 MHz bandwidth and Quadrature Phase Shift Keying (QPSK) constellation is generated using ADS software to validate the proposed modeling technique and to evaluate the performance of the proposed methodology. The LTE signal is oversampled by a factor of 16 and the corresponding baseband signal has 1, samples which are sampled at a rate of 3.72 Msamples/sec. The complex baseband signal is then subjected to decomposition to a threecoordinate system according to the three-way decomposition algorithm discussed earlier in this chapter. Components obtained after decomposition and digital processing are then mapped to control voltages and fed to the experimental setup described in the previous section. An LO signal is generated at 2.2 GHz with a power level of -3 db to feed the three VGA paths. The signal is captured by a power spectrum analyzer and demodulated by VSA software followed by time alignment algorithm implemented in MATLAB. Table 3.4 Summary of performance for digital combining and proposed analog combining SPECIFICATION IDEAL DIGITAL COMBINING PROPOSED ANALOG COMBINING Signal bandwidth 1.4 MHz 1.4 MHz Number of testing samples 1, 1, Number of training samples 1, 1, Testing NMSE db db Training NMSE db db Nonlinearity order and Memory depth K=3, M=2 K=3, M=2 61

76 After capturing the output signal (measured signal) the derived TC-MP is used to estimate the output signal (estimated signal). The input to the TC-MP model is original complex baseband I/Q signal and output is the complex signal captured from the output of the transmitter. After obtaining the required input and output signals, model identification is performed to acquire the modeling coefficients and finally the modeled output. NMSE is then calculated between modeled output and measured output signals. The summary of results of the performance evaluation of the tree-way mixerless amplitude modulator based transmitter with ideal digital combining and the implemented topology with analog combining is depicted in Table 3.4. These results show that the proposed TC-MP model can replace the three MP models used in [39] to include the nonlinear distortion and memory effects of each branch. In addition, this model considers any gain and phase imbalance between the three different paths generated by the non-ideal analog combiner. (a) (b) Figure 3.8. Characteristics of modeled and measured output signals for digital combining architecture: (a) AM-PM, (b) AM-AM 62

77 To validate the proposed model, in addition to the NMSE results, the AM-PM and AM-AM of the modelled output and the measured output signals for the three-way transmitter implemented with digital combining are demonstrated in Fig. 3.8 and the AM-PM and AM-AM of the modelled output and measured output signals for the three-way transmitter implemented with analog combining are shown in Fig The proposed TC-MP model can predict the full transmitter behavior including nonlinearity and imbalance between the branches. (a) (b) Figure 3.9. Characteristics of modeled and measured output signals for analog combining architecture: (a) AM-PM, (b) AM-AM Moreover, the spectral representations of the modeled output, the measured output, and the error signal for the three-way transmitter with digital combing and the three-way transmitter with analog combining are shown in Fig. 3.1 and Fig. 3.11, respectively. From the graphs, we can conclude that the proposed forward model works exceptionally well for the three-way transmitter architecture whether the combining is ideal or implemented in analog. The spectra of the error 63

78 signals prove that in both cases, the out-of-band (nonlinear) and in-band (linear and nonlinear) distortions are all modeled accurately. Figure 3.1. Spectral response of modeled and measured output along with error signal for the three-way transmitter implementation with digital combining. Figure Spectral response of modeled and measured output along with error signal for the three-way transmitter implementation with analog combining. 64

79 3.7 Conclusion In this chapter, mixerless three-way amplitude modulator-based transmitter ranging from 5 MHz to 3 GHz is implemented completely using of-the-shelf RF components. Along with the implementation, a novel TC-MP forward model is proposed to model the characteristics of the three-way transmitter architecture and is validated using laboratory measurements. Since all the branches are implemented and modeled simultaneously as a one-box system, the proposed model considers the amplitude and phase imbalances between different branches. Furthermore, the performance of the proposed model, evaluated in terms of various figures of merits, shows the excellent modeling capability. 65

80 Chapter Four: Reverse Behavioral Modeling 4.1 Introduction Variable Gain Amplifiers (VGAs) used in the mixerless three-way transmitter topology introduce nonlinear Amplitude to Amplitude (AM-AM) and Amplitude to Phase (AM-PM) distortions as shown in chapter two. Digital Predistortion (DPD) is an effective technique to compensate for the nonlinear effects. Mitigation of nonlinear effects exhibited by VGAs in the mixerless three-way amplitude modulator based transmitter is challenging because till now no general theory that defines the relationship between the system s input and output for such a topology exists [6]. In addition, the unconventional signal decomposition prevents conventional predistortion algorithms from performing accurately, especially in the presence of gain and phase imbalance. VGAs are the primary source of nonlinear distortion in the mixerless three-way transmitter topology. In general, nonlinearities result in distortions which include adjacent channels interference caused by the intermodulation distortion that generates spectral regrowth [61], and distortion of signal s constellation or Error Vector Magnitude (EVM) degradation [62]. To avoid these unwanted effects, DPD is widely used in literature to linearize power amplifiers and radio frequency (RF) transmitters [6-63]. A digital predistorter is a functional block that precedes a nonlinear Device Under Test (DUT), which in our case is the parallel combination of three VGAs. A digital predistortor exhibits an inverse nonlinear response to that of the DUT. Digital predistorter learning architectures for pre-inverse model identification can be classified into direct learning and indirect learning architectures [63]. Direct learning means that the relation between input and output of the DUT is estimated, and the predistortion is obtained directly by pre-inverting the DUT characteristics [63]. Indirect learning means that a postdistorter first derives a post-inverse of the DUT without placing any predistorter in the forward path. The postdistorter computes the 66

81 ` coefficients of the post-inverse model of the nonlinear DUT and copies them to the predistorter with the aim of linearizing the system. In this thesis, digital predistorter based on indirect learning architecture is used. Fig. 4.1 shows the Digital Signal Processing (DSP) block of mixerless three-way transmitter and the principle of implementation and operation of the DPD part, which is based on indirect learning. Initially, the digital predistorter block is absent as explained earlier. The signal S in1 is decomposed into x in,1, y in,1 and z in,1 components along the, 12 and 24 axes using three-way decomposition algorithm as explained in earlier. An offset value is added to the components to ensure non-zero values. Then, the components are subjected to digital filtering to avoid any discontinuities. Finally, the x in,1, y in,1 and z in,1 components are mapped to generate control voltages for the VGA. The inputs generated is then downloaded into the signal generators, which have built-in digital-to-analog converters (DACs) and then fed to the gain control pins of the VGAs. The RF output from all the three VGAs is then summed together to acquire S out. DUT Decomposition (,12,24 ) x in1 DACx Vx VGAx S in1 (n) Digital Predistorter S dpd Filtering y in1 Voltage Mapping DACy Vy VGAy S out (n) _ e(n) Compensation z in1 DACz Vz VGAz + g(n) Postdistorter Figure 4.1. Block schematic for the operation of digital predistorter based on indirect learning. 67

82 As shown in Fig. 4.1, the postdistorter block first computes the post-inverse of the DUT by identifying the post-inverse modeling coefficients. These coefficients are then copied to the predistortion block placed before the DUT. The coefficients are updated after each iteration to linearize the transmitter system. 4.2 Digital predistortion (DPD) Fig. 4.2 shows the working of DPD technique to linearize the mixerless transmitter architecture. S in1 Input DUT S out Output (a) S in1 Forward Model S' out (b) S out Reverse Model S' in1 (c) Sin1 Postdistorter S dpd DUT (d) Output Figure 4.2. Predistortion and linearization. Fig. 4.2 (a) shows that S in1 acts as the complex input signal to the three-way mixerless transmitter architecture and S out acts as the complex output signal. Moreover, as seen from Fig 4.2 (b) for forward modeling, when the input complex signal S in1 acts as the input to the model then the output signal is estimated as Sʹout. The input and output signals are swapped to obtain the reverse model as explained and proved earlier. Thus, for the reverse model, as shown in Fig. 4.2 (c), when the 68

83 input is S out then the output is estimated as Sʹin1. To generate a predistorted (postdistorted in this case) signal, the reverse model coefficients are multiplied with the input signal as shown in Fig. 4.2 (d) which is then passed to the DUT after the three-way decomposition algorithm to obtain the linearized signal. 4.3 Reverse model for mixerless three-way amplitude modulator-based transmitter The nonlinear gain and phase responses of the VGAs and their corresponding memory effects can be modeled using a TC-MP as shown in chapter three. The following section proves that the TC- MP model can be successfully used for predistorting the mixerless three-way amplitude modulator-based transmitter Triadic complex memory polynomial calibration In this section, the aim is to obtain a reverse model by swapping the input and output signals. We know that a conventional memory polynomial of nonlinearity order K and memory depth M, can accurately model the nonlinearity and other imperfections of the VGA [38, 39]. Moreover, the same memory polynomial can also be used to mitigate these imperfections [38, 39]. Consider a forward model of mixerless transmitter as shown in Fig The conventional memory polynomial model for VGAx, VGAy and VGAz can be represented as, K M k out k, m in1 k1 m (4.1) x ( n) h x ( n m) K M k out k, m in1 k1 m (4.2) y ( n) h y ( n m) 69

84 K M k out k, m in1 k1 m (4.3) z ( n) h z ( n m) where, h k,m is the real predetermined calibration constant. M is the memory depth and K is the nonlinearity order of the memory polynomial. x in,1, y in,1 and z in,1 are the input envelopes to VGAx, VGAy and VGAz respectively. While, x out, y out and z out are output signals of VGAx, VGAy and VGAz, respectively. T -1 T x in,1 VGAx f 1 (x) x out e j S in1 Signal Decomposition y in,1 VGAy f 2 (y) y out e j12 S out T-Transfer Function T -1 - Inverse transfer function z in,1 VGAz f 3 (z) z out e j24 Figure 4.3. Forward model of the mixerless three-way amplitude modulator-based transmitter. From Fig. 4.3, it can be observed that if signal decomposition block is represented by transfer function T, then the block characterized with dashed line can be represented by T -1 as its function is opposite to that of signal decomposition block. The relation between decomposed input components (x in,1, y in,1 and z in,1 ) and output signal (S out ), can be mathematically represented as, S x y z (4.4) 1 out T f 1 ( in,1),f 2 ( in,1),f 3 ( in,1) 7