Dr. S Intekhab Amin Ph.D (Electronics and Communication Engg.) Mobile :

Transcription

1 Dr. S Intekhab Amin Ph.D (Electronics and Communication Engg.) Mobile : samin@jmi.ac.in intekhabamin@gmail.com SUMMARY [ Ph.D in Semiconductor Device Design, Modeling and Simulation (E &C Engg.). M.Tech.-Electronics Circuit & System Design (Electronics Engg.), Graduate- Electronics & Communication Engineering with R&D Experience in Satellite System Design in IIT-Madras & 2 years of teaching Experience.] Research Area: Research Interest: His research area includes Device modeling, Design and Simulation of silicon and III-V based Semiconductor Devices viz. Junctionless MOSFET, TFET, TFT, Ferroelectric Devices, Device modeling for sensor application, Digital VLSI Circuits and System Design, Analog Circuits and System Design, Reconfigurable FPGA implementations. Experience Worked as Assistant Professor in Manav Rachna College of Engineering for 2 Years ( ). Worked as a Project Associate in Satellite System Design at IIT-Madras ( ). Qualification Ph.D (2017) : Electronics and Communication Engineering N.I.T Jalandhar Post Graduation (2009) : M.Tech (Electronics Circuit and System Design) Z.H.C.E.T, A.M.U, Aligarh. 1 st Divn, 74% Graduation (2006) : Electronics & Communication Engineering The Institution of Engineers (India). 1 st Divn, 64.74% Research Publications. 1. S. Intekhab Amin and R.K.Sarin, Analog Performance Investigation of Gate misaligned Double gate Junctionless Transistor, J. of Computational Electronics, Springer, vol. 14, Issue 3, pp , Sep

2 2. S. Intekhab Amin and R.K.Sarin, Direct Tunneling Gate Current Model for Symmetric Double Gate Junctionless Transistor With SiO 2 / High-k Gate stacked Dielectric, J. of Semicond., IOP science, vol.37, issue 2, pp , Feb S. Intekhab Amin and R.K.Sarin, The Impact of Gate Misalignment on Analog Performance of Dual-Material Double Gate Junctionless Transistor, J. of Semiconductors, IOP science, vol. 36, issue. 9, pp , Sep S. Intekhab Amin and R.K.Sarin, Gate Misalignment Analysis of Dual-Material Double Gate Junctionless Transistor, J. of Nanoengineering and Nanomanufacturing, ASP, vol. 5, pp. 1-5, S. Intekhab. Amin, and R.K. Sarin, Charge-Plasma Based Dual-Material and Gate-Stacked Architecture of Junctionless Transistor for Enhanced Analog Performance, Superlattices and Microstructures, Elsevier, vol. 88, pp , Oct S. Intekhab. Amin, and R.K. Sarin, Enhanced Analog Performance of Charge Plasma Based Dual Material and Gate Stacked Architecture of Junctionless Transistor With High-k Spacer, Applied Physics A, Springer, vol. 122, pp , Mar S. Intekhab Amin and R.K. Sarin, Channel Grading Technique for improved Tolerance To Gate Misaligned Double Gate Junctionless Transistor, J. of Compt. Int. And Elect. Syst, ASP, vol. 4, pp. 1-7, S. Intekhab. Amin, Sunny Anand, and R.K. Sarin, Charge Plasma Based Dual Material and Gate Stacked Architecture of Junctionless Transistor A Performance Analysis, IEEE conf. UPCON 2016, IIT BHU. 9. S.Intekhab Amin and R.K.Sarin, Junctionless Transistor: A review CIIT 2013 Mumbai, IET Dig. Lib., pp , Oct Sunny Anand, S Intekhab Amin, and R.K.Sarin, Performance analysis of charge plasma based Dual Electrode Tunnel FET, J. of Semiconductors, IOP Science, vol.37, issue 3, Mar

3 11. Sunny Anand, S Intekhab Amin, and R.K.Sarin, Analog Performance Investigation of Charge Plasma Based Dual Electrode Tunnel FET. J. of Comput. Electron., Springer, vol. 15, issue 1, pp , Mar Gurmeet Singh, S.Intekhab Amin, Sunny Anand, and R. K. Sarin, Design of Si 0.5 Ge 0.5 Based Tunnel Field Effect Transistor and its Performance Evaluation, Superlattice and Microstructure, Elsevier, vol. 92, pp , Apr Bhuwan Chandra joshi, S Intekhab Amin and R.K.sarin, Analysis of GIDL and Impact Ionization Writing Methods in 100nm SOI ZDRAM, Journal of Electron Devices, vol. 20, pp , Dec S.Intekhab Amin and M.Shah Alam, Use of TCAD Tool for the fabrication of sub-40nm bulk MOSFET and its performance investigation, National conference on VLSI,MEMS and NEMS VMN 2010, Sept Sunny Anand, S. Intekhab Amin, and R.K.Sarin, Performance Analysis of Different Material Based Dual Electrode Doping-less TFET, in Europian Advanced Material Congress Sweden, Aug Book. 1. S Intekhab Amin and M.Shah Alam, Novel Nanoscale MOSFET with TCAD, Lambert Academic Publishing, ISBN: Seminar/Workshop:- Multimedia and its Applications Others Advances in wireless Networks Emerging Trend of Research in Electronics and Communication Electronics and Communication System Design Aspects, May 2015 INUP Familiarization Workshop Nanofabrication Technology Recent Trends in Instrumentration and Control Engineering Medal Signal Processing and its Interpretation Workshop on Multimedia and its Applications Held All India rank 2 nd in section examination S N Ghosh memorial prize and Institution prize Qualified GATE in 2007

4 Software Skills Electronic Design Package : Silvaco TCAD TOOL,ADS, Xilinx ISE, ModelSIM, Programming Language Microwind & DSCH2.6c, LT-Spice, ORCAD : VerilogHDL, VHDL,C, Assembly Language (MCS51 & ADSP 2191),Pspice. FPGA/CPLD/Microcontroller: Xilinx FPGAs (Spartan3, Spartan3E, Virtex4) Subjects Area Micro& Nano Electronics Semiconductor Devices. Digital and Analog Integrated Circuit Design Digital System Design. VLSI Technology and Design Embedded System Design Ph.D Thesis Work: Title:- Device Design Considerations and Performance Analysis of Multiple Gate Junctionless Transistor. The performance analysis of junctionless Transistor is performed under gate misaligned condition and fixed its tolerance limit to provide best device performance Analytically studied impact of gate leakage current and its reduction for junctionless transsitor. Gate engineered design of junctionless transistor are analyzed under gate misaligned condition to provide its tolerance limit. Proposed new design to enhance the performance of junctionless transistor. M. Tech Dissertation:- Organization:- AICTE Project on Design and Modeling of Nano-Scale SOI MOSFET. Title:- Use Of TCAD Tool for The Fabrication of Nano-Scale Bulk MOSFET and its Performance Investigation Tool:- Athena(Virtual Fabrication) & Atlas(Device Simulation), ADS. A 40nm Bulk MOSFET Fabrication process is carried out under channel engineering and source drain engineering process. These structures enable more aggressive device scaling in nano-scale region because of their ability to control short channel effects. How ever

5 during scaling the junction depth should also be scaled down, which increases parasitic resistance so silicidation technique has been applied to reduce their effects on device. Analog performance has been measured in terms of gm, gds,av,f T and f max and a comparison of an engineered device is done with a non engineered device to investigate the improved performance of an engineered device as compared to a non engineered device. Professional Training:- Undergone Professional Development program on VLSI Design from Sandeepani School of VLSI Design Project Work:- VGA Controller:- Title :-Development of an RTL module for 3-bit VGA interface controller and demonstrate color spectrum and moving geometrical object and debugging and monitoring using Chip Scope Pro on 640 x 480 VGA display using Spartan 3 kit. Develop an RTL module to support buffering of multiple image data in BMP file format and verifying the design by using file IO operation in testbench by writing image data to the DUT.Using a FIFO with suitable parameters from Xilinx CORGEN. FSL Core :- Title :- Design of RTL module for an FSL core with data loopback. Verify and design by writing an image data to the input side of FSL bus and read the image data from the output side of FSL bus. The custom logic in the FSL core will be enabled by control data at the input side. Validation of FSL core in the imbedded test platform Project Work :- Title :- Development of an RTL module for UART transmitter and receiver and by using 8 X 32 FIFO and transmitter write logic as an interface to transceiver and debugging and monitoring using Chip Scope Pro on FPGA Spartan 3 kit. Project Work ( ):- Organization:-Centre for Industrial Consultancy and Sponsored Research(IC & SR), IIT-Madras. Title: Sparse Area Communication System (SACS), Design of Satellite System.

6 Tested one of the Remote Terminal (RT) at ISRO (SAC) to pass voice and data between RT at which was installed at ISRO and the Hub at IIT-M tested successfully with data rate at 128kbps. RF Testing of Satellite System when using signal generator and to compare it with actual transmitted signal through Hub terminal. Testing of FEC Card for the vocoder to boot properly and bit error rate (BER) testing for better constellation of QPSK signal Work on SPORTS & DMA configuration of Analog Processors ADSP(2191) on Modem which is the integral part of Hub and Remote terminal. Played a major role in Research & Development and for single channel as well as for Multi Channel Tx and Rx for Remote and Hub. Personal Detail:- Name : Dr. S Intekhab Amin Father : S Amin Ahmed Address : Road no. 12, Malik Colony, New Karimgunj, Gaya, Bihar, , India Mobile no : samin@jmi.ac.in, intekhabamin@gmail.com