ML610Q438/ML610Q439 GENERAL DESCRIPTION FEATURES. FEDL610Q439-3 Issue Date: Jun 7, 2011

Transcription

1 8-bit Microcontroller with a Built-in LCD driver Issue Date: Jun 7, 20 GENERAL DESCRIPTION This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I 2 C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nx-u8/00. The CPU nx-u8/00 is capable of efficient instruction execution in -instruction -clock mode by 3-stage pipe line architecture parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask ROM and is most suitable for battery-driven applications. The on-chip debug function that is installed enables program debugging and programming. FEATURES CPU 8-bit RISC CPU (CPU name: nx-u8/00) Instruction system: 6-bit instructions Instruction set: On-Chip debug function Minimum instruction execution time 30.5 s (@ khz system clock) s (@4.096 MHz system clock) Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on Internal memory Internal 28KByte Flash ROM (64K 6 bits) (including unusable KByte TEST area) Internal 6KByte Data RAM (644 8 bits), KByte Display Allocation RAM (024 x 8bit) Internal 92-byte RAM for display Interrupt controller 2 non-maskable interrupt sources (Internal source:, External source: ) 27 maskable interrupt sources (Internal sources: 9, External sources: 8) Time base counter Low-speed time base counter channel Frequency compensation (Compensation range: Approx. 488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) High-speed time base counter channel Watchdog timer Non-maskable interrupt and reset Free running Overflow period: 4 types selectable (25ms, 500ms, 2s, and 8s) Timers 8 bits 4 channels (6-bit configuration available) khz timer 0 Hz/ Hz interrupt function /36

2 Capture Time base capture 2 channels (4096 Hz to 32 Hz) PWM Resolution 6 bits 3 channel Synchronous serial port Master/slave selectable LSB first/msb first selectable 8-bit length/6-bit length selectable Timer interrupt is used as a serial clock and selection is possible UART TXD/RXD channel Bit length, parity/no parity, odd parity/even parity, stop bit/2 stop bits Positive logic/negative logic selectable Built-in baud rate generator I 2 C bus interface Master function only Fast mode (400 kbps@4mhz), standard mode (00 kbps@mhz, 50kbps@500kHz) Melody driver Scale: 29 types (Melody sound frequency: 508 Hz to khz) Tone length: 63 types Tempo: 5 types Buzzer output mode (4 output modes, 8 frequencies, 6 duty levels) RC oscillation type A/D converter 24-bit counter Time division 2 channels Successive approximation type A/D converter 2-bit A/D converter Input 2 channels General-purpose ports Non-maskable interrupt input port channel Input-only port 0 channels (including secondary functions) Output-only port 3 channels (including secondary functions) Input/output port 20 channels (including secondary functions) LCD driver Dot matrix can be supported. ML60Q438: 344 dots max. (56 seg 24 com) ML60Q439: 024 dots max. (64 seg 6 com) / to /24 duty /3 or /4 bias (built-in bias generation circuit) Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 02 Hz) Bias voltage multiplying clock selectable (8 types) Contrast adjustment (/3 bias: 32 steps, /4 bias: 20 steps) LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable Programmable display allocation function (available only when /~/8 duty is selected) The metal option of only ML60Q439 Type B : 6com x 64seg (seg63 to seg0: segment port) Type C : 6com x 56seg (seg63 to seg56: output port seg55 to seg0: segment port) Type D : 6com x 48seg (seg63 to seg48: output port seg47 to seg0: segment port) 2/36

3 Type E : 6com x 40seg (seg63 to seg40: output port seg39 to seg0: segment port) Type F : 6com x 32seg (seg63 to seg32: output port seg3 to seg0: segment port) Reset Reset through the RESET_N pin Power-on reset generation when powered on Reset when oscillation stop of the low-speed clock is detected Reset by the watchdog timer (WDT) overflow Power supply voltage detect function Judgment voltages: One of 6 levels Judgment accuracy: 2% (Typ.) Clock Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock) Crystal oscillation ( khz) High-speed clock: Built-in RC oscillation (2M/500kHz) Built-in PLL oscillation (8.92 MHz 2.5%), crystal/ceramic oscillation (4.096 MHz), external clock Selection of high-speed clock mode by software: Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock Power management HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) Clock gear: The frequency of high-speed system clock can be changed by software (/, /2, /4, or /8 of the oscillation clock) Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. Shipment Chip (Die) ML60Q438-xxxWA (Blank product: ML60Q438-NNNWA) ML60Q438P-xxxWA (Blank product: ML60Q438P-NNNWA) ML60Q439-xxxWA (Blank product: ML60Q439-NNNWA) ML60Q439P-xxxWA (Blank product: ML60Q439P-NNNWA) 44-pin plastic LQFP ML60Q438-xxxTCZ03A (Blank product: ML60Q438-NNNTCZ03A) ML60Q438P-xxxTCZ03A (Blank product: ML60Q438P-NNNTCZ03A) ML60Q439-xxxTCZ03A (Blank product: ML60Q439-NNNTCZ03A) ML60Q439P-xxxTCZ03A (Blank product: ML60Q439P-NNNTCZ03A) xxx: ROM code number Guaranteed operating range Operating temperature: 20 C to 70 C (P version : 40 C to 85 C) Operating voltage: V DD =.V to 3.6V, AV DD = 2.2V to 3.6V 3/36

4 BLOCK DIAGRAM ML60Q438 Block Diagram Figure show the block diagram of the ML60Q438. "*" indicates the secondary function of each port. CPU (nx-u8/00) EPSW~3 PSW GREG 0~5 ELR~3 LR ECSR~3 DSR/CSR Timing Controller On-Chip ICE ALU Instruction Decoder EA SP Instruction Register PC BUS Controller Program Memory (Flash) 28Kbyte V PP V DD V SS RESET_N TEST XT0 XT OSC0* OSC* LSCLK* OUTCLK* V DDL V DDX IN0* CS0* RS0* RT0* CRT0* RCM* IN* CS* RS* RT* RESET & TEST OSC Power RC-ADC 2 4 Data-bus RAM 644byte Interrupt Controller WDT TBC khztc Capture 2 4 8bit Timer SSIO UART I 2 C PWM 3 Melody GPIO SCK0* SIN0* SOUT0* RXD0* TXD0* SDA* SCL* PWM0* to PWM2* MD0* NMI P00 to P03 P0 to P P20 to P22 P30 to P35 P40 to P47 AV DD AV SS V REF AIN0, AIN 2bit-ADC BLD Display Allocation RAM KByte Display RAM 92Byte LCD Driver LCD BIAS COM0 to COM23 SEG0 to SEG55 V L, V L2, V L3, V L4 C, C2, C3, C4 Figure ML60Q438 Block Diagram 4/36

5 ML60Q439 Block Diagram Figure 2 show the block diagram of the ML60Q439. "*" indicates the secondary function of each port. CPU (nx-u8/00) EPSW~3 PSW GREG 0~5 ELR~3 LR ECSR~3 DSR/CSR Timing Controller On-Chip ICE ALU Instruction Decoder EA SP Instruction Register PC BUS Controller Program Memory (Flash) 28Kbyte V PP V DD V SS RESET_N TEST XT0 XT OSC0* OSC* LSCLK* OUTCLK* V DDL V DDX IN0* CS0* RS0* RT0* CRT0* RCM* IN* CS* RS* RT* RESET & TEST OSC Power RC-ADC 2 4 Data-bus RAM 644byte Interrupt Controller WDT TBC khztc Capture 2 4 8bit Timer SSIO UART I 2 C PWM 3 Melody GPIO SCK0* SIN0* SOUT0* RXD0* TXD0* SDA* SCL* PWM0* to PWM2* MD0* NMI P00 to P03 P0 to P P20 to P22 P30 to P35 P40 to P47 AV DD AV SS V REF AIN0, AIN 2bit-ADC BLD Display Allocation RAM KByte Display RAM 92Byte LCD Driver LCD BIAS COM0 to COM5 SEG0 to SEG63 V L, V L2, V L3, V L4 C, C2, C3, C4 Figure 2 ML60Q439 Block Diagram 5/36

6 LAPIS Semiconductor 6/36 PIN CONFIGURATION ML60Q438 LQFP44 Pin Layout (NC): No Connection Figure 3 ML60Q438 LQFP44 Pin Configuration P06 P05 P04 PA5 PA4 PA3 PA2 PA PA0 COM8 COM9 COM0 COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM20 COM2 COM22 COM23 SEG55 SEG54 SEG53 SEG52 SEG5 AVDD (NC) AIN AIN0 VSS P07 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG4 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG3 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG2 SEG20 SEG9 SEG8 SEG7 (NC) SEG6 V REF AV SS V SS P20 P2 P22 P40 P4 V PP RESET_N P44 P45 P46 P47 P30 P3 P34 P32 P33 P35 TEST V DD V DDL V SS V DDX XT0 (NC) XT P42 P43 V L V L2 V L3 V L4 C C2 C3 C4 pin 44pin 72pin 73pin 36pin 37pin 08pin 09pin L60Q438 P00/EXI0 P0/EXI P02/EXI2 P03/EXI3 NMI VSS P0 (NC) P VDD COM0 COM COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG0 SEG SEG2 SEG3 SEG4 SEG5

7 LAPIS Semiconductor 7/36 ML60Q439 LQFP44 Pin Layout (NC): No Connection Figure 4 ML60Q439 LQFP44 Pin Configuration P06 P05 P04 PA5 PA4 PA3 PA2 PA PA0 COM8 COM9 COM0 COM COM2 COM3 COM4 COM5 SEG63 SEG62 SEG6 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG5 AVDD (NC) AIN AIN0 VSS P07 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG4 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG3 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG2 SEG20 SEG9 SEG8 SEG7 (NC) SEG6 V REF AV SS V SS P20 P2 P22 P40 P4 V PP RESET_N P44 P45 P46 P47 P30 P3 P34 P32 P33 P35 TEST V DD V DDL V SS V DDX XT0 (NC) XT P42 P43 V L V L2 V L3 V L4 C C2 C3 C4 pin 44pin 72pin 73pin 36pin 37pin 08pin 09pin L60Q439 P00/EXI0 P0/EXI P02/EXI2 P03/EXI3 NMI VSS P0 (NC) P VDD COM0 COM COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG0 SEG SEG2 SEG3 SEG4 SEG5

8 ML60Q438 Chip Pin Layout & Dimension AVDD AIN AIN0 VSS P07 P06 P05 P04 PA5 PA4 PA3 PA2 PA PA0 COM8 COM9 COM0 COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM20 COM2 COM22 COM23 SEG55 SEG54 SEG53 SEG52 SEG5 VREF SEG50 AVSS SEG49 VSS SEG48 P SEG47 P SEG46 P22 65 SEG45 P SEG44 P SEG43 VPP 4 62 SEG42 RESET_N 5 6 SEG4 P SEG40 P SEG39 P SEG38 P SEG37 P SEG36 P SEG35 P SEG34 P SEG33 P SEG32 P SEG3 TEST SEG30 VDD SEG29 VDDL SEG28 VSS SEG27 VDDX SEG26 XT SEG25 XT SEG24 P SEG23 P SEG22 VL 35 4 SEG2 VL SEG20 VL SEG9 VL SEG8 C SEG7 C SEG6 3.46m C3 C4 P00/EXI P0/EXI P02/EXI P03/EXI NMI VSS P0 P VDD COM0 COM COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG0 SEG SEG2 SEG3 SEG4 SEG mm Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 3.5 mm 3.46 mm 40 pins 80 m 80 m 80 m 350 m V SS level Figure 5 ML60Q438 Chip Layout & Dimension 8/36

9 ML60Q439 Chip Pin Layout & Dimension AVDD AIN AIN0 VSS P07 P06 P05 P04 PA5 PA4 PA3 PA2 PA PA0 COM8 COM9 COM0 COM COM2 COM3 COM4 COM SEG63 SEG62 SEG6 SEG60 SEG59 SEG58 SEG57 SEG SEG55 SEG54 SEG53 SEG52 SEG5 VREF SEG50 AVSS SEG49 VSS SEG48 P SEG47 P SEG46 P22 65 SEG45 P SEG44 P SEG43 VPP 4 62 SEG42 RESET_N 5 6 SEG4 P SEG40 P SEG39 P SEG38 P SEG37 P SEG36 P SEG35 P SEG34 P SEG33 P SEG32 P SEG3 TEST SEG30 VDD SEG29 VDDL SEG28 VSS SEG27 VDDX SEG26 XT SEG25 XT SEG24 P SEG23 P SEG22 VL 35 4 SEG2 VL SEG20 VL SEG9 VL SEG8 C SEG7 C SEG6 3.46mm C3 C4 P00/EXI P0/EXI P02/EXI P03/EXI NMI VSS P0 P VDD COM0 COM COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG0 SEG SEG2 SEG3 SEG4 SEG mm Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 3.5 mm 3.46 mm 40 pins 80 m 80 m 80 m 350 m V SS level Figure 6 ML60Q439 Chip Layout & Dimension 9/36

10 LAPIS Semiconductor ML60Q438 Pad Coordinates PAD No. Pad Name X (μm) Y (μm) Table ML60Q438 Pad Coordinates PAD No. Pad Name X (μm) Y (μm) PAD No. Pad Name Chip Center: X=0,Y=0 C SEG PA C SEG PA P00/EXI SEG PA P0/EXI SEG P P02/EXI2 /RXD0/P2 CK X (μm) Y (μm) SEG P P03/EXI SEG P NMI SEG P VSS SEG VSS P SEG AIN P SEG AIN VDD SEG AVDD COM SEG VREF COM SEG AVSS COM SEG VSS COM SEG P COM SEG P COM SEG P COM SEG P COM SEG P SEG SEG VPP SEG SEG RESET_N SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG COM P SEG COM P SEG COM P SEG COM TEST SEG COM VDD SEG COM VDDL SEG COM VSS SEG COM VDDX SEG COM XT SEG COM XT SEG COM P SEG COM P SEG COM VL SEG COM VL SEG COM VL SEG COM VL SEG PA C SEG PA C SEG PA /36

11 LAPIS Semiconductor ML60Q439 Pad Coordinates PAD No. Pad Name X (μm) Y (μm) Table 2 ML60Q439 Pad Coordinates PAD No. Pad Name X (μm) Y (μm) PAD No. Pad Name Chip Center: X=0,Y=0 C SEG PA C SEG PA P00/EXI SEG PA P0/EXI SEG P P02/EXI2 /RXD0/P2 CK X (μm) Y (μm) SEG P P03/EXI SEG P NMI SEG P VSS SEG VSS P SEG AIN P SEG AIN VDD SEG AVDD COM SEG VREF COM SEG AVSS COM SEG VSS COM SEG P COM SEG P COM SEG P COM SEG P COM SEG P SEG SEG VPP SEG SEG RESET_N SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG SEG P SEG SEG TEST SEG SEG VDD SEG SEG VDDL SEG SEG VSS SEG SEG VDDX SEG COM XT SEG COM XT SEG COM P SEG COM P SEG COM VL SEG COM VL SEG COM VL SEG COM VL SEG PA C SEG PA C SEG PA /36

12 PIN LIST PAD No. Primary function Secondary function Tertiary function Q439 Q438 Pin name I/O Function Pin name I/O Function Pin name I/O Function 8,02, 8,02, Negative power supply 08,2 Vss 08,29 pin 9,27,27 V DD Positive power supply pin Power supply pin for V DDL internal logic (internally generated) V DDX Power supply pin for low-speed oscillation (internally generated) 4 4 V PP Power supply pin for Flash ROM AV SS Negative power supply pin for successive approximation type ADC AV DD Positive power supply pin for successive approximation type ADC V L Power supply pin for LCD bias (internally generated) V L2 Power supply pin for LCD bias (internally generated) V L3 Power supply pin for LCD bias (internally generated) V L4 Power supply pin for LCD bias (internally generated) C Capacitor connection pin for LCD bias generation C2 Capacitor connection pin for LCD bias generation C3 Capacitor connection pin for LCD bias generation 2 2 C4 Capacitor connection pin for LCD bias generation TEST I/O Input/output pin for testing 5 5 RESET_ N I Reset input pin 3 3 XT0 I Low-speed clock oscillation pin XT O Low-speed clock oscillation pin V REF Reference power supply pin for successive approximation type ADC AIN0 I Successive approximation type ADC input 2/36

13 PAD No. Primary function Secondary function Tertiary function Q439 Q438 Pin name I/O Function Pin name I/O Function Pin name I/O Function Successive AIN I approximation type ADC input 7 7 NMI I Non-maskable interrupt pin 3 3 Input port, External P00/EXI0/C I interrupt 0 input, AP0 Capture 0 input 4 4 Input port, External P0/EXI/C I interrupt input, AP Capture input 5 5 P02/EXI2 Input port, External interrupt 2, UART0 /RXD0 I receive, PWM2 external /P2CK clock input 6 6 P03/EXI3 I Input port, External interrupt P04/EXI4 I/O Input port, External interrupt P05/EXI5 I/O Input port, External interrupt P06/EXI6 I/O Input port, External interrupt P07/EXI7 I/O Input port, External interrupt P0 I Input port OSC0 I High-speed oscillation 0 0 P I Input port OSC O High-speed oscillation P20/LED0 O Output port LSCLK O Low-speed clock output PWM2 O PWM2 output 0 0 P2/LED O Output port OUTCLK O High-speed clock output P22/LED2 O Output port MD0 O Melody output P30 I/O Input/output port IN0 I RC type ADC0 oscillation input pin PWM2 O PWM2 output 2 2 P3 I/O Input/output port CS0 O RC type ADC0 reference capacitor connection pin P32 I/O Input/output port RS0 O RC type ADC0 reference resistor connection pin P33 I/O Input/output port RT0 O RC type ADC0 resistor sensor connection pin P34 I/O Input/output port RCT0 O RC type ADC0 resistor/capacitor PWM0 O PWM0 output sensor connection pin P35 I/O Input/output port RCM O RC type ADC oscillation monitor PWM O PWM output 2 2 P40 I/O Input/output port SDA I/O I2C data input/output SIN0 I SSIO data input 3 3 P4 I/O Input/output port SCL I/O I2C clock input/output SCK0 I/O SSIO synchronous clock P42 I/O Input/output port RXD0 I UART data input SOUT0 O SSIO data output P43 I/O Input/output port TXD0 O UART data output PWM0 O PWM0 output P44/T02P0 CK P45/T3P CK P46/T46P2 CK I/O I/O I/O Input/output port, Timer 0/Timer 2/PWM0 external clock input Input/output port, Timer /Timer 3/PWM external clock input Input/output port, PWM2 external clock input IN CS RS I O O RC type ADC oscillation input pin RC type ADC reference capacitor connection pin RC type ADC reference resistor connection pin SIN0 I SSIO0 data input SCK0 I/O SSIO0 synchronous clock SOUT0 O SSIO0 data output 3/36

14 LAPIS Semiconductor PAD No. Primary function Secondary function Tertiary function Q439 Q438 Pin name I/O Function Pin name I/O Function Pin name I/O Function RC type ADC 9 9 P47 I/O Input/output port RT O resistor sensor PWM O PWM output connection pin PA0 I/O Input/output port PA I/O Input/output port PA2 I/O Input/output port PA3 I/O Input/output port PA4 I/O Input/output port PA5 I/O Input/output port 2 2 COM0 O LCD common pin 3 3 COM O LCD common pin 4 4 COM2 O LCD common pin 5 5 COM3 O LCD common pin 6 6 COM4 O LCD common pin 7 7 COM5 O LCD common pin 8 8 COM6 O LCD common pin 9 9 COM7 O LCD common pin 9 9 COM8 O LCD common pin COM9 O LCD common pin COM0 O LCD common pin COM O LCD common pin COM2 O LCD common pin COM3 O LCD common pin COM4 O LCD common pin COM5 O LCD common pin 83 COM6 O LCD common pin 82 COM7 O LCD common pin 8 COM8 O LCD common pin 80 COM9 O LCD common pin 79 COM20 O LCD common pin 78 COM2 O LCD common pin 77 COM22 O LCD common pin 76 COM23 O LCD common pin SEG0 O LCD segment pin 2 2 SEG O LCD segment pin SEG2 O LCD segment pin SEG3 O LCD segment pin SEG4 O LCD segment pin SEG5 O LCD segment pin SEG6 O LCD segment pin SEG7 O LCD segment pin SEG8 O LCD segment pin SEG9 O LCD segment pin SEG0 O LCD segment pin 3 3 SEG O LCD segment pin SEG2 O LCD segment pin SEG3 O LCD segment pin SEG4 O LCD segment pin SEG5 O LCD segment pin SEG6 O LCD segment pin 4/36

15 PAD No. Primary function Secondary function Tertiary function Q439 Q438 Pin name I/O Function Pin name I/O Function Pin name I/O Function SEG7 O LCD segment pin SEG8 O LCD segment pin SEG9 O LCD segment pin SEG20 O LCD segment pin 4 4 SEG2 O LCD segment pin SEG22 O LCD segment pin SEG23 O LCD segment pin SEG24 O LCD segment pin SEG25 O LCD segment pin SEG26 O LCD segment pin SEG27 O LCD segment pin SEG28 O LCD segment pin SEG29 O LCD segment pin SEG30 O LCD segment pin 5 5 SEG3 O LCD segment pin SEG32 O LCD segment pin SEG33 O LCD segment pin SEG34 O LCD segment pin SEG35 O LCD segment pin SEG36 O LCD segment pin SEG37 O LCD segment pin SEG38 O LCD segment pin SEG39 O LCD segment pin SEG40 O LCD segment pin 6 6 SEG4 O LCD segment pin SEG42 O LCD segment pin SEG43 O LCD segment pin SEG44 O LCD segment pin SEG45 O LCD segment pin SEG46 O LCD segment pin SEG47 O LCD segment pin SEG48 O LCD segment pin SEG49 O LCD segment pin SEG50 O LCD segment pin 7 7 SEG5 O LCD segment pin SEG52 O LCD segment pin SEG53 O LCD segment pin SEG54 O LCD segment pin SEG55 O LCD segment pin 76 SEG56 O LCD segment pin 77 SEG57 O LCD segment pin 78 SEG58 O LCD segment pin 79 SEG59 O LCD segment pin 80 SEG60 O LCD segment pin 8 SEG6 O LCD segment pin 82 SEG62 O LCD segment pin 83 SEG63 O LCD segment pin 5/36

16 PIN DESCRIPTION Pin name I/O Description Primary/ Secondary/ Logic Tertiary System RESET_N I Reset input pin. When this pin is set to a L level, system reset mode is Negative set and the internal section is initialized. When this pin is set to a H level subsequently, program execution starts. A pull-up resistor is internally connected. XT0 I Crystal connection pin for low-speed clock. XT O A khz crystal oscillator (see measuring circuit ) is connected to this pin. Capacitors CDL and CGL are connected across this pin and V SS as required. OSC0 I Crystal/ceramic connection pin for high-speed clock. Secondary OSC O A crystal or ceramic is connected to this pin (4. MHz max.). Capacitors CDH and CGH (see measuring circuit ) are connected across this pin and V SS. This pin is used as the secondary function of the P0 pin(osc0) and P pin(osc). Secondary LSCLK O Low-speed clock output pin. This pin is used as the secondary function of Secondary the P20 pin. OUTCLK O High-speed clock output pin. This pin is used as the secondary function of the P2 pin. Secondary General-purpose input port P00-P07 I General-purpose input port. Primary Positive Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P0-P I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. Primary Positive General-purpose output port P20-P22 O General-purpose output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. Primary Positive General-purpose input/output port P30-P35 I/O General-purpose input/output port. Primary Positive Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P40-P47 I/O General-purpose input/output port. Primary Positive Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. PA0-PA5 I/O General-purpose input/output port. Primary Positive UART TXD0 O UART data output pin. This pin is used as the secondary function of the P43 pin. RXD0 I UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. Secondary Primary/Se condary Positive Positive 6/36

17 Pin name I/O Description I 2 C bus interface SDA I/O I 2 C data input/output pin. This pin is used as the secondary function of the P40 pin. This pin has an NMOS open drain output. When using this pin as a function of the I 2 C, externally connect a pull-up resistor. SCL O I 2 C clock output pin. This pin is used as the secondary function of the P4 pin. This pin has an NMOS open drain output. When using this pin as a function of the I 2 C, externally connect a pull-up resistor. Synchronous serial (SSIO) SCK0 I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P4 or P45 pin. SIN0 I Synchronous serial data input pin. This pin is used as the tertiary function of the P40 or P44 pin. SOUT0 O Synchronous serial data output pin. This pin is used as the tertiary function of the P42 or P46 pin. PWM PWM0 O PWM0 output pin. This pin is used as the tertiary function of the P43 or P34 pin. T0P0CK I PWM0 external clock input pin. This pin is used as the primary function of the P44 pin. PWM O PWM output pin. This pin is used as the tertiary function of the P47 or P35 pin. TPCK I PWM external clock input pin. This pin is used as the primary function of the P45 pin. PWM2 O PWM2 output pin. This pin is used as the tertiary function of the P20 or P30 pin. P2CK I PWM2 external clock input pin. This pin is used as the primary function of the P02 pin. External interrupt NMI I External non-maskable interrupt input pin. An interrupt is generated on both edges. EXI0-7 I External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00-P07 pins. Capture Primary/ Secondary/ Tertiary Secondary Secondary Logic Positive Positive Tertiary Tertiary Tertiary Tertiary Positive Positive Positive Primary Tertiary Positive Primary Tertiary Positive Primary Primary Primary Positive/ negative Positive/ negative CAP0 I Capture trigger input pins. The value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. Primary Positive/ negative CAP I These pins are used as the primary functions of the P00 pin(cap0) and P0 pin(cap). Primary Positive/ negative Timer T0P0CK I External clock input pin used for Timer 0. This pin is used as the primary Primary function of the P44 pin. TPCK I External clock input pin used for Timer. This pin is used as the primary Primary function of the P45 pin. Melody MD0 O Melody/buzzer signal output pin. This pin is used as the secondary function of the P22 pin. Secondary Positive/ negative LED drive LED0-2 O Nch open drain output pins to drive LED. Primary Positive/ negative 7/36

18 Pin name I/O Description Primary/ Secondary/ Tertiary Logic RC oscillation type A/D converter IN0 I Channel 0 oscillation input pin. This pin is used as the secondary function Secondary of the P30 pin. CS0 O Channel 0 reference capacitor connection pin. This pin is used as the Secondary secondary function of the P3 pin. RS0 O This pin is used as the secondary function of the P32 pin which is the Secondary reference resistor connection pin of Channel 0. RT0 O Resistor sensor connection pin of Channel 0 for measurement. This pin is Secondary used as the secondary function of the P34 pin. CRT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. Secondary This pin is used as the secondary function of the P33 pin. RCM O RC oscillation monitor pin. This pin is used as the secondary function of Secondary the P35 pin. IN I Oscillation input pin of Channel. This pin is used as the secondary Secondary function of the P44 pin. CS O Reference capacitor connection pin of Channel. This pin is used as the Secondary secondary function of the P45 pin. RS O Reference resistor connection pin of Channel. This pin is used as the Secondary secondary function of the P46 pin. RT O Resistor sensor connection pin for measurement of Channel. This pin is Secondary used as the secondary function of the P47 pin. Successive approximation type A/D converter AV SS Negative power supply pin for successive approximation type A/D converter. AV DD Positive power supply pin for successive approximation type A/D converter. V REF Reference power supply pin for successive approximation type A/D converter. AIN0 I Channel 0 analog input for successive approximation type A/D converter. AIN I Channel analog input for successive approximation type A/D converter. LCD drive signal COM0-5 O Common output pins. COM8-23 O Common output pins. These pins are for the ML60Q438, but are not provided in the ML60Q439. SEG0-57 O Segment output pin. SEG58-63 O Segment output pins. These pins are for the ML60Q439, but are not provided in the ML60Q438. LCD driver power supply V L Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb, V L2 Cc, and Cd (see measuring circuit ) are connected between V SS and V L, V L3 V L2, V L3, and V L4, respectively. V L4 C Power supply pins for LCD bias (internally generated). Capacitors C2 C2 and C34 (see measuring circuit ) are connected between C and C2 and C3 between C3 and C4, respectively. C4 For testing TEST I/O Input/output pin for testing. A pull-down resistor is internally connected. Power supply V SS Negative power supply pin. 8/36

19 V DD Positive power supply pin. V DDL Positive power supply pin (internally generated) for internal logic. Capacitors CL0 and CL (see measuring circuit ) are connected between this pin and V SS. V DDX Plus-side power supply pin (internally generated) for low-speed oscillation. Capacitor Cx (see measuring circuit ) is connected between this pin and V SS. V PP Power supply pin for programming Flash ROM. A pull-up resistor is internally connected. 9/36

20 LAPIS Semiconductor TERMINATION OF UNUSED PINS Table 3 shows methods of terminating the unused pins. Table 3 Termination of Unused Pins V PP AV DD Pin Recommended pin termination Open V SS AV SS V SS V REF AIN0, AIN V SS Open V L, V L2, V L3, V L4 Open C, C2, C3, C4 Open RESET_N Open TEST Open NMI Open P00 to P07 V DD or V SS P0 to P V DD P20 to P22 Open P30 to P35 Open P40 to P47 Open PA0 to PA5 Open COM0 to 23 Open SEG0 to 63 Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. The main difference points of ML60Q438 and ML60Q439 Table 4 The main difference points of ML60Q438 and ML60Q439. Function ML60Q438 ML60Q439 LCD COM COM23 to COM0 COM5 to COM0 LCD SEG SEG55 to SEG0 SEG63 to SEG0 20/36

21 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (V SS = AV SS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage V DD Ta = 25 C 0.3 to +4.6 V Power supply voltage 2 AV DD Ta = 25 C 0.3 to +4.6 V Power supply voltage 3 V PP Ta = 25 C 0.3 to +9.5 V Power supply voltage 4 V DDL Ta = 25 C 0.3 to +3.6 V Power supply voltage 5 V DDX Ta = 25 C 0.3 to +3.6 V Power supply voltage 6 V L Ta = 25 C 0.3 to +.75 V Power supply voltage 7 V L2 Ta = 25 C 0.3 to +3.5 V Power supply voltage 8 V L3 Ta = 25 C 0.3 to V Power supply voltage 9 V L4 Ta = 25 C 0.3 to +7.0 V Input voltage V IN Ta = 25 C 0.3 to V DD+0.3 V Output voltage V OUT Ta = 25 C 0.3 to V DD+0.3 V Output current I OUT Port3 A, Ta = 25 C 2 to + ma Output current 2 I OUT2 Port2, Ta = 25 C 2 to +20 ma Power dissipation PD Ta = 25 C 22 mw Storage temperature T STG 55 to +50 C RECOMMENDED OPERATING CONDITIONS (V SS = AV SS = 0V) Parameter Symbol Condition Range Unit Operating temperature T OP ML60Q438/Q to +70 C ML60Q438P/Q439P Operating voltage V DD. to 3.6 V AV DD 2.2 to 3.6 AV DD V DD =. to 3.6V 30k to 36k Operating frequency (CPU) f OP V DD =.3 to 3.6V 30k to 650k Hz V DD =.8 to 3.6V 30k to 4.2M Low-speed crystal oscillation frequency f XTL k Hz Low-speed crystal oscillation C DL 0 to 2 external capacitor C GL 0 to 2 pf High-speed crystal/ceramic oscillation frequency f XTH 4.0M / 4.096M Hz High-speed crystal oscillation C DH 24 external capacitor C GH 24 pf Capacitor externally connected to C L0.0 30% V DDL pin C L 0. 30% F Capacitor externally connected to V DDX pin C X 0. 30% F Capacitors externally connected to V L, 2, 3, 4 pins C a, b, c, d.0 30% F Capacitors externally connected across C and C2 pins and across C3 and C4 pins C 2, C % F 2/36

22 OPERATING CONDITIONS OF FLASH ROM (V SS = AV SS = 0V) Parameter Symbol Condition Range Unit Operating temperature T OP At write/erase 0 to +40 C V DD At write/erase * 2.75 to 3.6 Operating voltage V DDL At write/erase * 2.5 to 2.75 V V PP At write/erase * 7.7 to 8.3 Write cycles C EP 80 cycles Data retention Y DR 0 years * : In addition the power supply to VDD pin and VPP pin, within the range 2.5V to 2.75V has to be supplied to VDDL pin when programming and eraseing Flash ROM. DC CHARACTERISTICS (/5) (V DD =. to 3.6V, AV DD = 2.2 to 3.6V, V SS = AV SS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version,unless otherwise specified ) (/5) Parameter Symbol Condition 500kHz RC oscillation frequency f RC V DD =.3 to 3.6V Ta = 25 C Ta = 20 to +70 C Rating Min. Typ. Max. Typ. 0% Typ. 25% Typ. 0% Typ. 25% Unit khz khz Measuring circuit PLL oscillation frequency* 4 LSCLK = kHz f PLL V DD =.8 to 3.6V -2.5% % MHz Low-speed crystal oscillation 2 start time* TXTL s 500kHz RC oscillation start time T RC s High-speed crystal oscillation 3 TXTH VDD =.8 to 3.6V 2 20 start time* PLL oscillation start time T PLL V DD =.8 to 3.6V 0 ms Low-speed oscillation stop detect * time TSTOP Reset pulse width P RST 200 Reset noise elimination s P pulse width NRST 0.3 Power-on reset activation power rise time T POR 0 ms *: When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. * 2 : Use KHz Crystal Resonator DT-26 (Load capacitance 6pF) (KDS: DAISHINKU CORP.) * 3 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera). * 4 : 024 clock average. RESET RESET_N VIL VIL P RST RESET_N pin reset 0.9xV DD VDD 0.xV DD T POR Power on reset 22/36

23 DC CHARACTERISTICS (2/5) (V DD =. to 3.6V, AV DD = 2.2 to 3.6V, V SS = AV SS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version, unless otherwise specified) (2/5) Parameter Symbol Condition Rating Min. Typ. Max. Unit CN4 0 = 00H CN4 0 = 0H CN4 0 = 02H CN4 0 = 03H CN4 0 = 04H CN4 0 = 05H CN4 0 = 06H CN4 0 = 07H CN4 0 = 08H CN4 0 = 09H CN4 0 = 0AH CN4 0 = 0BH..6.2 CN4 0 = 0CH CN4 0 = 0DH CN4 0 = 0EH V L voltage V L V DD = 3.0V, CN4 0 = 0FH Tj = 25 C CN4 0 = 0H V CN4 0 = H CN4 0 = 2H CN4 0 = 3H CN4 0 = 4H * CN4 0 = 5H * CN4 0 = 6H * CN4 0 = 7H * CN4 0 = 8H * CN4 0 = 9H * CN4 0 = AH * CN4 0 = BH * CN4 0 = CH * CN4 0 = DH * CN4 0 = EH * CN4 0 = FH * V L temperature deviation V L V DD = 3.0V mv/ C V L voltage dependency V L V DD =.3 to 3.6V 5 20 mv/v V L2 voltage V L2 V DD = 3.0V, Tj = 25 C Typ. 300k load (V L4 V SS) % VL 2 Typ. +4% V L3 voltage V L4 voltage LCD bias voltage generation time V L3 V L4 V DD = 3.0V, /3 bias Typ. V L 2 Tj = 25 C /4 bias 0% V L 3 300k load /3 bias Typ. V L 3 (V L4 V SS) /4 bias 0% V L 4 Typ. +4% Typ. +5% T BIAS 600 ms *: When using /4 bias, the V L voltage is set to typ..32 V (same voltage as in CN4 0 = 3H). V Measuring circuit 23/36

24 DC CHARACTERISTICS (3/5) (V DD =. to 3.6V, AV DD = 2.2 to 3.6V, V SS = AV SS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version,unless otherwise specified) (3/5) Parameter Symbol Condition BLD threshold voltage BLD threshold voltage temperature deviation Supply current Supply current 2 Supply current 3 Supply current 4 Supply current 5 V BLD V DD =.35 to 3.6V Rating Min. Typ. Max. LD2 0 = 0H.35 LD2 0 = H.4 LD2 0 = 2H.45 LD2 0 = 3H.5 LD2 0 = 4H.6 LD2 0 = 5H.7 LD2 0 = 6H.8 LD2 0 = 7H Typ..9 Typ. LD2 0 = 8H 2% % LD2 0 = 9H 2. LD2 0 = 0AH 2.2 LD2 0 = 0BH 2.3 LD2 0 = 0CH 2.4 LD2 0 = 0DH 2.5 LD2 0 = 0EH 2.7 LD2 0 = 0FH 2.9 V BLD V DD =.35 to 3.6V 0 %/ C IDD IDD2 IDD3 IDD4 IDD5 CPU: In STOP state. Low-speed/high-speed oscillation: stopped. CPU: In HALT state (LTBC, RTC: Operating* 3 * 5 ). High-speed oscillation: Stopped. LCD/BIAS circuits: Stopped. Ta = 25 C Ta = -20 to +70 C Ta = 25 C Ta = -20 to +70 C Ta = CPU: In kHz operating state.* * 3 25 C High-speed oscillation: Stopped. 2 Ta = -20 LCD/BIAS circuits: Operating.* to +70 C Ta = CPU: In 500kHz CR operating state. 25 C LCD/BIAS circuits: Operating.* 2 * 3 Ta = -20 to +70 C CPU: In 4.096MHz operating state. PLL: In oscillating state. LCD/BIAS circuits: Operating. * 2 * 3 V DD =.8 to 3.6V Ta = 25 C Ta = -20 to +70 C * : CPU operating rate is 00% (No HALT state). * 2 : All SEGs: off waveform, No LCD panel load, /3 bias, /3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock: /28 LSCLK (256Hz) * 3 : Use KHz Crystal Resonator DT-26 (Load capacitance 6pF) (KDS: DAISHINKU CORP.) * 4 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera). * 5 : Significant bits of BLKCON0~BLKCON4 registers are all. Unit V A A A A ma Measuring circuit 24/36

25 DC CHARACTERISTICS (4/5) (V DD =. to 3.6V, AV DD = 2.2 to 3.6V, V SS = AV SS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version,unless otherwise specified) (4/5) Parameter Symbol Condition Output voltage (P20 P22/2 nd function is selected) (P30 P36) (P40 P47) (PA0 PA5) VOH VOL IOH = 0.5mA, V DD =.8 to 3.6V Rating Min. Typ. Max. V DD 0.5 V DD IOH = -0.mA, V DD =.3 to 3.6V 0.3 V IOH = -0.03mA, V DD =. to 3.6V DD 0.3 IOL = +0.5mA, V DD =.8 to 3.6V 0.5 IOL = +0.mA, V DD =.3 to 3.6V 0.5 IOL = +0.03mA, V DD =. to 3.6V 0.3 Unit Measuring circuit Output voltage 2 (P20 P22/2 nd function is Not selected) Output voltage 3 (P40 P4) IOH = 0.5mA, V DD =.8 to 3.6V V DD 0.5 VOH2 IOH = -0.mA, V DD =.3 to 3.6V 0.3 IOH = -0.03mA, V DD =. to 3.6V V DD 0.3 VOL2 IOL2 = +5mA, V DD =.8 to 3.6V 0.5 VOL3 IOL3 = +3mA, V DD = 2.0 to 3.6V (when I 2 C mode is selected) 0.4 VOH4 IOH4 = 0.2mA, VL=.2V V L4 0.2 V DD V 2 Output voltage 4 (COM0 23) (SEG0 63) VOMH4 IOMH4 = +0.2mA, VL=.2V VOMH4S IOMH4S = 0.2mA, VL=.2V V L3 0.2 VOM4 IOM4 = +0.2mA, VL=.2V VOM4S IOM4S = 0.2mA, VL=.2V V L2 0.2 VOML4 IOML4 = +0.2mA, VL=.2V V L V L V L +0.2 VOML4S IOML4S = 0.2mA, VL=.2V V L 0.2 VOL4 IOL4 = +0.2mA, VL=.2V 0.2 Output leakage (P20 P22) IOOH VOH = V DD (in high-impedance state) (P30 P35) (P40 P47) (PA0 PA5) IOOL VOL = V SS (in high-impedance state) IIH VIH = V DD 0 Input current V DD =.8 to 3.6V (RESET_N) IIL VIL = V SS V DD =.3 to 3.6V Input current (TEST) Input current 2 (NMI) (P00 P03) (P04 P07) V DD =. to 3.6V V DD =.8 to 3.6V IIH VIH = V DD V DD =.3 to 3.6V V DD =. to 3.6V IIL VIL = V ss - IIH2 V DD =.8 to 3.6V VIH2 = V DD V DD =.3 to 3.6V (when pulled-down) V DD =. to 3.6V IIL2 VIL2 = V SS V DD =.8 to 3.6V A 3 A 4 25/36

26 (P0 P) (P30 P35) (P40 P47) (PA0 PA5) (when pulled-up) V DD =.3 to 3.6V V DD =. to 3.6V IIH2Z VIH2 = V DD (in high-impedance state) IIL2Z VIL2 = V SS (in high-impedance state) DC CHARACTERISTICS (5/5) (VDD =. to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version,unless otherwise specified) (5/5) Parameter Symbol Condition Input voltage (RESET_N) (TEST) (NMI) (P00 P03) (P04 P07) (P0 P) (P3 P35) (P40 P43) (P45 P47) (PA0 PA5) Hysteresis width (RESET_N) (TEST) (NMI) (P00 P03) (P04 P07) (P0 P) (P3 P35) (P40 P43) (P45 P47) (PA0 PA5) Input voltage 2 (P30, P44) Input pin capacitance (NMI) (P00 P03) (P04 P07) (P0 P) (P30 P35) (P40 P47) (PA0 PA5) VIH VIL VT VIH2 V DD =.3 to 3.6V V DD =. to 3.6V Rating Min. Typ. Max. 0.7 V DD V DD 0.7 V DD V DD V DD =.3 to 3.6V 0 V DD =. to 3.6V 0 V DD = 2.0 to 3.6V V DD =. to 3.6V 0.3 V DD 0.2 V DD V DD V DD V DD V DD V DD V DD 0.7 V DD V DD VIL2 0 CIN f = 0kHz V rms = 50mV Ta = 25 C 0.3 V DD Unit Measuring circuit V 5 5 pf HYSTERESIS WIDTH Input signal V T V DD Internal signal V SS V DDL V SS 26/36

27 MEASURING CIRCUITS MEASURING CIRCUIT XT0 C kHz crystal C GH C DH 4.096MHz crystal C V XT P0/OSC0 P/OSC V DD AV DD V REF V DDL A C L C L0 V DDX V L V L2 V L3 V L4 C X C a C b C c C d C3 C2 C V SS AV SS C 34 C 2 C V: F C L0: F C L: 0. F C X: 0. F C a,c b,c c,c d: F C 2,C 34: F C GH: 24pF C DH: 24pF KHz Crystal Resonator : DT-26 (Load capacitance 6pF) (KDS: DAISHINKU CORP.) 4.096MHz crystal: HC49SFWB (Kyocera) MEASURING CIRCUIT 2 VIH (*2) (*) Input pins Output pins V VIL V DD V DDL V DDX V L V L2 V L3 V L4 AV DDV REF V SSAV SS (*) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. 27/36

28 MEASURING CIRCUIT 3 VIH (*2) RS Input pins Output pins A VIL V DD V DDL V DDX V L V L2 V L3 V L4 AV DDV REF V SSAV SS MEASURING CIRCUIT 4 *: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. (*3) A Input pins Output pins V DD V DDL V DDX V L V L2 V L3 V L4 AV DDV REF V SSAV SS *3: Measured at the specified output pins. MEASURING CIRCUIT 5 VIH VIL (*) Input pins V DD Output pins V DDL V DDX V L V L2 V L3 V L4 AV DDV REF V SSAV SS Waveform monitoring *: Input logic circuit to determine the specified measuring conditions. 28/36

29 AC CHARACTERISTICS (External Interrupt) (V DD =. to 3.6V, AV DD = 2.2 to 3.6V, V SS = AV SS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version, unless otherwise specified) Parameter Symbol Condition External interrupt disable period T NUL Interrupt: Enabled (MIE = ), CPU: NOP operation System clock: kHz Rating Min. Typ. Max. Unit s P00 P07 (Rising-edge interrupt) t NUL P00 P07 (Falling-edge interrupt) t NUL NMI, P00 P07 (Both-edge interrupt) t NUL AC CHARACTERISTICS (UART) (V DD =. to 3.6V, AV DD = 2.2 to 3.6V, V SS = AV SS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version, unless otherwise specified) Parameter Symbol Condition Rating Min. Typ. Max. Transmit baud rate t TBRT BRT* s BRT* Receive baud rate t RBRT BRT* BRT* s 3% +3% *: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H) and the UART mode register 0 (UA0MOD0). Unit t TBRT TXD0* t RBRT RXD0* *: Indicates the secondary function of the port. 29/36

30 AC CHARACTERISTICS (Synchronous Serial Port) (V DD =. to 3.6V, AV DD = 2.2 to 3.6V, V SS = AV SS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version, unless otherwise specified) SCLK input cycle (slave mode) SCLK output cycle (master mode) SCLK input pulse width (slave mode) SCLK output pulse width (master mode) SOUT output delay time (slave mode) SOUT output delay time (master mode) SIN input setup time (slave mode) SIN input setup time (master mode) SIN input hold time Parameter Symbol Condition t SCYC When high-speed oscillation is not active When high-speed oscillation is active (V DD =.8 to 3.6V) Rating Min. Typ. Max. Unit 0 s s t SCYC SCLK* s t SW t SW When high-speed oscillation is not active When high-speed oscillation is active (V DD =.8 to 3.6V) 4 s 0.4 s SCLK* 0.4 SCLK* 0.5 SCLK* 0.6 t SD 80 ns t SD 80 ns t SS 80 ns t SS 80 ns t SH 80 ns *: Clock period selected with S0CK3 0 of the serial port 0 mode register (SIO0MOD) s t SCYC t SW t SW SCLK0* t SD t SD SOUT0* t SS t SH SIN0* *: Indicates the secondary function of the port. 30/36

31 AC CHARACTERISTICS (I 2 C Bus Interface: Standard Mode 00kHz) (V DD =.8 to 3.6V, AV DD = 2.2 to 3.6V, V SS = AV SS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version, unless otherwise specified) Parameter Symbol Condition Rating Min. Typ. Max. Unit SCL clock frequency f SCL 0 00 khz SCL hold time (start/restart condition) t HD:STA 4.0 s SCL L level time t LOW 4.7 s SCL H level time t HIGH 4.0 s SCL setup time (restart condition) t SU:STA 4.7 s SDA hold time t HD:DAT s SDA setup time t SU:DAT 0.25 s SDA setup time (stop condition) t SU:STO 4.0 s Bus-free time t BUF 4.7 s AC CHARACTERISTICS (I 2 C Bus Interface: Fast Mode 400kHz) (V DD =.8 to 3.6V, AV DD = 2.2 to 3.6V, V SS = AV SS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version, unless otherwise specified) Parameter Symbol Condition Rating Min. Typ. Max. Unit SCL clock frequency f SCL khz SCL hold time (start/restart condition) t HD:STA 0.6 s SCL L level time t LOW.3 s SCL H level time t HIGH 0.6 s SCL setup time (restart condition) t SU:STA 0.6 s SDA hold time t HD:DAT s SDA setup time t SU:DAT 0. s SDA setup time (stop condition) t SU:STO 0.6 s Bus-free time t BUF.3 s Start condition Restart condition Stop condition P40/SDA P4/SCL t HD:STA t LOW t HIGH t SU:STA t HD:STA t SU:DAT t HD:DAT t BUF t SU:STO 3/36

32 AC CHARACTERISTICS (RC Oscillation A/D Converter) (V DD =.3 to 3.6V, AV DD = 2.2 to 3.6V, V SS = AV SS = 0V, Ta = 20 to +70 C, Ta = 40 to +85 C for P version, unless otherwise specified) Parameter Symbol Condition Rating Min. Typ. Max. Unit RS0, RS, Resistors for oscillation RT0, RT0-,RT CS0, CT0, CS 740pF k f OSC Resistor for oscillation = k khz Oscillation frequency f OSC2 Resistor for oscillation = 0k khz VDD =.5V f OSC3 Resistor for oscillation = 00k khz RS to RT oscillation frequency Kf RT0, RT0-, RT = khz ratio * Kf2 RT0, RT0-, RT = 0 khz VDD =.5V Kf3 RT0, RT0-, RT = 00 khz f OSC Resistor for oscillation = k khz Oscillation frequency f OSC2 Resistor for oscillation = 0k khz VDD = 3.0V RS to RT oscillation frequency ratio * f OSC3 Resistor for oscillation = 00k khz Kf RT0, RT0-, RT = khz Kf2 RT0, RT0-, RT = 0 khz VDD = 3.0V Kf3 RT0, RT0-, RT = 00 khz *: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. Kfx = f OSCX(RT0 CS0 oscillation) f OSCX(RT0- CS0 oscillation) f OSCX(RT CS oscillation) f OSCX(RS0 CS0 oscillation), f OSCX(RS0 CS0 oscillation), f OSCX(RS CS oscillation) (x =, 2, 3) CVR0 CVR CS0 CT0 RI0- RS0 RT0 CS RS RT RT0, RT0-, RT: k /0k /00k RS0, RS: 0k CS0, CT0, CS: 560pF CVR0, CVR: 820pF VIH IN0 CS0 RCT0 RS0 RT0 IN CS RS RT (*) Input pins RCM Frequency measurement (f OSCX) VIL V DD V DDL V DDX V SS *: Input logic circuit to determine the specified measuring conditions. C V C L C L0 C X Note: - Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN pin), including CVR0/CVR. Especially, do not have long wire between IN0/IN and RS0/RS. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. - When RT0/RT (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal. - Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have. 32/36