MSM63188A 4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Drivers and Melody Circuit, Operating at 0.9 V (Min.)

Transcription

1 This version: Nov Previous version: Jun Bit Microcontroller with Built-in 1024-Dot Matrix LCD Drivers and Melody Circuit, Operating at 0.9 V (Min.) GENERAL DESCRIPTION The is a CMOS 4-bit microcontroller with built-in 1024-dot matrix LCD drivers and operates at 0.9 V (min.). The is suitable for applications such as games, toys, watches, etc. which are provided with an LCD display. The is an M6318x series mask ROM-version product of OLMS-63K family, which employs Oki s original CPU core nx-4/250. The MSM63P180 is the one-time-programmable ROM version of MSM63188/A, having one-time PROM (OTP) as internal program memory. The MSM63P180 is used to evaluate the software development. FEATURES Rich instruction set 439 instructions Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, ROM table reference, external memory transfer, stack operations, flag operations, branch, conditional branch, call/return, control. Rich selection of addressing modes Indirect addressing of four data memory types, with current bank register, extra bank register, HL register and XY register. Data memory bank internal direct addressing mode. Processing speed Two clocks per machine cycle, with most instructions executed in one machine cycle. Minimum instruction execution time : 61 µs (@ khz system clock) 1 µs (@ 2MHz system clock) Clock generation circuit Low-speed clock High-speed clock : Crystal oscillator ( khz) : Select ceramic oscillator (2 MHz Max.) or RC oscillator (1 MHz Max.) using software. Program memory space 16K words Basic instruction length is 16 bits/word Data memory space 3584 nibbles External data memory space 64 Kbytes (expandable by using an I/O port) Stack level Call stack level Register stack level : 16 levels : 16 levels 1/34

2 I/O ports Input ports Output ports : Selectable as input with pull-up resistance/input with pull-down resistance/high-impedance input : Selectable as P-channel open drain output/n-channel open drain output/cmos output/high-impedance output Input-output ports: Selectable as input with pull-up resistance/input with pull-down resistance/high-impedance input Selectable as P-channel open drain output/n-channel open drain output/cmos output/high-impedance output Can be interfaced with external peripherals that use a different power supply that this device uses. Number of ports Input port Output port Input-output port : 2 ports 4 bits : 6 ports 4 bits : 6 ports 4 bits Melody output function Melody sound frequency Tone length Tempo Note data Buzzer drive signal output : 529 to 2979 Hz : 63 types : 15 types : Resides in the program memory : 4 khz LCD driver Number of segments : 1024 Max. (64 SEG 16 COM) 1/1 to 1/16 duty 1/4 or 1/5 bias (regulator built-in) Selectable as all-on mode/all-off mode/power down mode/normal display mode Adjustable contrast Multiplier/divider circuits Multiplier Divider : (8 bits) (8 bits) Product (16 bits) : (16 bits) (8 bits) Quotient (16 bits), Remainder (8 bits) Reset function Reset through RESET pin Power-on reset Reset by low-speed oscillation halt Battery check Low-voltage supply check Criterion voltage : Can be selected as 1.05 ±0.10 V, 1.30 ±0.15 V, 2.20 ±0.20 V or 2.80 ±0.30 V Power supply backup Backup circuit (voltage multiplier) enables operation at 0.9 V minimum 2/34

3 Timers and counter 8-bit timer 4 Selectable as auto-reload mode/capture mode/clock frequency measurement mode Watchdog timer 1 Overflows in 2 sec. 100 Hz timer 1 Measurable in steps of 1/100 sec. 15-bit time base counter 1 1, 2, 4, 8, 16, 32, 64 and 128 Hz signals can be read Serial port Mode UART communication speed Clock frequency in synchronous mode Data length : UART mode, synchronous mode : 1200 bps, 2400 bps, 4800 bps, 9600 bps : khz (internal clock mode), external clock frequency : 5 to 8 bits Interrupt sources External interrupt : 4 Internal interrupt : 13 (watchdog timer interrupt is a nonmaskable interrupt) Operating voltage When backup used When backup not used : 0.9 to 2.7 V (Low-speed clock operating) 1.2 to 2.7 V (Operating frequency: 300 to 500 khz) 1.5 to 2.7 V (Operating frequency: 200 khz to 1 MHz) : 1.8 to 5.5 V (Operating frequency: 300 to 500 khz) 2.2 to 5.5 V (Operating frequency: 300 khz to 1 MHz) 2.7 to 5.5 V (Operating frequency: 200 khz to 2 MHz) Package: 176-pin plastic LQFP (LQFP176-P BK): (Product name: -xxxgs-bk) Chip (159 pads) : (Product name: -xxx) xxx indicates a code number. 3/34

4 BLOCK DIAGRAM An asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from V DDI (power supply for interface). CPU CORE nx-4/250 TIMING CON- TROL CBR EBR H X L Y RA A PC ROM 16 kw SP RSP ALU C G Z MIE BUS CON- TROL EXTMEM D0-7* A0-15* RESET TST1 TST2 STACK CAL : 16-level REG : 16-level RST TST INSTRUCTION DECODER INT 4 IR RAM 3584N INT188 MULDIV TBC DATA BUS INT 4 INT 2 INT 1 INT 1 TIMER 8bit 4 SIO MELODY INPUT PORT RD* WR* TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK* RXC* TXC* RXD* TXD* MD MDB P0.0-P0.3 P1.0-P1.3 XT0 XT1 OSC0 OSC1 TBCCLK* HSCLK* OSC INT 1 INT 1 BLD 100HzTC WDT OUTPUT PORT P2.0-P2.3 P3.0-P3.3 P4.0-P4.3 P5.0-P5.3 P6.0-P6.3 P7.0-P7.3 V DDH P8.0-P8.3 V DD CB1 BACK UP P9.0-P9.3 CB2 V DD1 V DD2 I/O PORT PA.0-PA.3 PB.0-PB.3 V DD3 V DD4 BIAS INT 3 PC.0-PC.3 PD.0-PD.3 V DD5 C1 C2 V DDL LCLK* FRAME* LCD & DSPR COM1-16 SEG0-63 V DDI V SS 4/34

5 5/34 PIN CONFIGURATION (TOP VIEW) 176-Pin Plastic LQFP Note: Pins marked as (NC) are no-connection pins which are left open. (NC) SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 (NC) P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 (NC) (NC) P5.0 P5.1 P5.2 P5.3 P6.0 P6.1 P6.2 P6.3 P7.0 P7.1 P7.2 P7.3 P8.0 P8.1 P8.2 P8.3 P9.0 P9.1 P9.2 P9.3 PA.0 PA.1 PA.2 PA.3 PB.0 PB.1 PB.2 PB.3 PC.0 PC.1 PC.2 PC.3 PD.0 PD.1 PD.2 PD.3 (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG (NC) COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VSS VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 V DDH CB1 CB2 VDD VDDL OSC1 OSC0 RESET XT1 XT0 TST2 TST1 (NC) (NC) MD MDB (NC) VDDI (NC)

6 PAD CONFIGURATION Pad Layout VDDI MDB MD TST1 TST2 XT0 XT1 RESET OSC0 OSC1 VDDL VDD CB2 CB1 VDDH C2 C1 VDD5 VDD4 VDD3 VDD2 VDD1 VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 PD.3 PD.2 PD.1 PD.0 PC.3 PC.2 PC.1 PC.0 PB.3 PB.2 PB.1 PB.0 PA.3 PA.2 PA.1 PA.0 P9.3 P9.2 P9.1 P9.0 P8.3 P8.2 P8.1 P8.0 P7.3 P7.2 P7.1 P7.0 P6.3 P6.2 P6.1 P6.0 P5.3 P5.2 P5.1 P (0, 0) 08M63188 Y X SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 P4.3 P4.2 P4.1 P4.0 P3.3 P3.2 P3.1 P3.0 P2.3 P2.2 P2.1 P2.0 P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG Note: The chip substrate voltage is V SS. Chip Size : 6.60 mm 6.60 mm Chip Thickness : 350 µm (typ.) Coordinate Origin : Chip center Pad Hole Size : 100 µm 100 µm Pad Size : 110 µm 110 µm Minimum Pad Pitch: 140 µm 6/34

7 Pad Coordinates Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) 1 P SEG SEG P SEG SEG P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG COM P SEG V SS P SEG V DD SEG SEG V DD SEG SEG V DD SEG SEG V DD SEG SEG V DD SEG SEG C SEG SEG C SEG SEG V DDH SEG SEG CB SEG SEG CB SEG SEG V DD SEG SEG V DDL SEG SEG OSC SEG SEG OSC SEG SEG RESET SEG SEG XT SEG SEG XT SEG SEG TST SEG SEG TST SEG SEG MD SEG SEG MDB SEG SEG V DDI /34

8 Pad Coordinates (continued) Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) 124 PD PA P PD PA P PD PA P PD PA P PC P P PC P P PC P P PC P P PB P P PB P P PB P P PB P P /34

9 PIN DESCRIPTIONS The basic functions of each pin of the are described in Table 1. A symbol with a slash ( / ) denotes a pin that has a secondary function. Refer to Table 2 for secondary functions. For type, denotes a power supply pin, I an input pin, O an output pin, and I/O an input-output pin. Table 1 Pin Descriptions (Basic Functions) Function Symbol Pin Pad No. Type Description V DD Positive power supply V SS Negative power supply V DD Power supply pins for LCD bias (internally generated). V DD Capacitors (0.1 µf) should be connected between these pins and V DD V SS. V DD V DD C Capacitor connection pins for LCD bias generation. Power C A capacitor (0.1 µf) should be connected between C1 and C2. supply Positive power supply pin for external interface V DDI (power supply for input, output, and input-output ports) Oscillation Test V DDL V DDH CB CB XT I XT O OSC I OSC O TST I TST I Positive power supply pin for internal logic (internally generated). A capacitor (0.1 µf) should be connected between this pin and V SS. Voltage multiplier pin for power supply backup (internally generated). A capacitor (1.0 µf) should be connected between this pin and V SS. Pins to connect a capacitor for voltage multiplier. A capacitor (1.0 µf) should be connected between CB1 and CB2. Low-speed clock oscillation pins. A khz crystal should be connected between XT0 and XT1, and C G (5 to 25 pf) should be connected between XT0 and V SS. High-speed clock oscillation pins. A ceramic resonator and capacitors (C L0, C L1 ) or external oscillation resistor (R OS ) should be connected to these pins. Input pins for testing. A pull-down resistor is internally connected to these pins. The user cannot use these pins. Reset RESET I Reset input pin. Setting this pin to H level puts this device into a reset state. Then, setting this pin to L level starts executing an instruction from address 0000H. A pull-down resistor is internally connected to this pin. Melody MD O Melody output pin (non-inverted output) MDB O Melody output pin (inverted output) 9/34

10 Table 1 Pin Descriptions (Basic Functions) (continued) Function Symbol Pin Pad No. Type Description Port P0.0/INT P0.1/INT P0.2/INT P0.3/INT P1.0/INT P1.1/INT P1.2/INT P1.3/INT P P P P P P P P P4.0/A P4.1/A P4.2/A P4.3/A P5.0/A P5.1/A P5.2/A P5.3/A P6.0/A P6.1/A P6.2/A P6.3/A P7.0/A P7.1/A P7.2/A P7.3/A I I O O O O O O 4-bit input ports. Pull-up resistor input, pull-down resistor input, or highimpedance input is selectable for each bit. 4-bit output ports. P-channel open drain output, N-channel open drain output, CMOS output, or high-impedance output is selectable for each bit. 10/34

11 Table 1 Pin Descriptions (Basic Functions) (continued) Function Symbol Pin Pad No. Type Description P8.0/RD bit input-output ports. P8.1/WR In input mode, pull-up resistor input, pull-down resistor I/O input, or high-impedance input is selectable for each P bit. P8.3/INT In output mode, P-channel open drain output, N- P9.0/D channel open drain output, CMOS output, or highimpedance output is selectable for each bit. P9.1/D I/O P9.2/D Port P9.3/D PA.0/D PA.1/D PA.2/D PA.3/D PB.0/INT0/ TM0CAP/TM0OVF PB.1/INT0/ TM1CAP/TM1OVF PB.2/INT0/T02CK PB.3/INT0/T13CK PC.0/INT1/RXD PC.1/INT1/TXC PC.2/INT1/RXC PC.3/INT1/TXD PD.0/FRAME PD.1/LCLK PD.2/TBCCLK PD.3/HSCLK I/O I/O I/O I/O 11/34

12 Table 1 Pin Descriptions (Basic Functions) (continued) Function Symbol Pin Pad No. Type Description COM LCD common signal output pins COM COM COM COM COM COM COM COM O COM COM COM COM COM COM COM SEG LCD segment signal output pins SEG SEG SEG LCD SEG SEG SEG SEG SEG SEG SEG SEG SEG O SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG /34

13 Table 1 Pin Descriptions (Basic Functions) (continued) Function Symbol Pin Pad No. Type Description SEG LCD segment signal output pins SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG LCD SEG O SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG /34

14 Table 2 shows the secondary functions of each pin of the. Table 2 Pin Descriptions (Secondary Functions) Function Symbol Pin Pad No. Type Description PB.0/INT External 0 interrupt input pins. PB.1/INT The change of input signal level causes an interrupt to occur. I The Port B Interrupt Enable register (PBIE) enables or PB.2/INT disables an interrupt for each bit. PB.3/INT PC.0/INT External 1 interrupt input pins. PC.1/INT The change of input signal level causes an interrupt to occur. I The Port C Interrupt Enable register (PCIE) enables or PC.2/INT disables an interrupt for each bit. PC.3/INT External Interrupt P8.3/INT I P0.0/INT P0.1/INT P0.2/INT P0.3/INT P1.0/INT P1.1/INT P1.2/INT P1.3/INT I External 4 interrupt input pin. The change of input signal level causes an interrupt to occur. External 5 interrupt input pins. The change of input signal level causes an interrupt to occur. The Port 0 Interrupt Enable register (P0IE) and Port 1 Interrupt Enable register (P1IE) enable or disable an interrupt for each bit. 14/34

15 Table 2 Pin Descriptions (Secondary Functions) (continued) Function Symbol Pin Pad No. Type Description Capture PB.0/TM0CAP I Timer 0 capture input pin. PB.1/TM1CAP I Timer 1 capture input pin. PB.0/TM0OVF O Timer 0 overflow flag output pin. PB.1/TM1OVF O Timer 1 overflow flag output pin. Timer PB.2/T02CK I External clock input pin for timer 0 and timer 2. PB.3/T13CK I External clock input pin for timer 1 and timer 3. LCD PD.0/FRAME O Frame output pin for LCD driver expansion External Expansion PD.1/LCLK O Clock output pin for LCD driver expansion Oscillation PD.2/TBCCLK O Low-speed oscillation clock output pin Output PD.3/HSCLK O High-speed oscillation clock output pin PC.0/RXD I Serial port receive data input pin Serial Port PC.1/TXC I/O PC.2/RXC I/O Sync serial port clock input-output pin. Transmit clock output when this device is used as a master processor. Transmit clock input when this device is used as a slave processor. Sync serial port clock input-output pin. Receive clock output when this device is used as a master processor. Receive clock input when this device is used as a slave processor. PC.3/TXD O Serial port transmit data output pin. 15/34

16 Table 2 Pin Descriptions (Secondary Functions) (continued) Function Symbol Pin Pad No. Type Description External Memory P4.0/A P4.1/A P4.2/A P4.3/A P5.0/A P5.1/A P5.2/A P5.3/A P6.0/A P6.1/A P6.2/A P6.3/A P7.0/A P7.1/A P7.2/A P7.3/A P9.0/D P9.1/D P9.2/D P9.3/D PA.0/D PA.1/D PA.2/D PA.3/D O I/O P8.0/RD O P8.1/WR O Address output bus for external memory Data bus for external memory Read signal output pin for external memory (negative logic) Write signal output pin for external memory (negative logic) 16/34

17 ABSOLUTE MAXIMUM RATINGS (V SS = 0 V) Parameter Symbol Condition Rating Unit Power Supply Voltage 1 V DD1 Ta = 25 C 0.3 to +1.6 V Power Supply Voltage 2 V DD2 Ta = 25 C 0.3 to +2.9 V Power Supply Voltage 3 V DD3 Ta = 25 C 0.3 to +4.2 V Power Supply Voltage 4 V DD4 Ta = 25 C 0.3 to +5.5 V Power Supply Voltage 5 V DD5 Ta = 25 C 0.3 to +6.8 V Power Supply Voltage 6 V DD Ta = 25 C 0.3 to +6.0 V Power Supply Voltage 7 V DDI Ta = 25 C 0.3 to +6.0 V Power Supply Voltage 8 V DDH Ta = 25 C 0.3 to +6.0 V Power Supply Voltage 9 V DDL Ta = 25 C 0.3 to +6.0 V Input Voltage 1 V IN1 V DD Input, Ta = 25 C 0.3 to V DD V Input Voltage 2 V IN2 V DD Input, Ta = 25 C 0.3 to V DDI V Output Voltage 1 V OUT1 V DD1 Output, Ta = 25 C 0.3 to V DD V Output Voltage 2 V OUT2 V DD2 Output, Ta = 25 C 0.3 to V DD V Output Voltage 3 V OUT3 V DD3 Output, Ta = 25 C 0.3 to V DD V Output Voltage 4 V OUT4 V DD4 Output, Ta = 25 C 0.3 to V DD V Output Voltage 5 V OUT5 V DD5 Output, Ta = 25 C 0.3 to V DD V Output Voltage 6 V OUT6 V DD Output, Ta = 25 C 0.3 to V DD V Output Voltage 7 V OUT7 V DDI Output, Ta = 25 C 0.3 to V DDI V Output Voltage 8 V OUT8 V DDH Output, Ta = 25 C 0.3 to V DDH V Storage Temperature T STG 55 to +150 C 17/34

18 RECOMMENDED OPERATING CONDITIONS When backup is used (V SS = 0 V) Parameter Symbol Condition Range Unit Operating Temperature T op 20 to +70 C Operating Voltage V DD 0.9 to 2.7 V V DDI 0.9 to 5.5 V Crystal Oscillation Frequency f XT 30 to 35 khz Ceramic Oscillation Frequency f CM V DD = 1.2 to 2.7 V 300k to 500k V DD = 1.5 to 2.7 V 200k to 1M Hz V DD = 1.2 to 2.7 V 100 to 300 External RC Oscillator Resistance R OS V DD = 1.5 to 2.7 V 50 to 300 kω When backup is not used (V SS = 0 V) Parameter Symbol Condition Range Unit Operating Temperature T op 20 to +70 C Operating Voltage V DD 1.8 to 5.5 V V DDI 1.8 to 5.5 V Crystal Oscillation Frequency f XT 30 to 35 khz V DD = 1.8 to 5.5 V 300k to 500k Ceramic Oscillation Frequency f CM V DD = 2.2 to 5.5 V 300k to 1M Hz VDD = 2.7 to 5.5 V 200k to 2M V DD = 1.8 to 5.5 V 100 to 300 External RC Oscillator Resistance R OS V DD = 2.2 to 5.5 V 50 to 300 VDD = 2.7 to 5.5 V 30 to 300 kω 18/34

19 High-speed RC oscillation characteristics (Typ.) When backup is used (V DD = V DDI = 1.5 V) [[Reference] Reference] [Reference] f OSC [khz] R 1000 OS [kω] High-speed RC oscillation characteristics (Typ.) When backup is not used (V DD = V DDI = 3.0 V) [Reference] f OSC [khz] R 1000 OS [kω] 19/34

20 ELECTRICAL CHARACTERISTICS DC Characteristics (V SS = V DDI = 0.9 to 5.5 V, V SS = 0 V, Ta = 20 to +70 C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit V DD2 Voltage V DD2 1/5 bias, 1/4 bias (Ta = 25 C) V DD2 Voltage Temperature Deviation V V DD2 4 mv/ C V DD1 Voltage V DD1 1/5 bias, 1/4 bias Typ /2 V DD2 Typ V V DD3 Voltage V DD3 1/4 bias (connect V DD3 and V DD2 ) 1/5 bias Typ /2 V DD2 Typ Typ. 0.2 V DD2 Typ /5 bias Typ V DD2 Typ V DD4 Voltage V DD4 1/4 bias Typ /2 V DD2 Typ V V Measuring Circuit 1/5 bias Typ /2 V DD2 Typ V DD5 Voltage V DD5 1/4 bias Typ V DD2 Typ V V DDH Voltage (Backup used) V DDH High-speed clock oscillation stopped V DD = 1.5 V High-speed clock oscillation (Ceramic oscillation, 1 MHz V DD = 1.5 V) High-speed clock oscillation V DDL Voltage V DDL stopped High-speed clock oscillation (V DD = 1.2 to 5.5 V) Crystal Oscillation Start Voltage Crystal Oscillation Hold Voltage Crystal Oscillation Stop Detect Time External Crystal Oscillator Capacitance Internal Crystal Oscillator Capacitance External Ceramic Oscillator Capacitance Internal RC Oscillator Capacitance V STA Oscillation start time: within 5 seconds V V V V 1.0 V Backup 0.9 V V HOLD Backup not used 1.7 V T STOP ms C G 5 25 pf C D pf C L0, 1 CSA2.00MG (Murata MFG.- make) used V DD = 3.0 V 30 pf C OS pf V DD = 1.5 V V POR Voltage V POR1 V DD = 3.0 V V 1 V DD = 1.5 V V Non-POR Voltage V POR2 V DD = 3.0 V V Notes: 1. V DD varies in the range of 1.8 to 2.4 V depending on the value of the display contrast register (DSPCNT). 2. T STOP indicates that if the crystal oscillator stops over the value of T STOP, the system reset occurs. 3. POR denotes Power On Reset. 4. V POR1 indicates that POR occurs when V DD falls from V DD to V POR1 and again rises up to V DD. 5. V POR2 indicates that POR does not occur when V DD falls from V DD to V POR2 and again rises up to V DD. 20/34

21 DC Characteristics (continued) When backup is used (V DD = V DDI = 1.5 V, V SS = 0 V, 1/5 bias, DSPCNT = 0H, Ta = 20 to +70 C unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit Circuit CPU is in HALT state. Ta = 20 to +50 C Supply Current 1 I DD1 (High-speed clock oscillation stopped) Ta = 20 to +70 C µa CPU is in HALT state. LCD is in Power Down mode. Ta = 20 to +50 C Supply Current 2 I DD2 (High-speed clock oscillation stopped) Ta = 20 to +70 C µa Supply Current 3 I DD3 CPU is in operation at low-speed oscillation. (High-speed clock oscillation stopped) Supply Current 4 I DD4 CPU is in operation at high-speed oscillation (RC oscillation, f = approx. 720 khz, R OS = 51 kω) Supply Current 5 I DD5 CPU is in operation at high-speed oscillation (Ceramic oscillation, 1 MHz) µa µa µa 1 When backup is not used (V DD = V DDI = 3.0 V, V SS = 0 V, 1/5 bias, DSPCNT = 0H, Ta = 20 to +70 C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Supply Current 1 I DD1 (High-speed clock CPU is in HALT state. oscillation stopped) Supply Current 2 I DD2 LCD is in Power Down mode. (High-speed clock CPU is in HALT state. oscillation stopped) Supply Current 3 I DD3 CPU is in operation at low-speed oscillation. (High-speed clock oscillation stopped) Supply Current 4 I DD4 high-speed oscillation CPU is in operation at (RC oscillation) Ta = 20 to +50 C Ta = 20 to +70 C Ta = 20 to +50 C Ta = 20 to +70 C f = approx. 800 khz, R OS = 51 kω f = approx. 500 khz, R OS = 100 kω Supply Current 5 I DD5 CPU is in operation at high-speed oscillation (Ceramic oscillation, 2 MHz) µa µa µa µa µa Measuring Circuit 1 21/34

22 DC Characteristics (continued) (V DD = V DDI = V DDH = 3.0 V, V SS = 0 V, V DD1 = 1.1 V, V DD2 = 2.2 V, V DD3 = 3.3 V, V DD4 = 4.4 V, V DD5 = 5.5 V, Ta = 20 to +70 C unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit Circuit Output Current 1 V DDI = 1.5 V ma (P2.0 to P2.3) (P3.0 to P3.3) I OH1 V OH1 = V DDI 0.5 V V DDI = 3.0 V ma (P4.0 to P4.3) V DDI = 5.0 V ma V DDI = 1.5 V ma (PC.0 to PC.3) (PD.0 to PD.3) I OL1 V OL1 = 0.5 V V DDI = 3.0 V ma V DDI = 5.0 V ma Output Current 2 V DD = 1.5 V ma (MD, MDB) I OH2 V OH2 = V DD 0.7 V V DD = 3.0 V ma V DD = V DDH = 5.0 V ma V DD = 1.5 V ma I OL2 V OL2 = 0.7 V V DD = 3.0 V ma V DD = V DDH = 5.0 V ma Output Current 3 I OH3 V OH3 = V DD5 0.2 V (V DD5 level) 4 µa (SEG0 to SEG39) (COM1 to COM16) Output Current 4 (OSC1) Output Leakage (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) (PD.0 to PD.3) I OHM3 V OHM3 = V DD V (V DD4 level) 4 µa I OHM3S V OHM3S = V DD4 0.2 V (V DD4 level) 4 µa I OMH3 V OMH3 = V DD V (V DD3 level) 4 µa I OMH3S V OMH3S = V DD3 0.2 V (V DD3 level) 4 µa I OML3 V OML3 = V DD V (V DD2 level) 4 µa I OML3S V OML3S = V DD2 0.2 V (V DD2 level) 4 µa I OLM3 V OLM3 = V DD V (V DD1 level) 4 µa I OLM3S V OLM3S = V DD1 0.2 V (V DD1 level) 4 µa I OL3 V OL3 = V SS V (V SS level) 4 µa I OH4R I OL4R I OH4C I OL4C V OH4R = V DDH 0.5 V V DD = V DDH = 3.0 V ma (RC oscillation) V DD = V DDH = 5.0 V ma V OL4R = 0.5 V V DD = V DDH = 3.0 V ma (RC oscillation) V DD = V DDH = 5.0 V ma V OH4C = V DDH 0.5 V V DD = V DDH = 3.0 V µa (ceramic oscillation) V DD = V DDH = 5.0 V µa V OL4C = 0.5 V V DD = V DDH = 3.0 V µa (ceramic oscillation) V DD = V DDH = 5.0 V µa I OOH V OH = V DDI 0.3 µa I OOL V OL = V SS 0.3 µa 2 22/34

23 DC Characteristics (continued) (V DD = V DDI = V DDH = 3.0 V, V SS = 0 V, V DD1 = 1.1 V, V DD2 = 2.2 V, V DD3 = 3.3 V, V DD4 = 4.4 V, V DD5 = 5.5 V, Ta = 20 to +70 C unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit Circuit Input Current 1 V DDI = 1.5 V µa (P0.0 to P0.3) V I IH1 = V DDI (P1.0 to P1.3) IH1 (when pulled down) V DDI = 3.0 V µa (P8.0 to P8.3) V DDI = 5.0 V µa (P9.0 to P9.3) V DDI = 1.5 V µa (PD.0 to PD.3) I IL1 V IL1 = V SS (when pulled up) V DDI = 3.0 V µa V DDI = 5.0 V µa Input Current 2 (OSC0) I IH1Z V IH1 = V DDI (in a high impedance state) 0 1 µa I IL1Z V IL1 = V SS (in a high impedance state) 1 0 µa I IL2 V IL2 = V SS V DD = V DDH = 3.0 V µa (when pulled up) V DD = V DDH = 5.0 V µa I IH2R V IH2R = V DDH (RC oscillation) 0 1 µa I IL2R V IL2R = V SS (RC oscillation) 1 0 µa I IH2C I IL2C V IH2C = V DDH V DD = V DDH = 3.0 V µa (ceramic oscillation) V DD = V DDH = 5.0 V µa V IL2C = V SS V DD = V DDH = 3.0 V µa (ceramic oscillation) V DD = V DDH = 5.0 V µa 3 Input Current 3 (RESET) V DD = 1.5 V µa I IH3 V IH3 = V DD V DD = 3.0 V µa V DD = V DDH = 5.0 V ma Input Current 4 (TST1, TST2) I IL3 V IL3 = V SS 1 0 µa V DD = 1.5 V µa I IH4 V IH4 = V DD V DD = 3.0 V ma V DD = V DDH = 5.0 V ma I IL4 V IL4 = V SS 1 0 µa 23/34

24 DC Characteristics (continued) Input Volotage 1 (P0.0 to P0.3) (P1.0 to P1.3) (P8.0 to P8.3) (P9.0 to P9.3) (PD.0 to PD.3) Input Voltage 2 (OSC0) (V DD = V DDI = V DDH = 3.0 V, V SS = 0 V, V DD1 = 1.1 V, V DD2 = 2.2 V, V DD3 = 3.3 V, V DD4 = 4.4 V, V DD5 = 5.5 V, Ta = 20 to +70 C unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit Circuit V DDI = 1.5 V V V IH1 V DDI = 3.0 V V V DDI = 5.0 V V V DDI = 1.5 V V V IL1 V DDI = 3.0 V V V DDI = 5.0 V 0 1 V V DD = V DDH = 3.0 V V V IH2 V DD = V DDH = 5.0 V V V DD = V DDH = 3.0 V V V IL2 V DD = V DDH = 5.0 V 0 1 V Input Voltage 3 (RESET, TST1, TST2) V DD = 1.5 V V V IH3 V DD = 3.0 V V V DD = V DDH = 5.0 V V V DD = 1.5 V V V IL3 V DD = 3.0 V V V DD = V DDH = 5.0 V 0 1 V 4 Hysteresis Width 1 (P0.0 to P0.3) (P1.0 to P1.3) (P8.0 to P8.3) V T1 V DDI = 1.5 V V V DDI = 3.0 V V (PD.0 to PD.3) V DDI = 5.0 V V Hysteresis Width 2 V DD = 1.5 V V (RESET, TST1, TST2) V T2 V DD = 3.0 V V VDD = VDDH = 5.0 V V Input Pin Capacitance (P0.0 to P0.3) (P1.0 to P1.3) (P8.0 to P8.3) (P9.0 to P9.3) C IN 5 pf 1 (PC.0 to PC.3) (PD.0 to PD.3) 24/34

25 Measuring circuit 1 C b12 C 12 CB1 CB2 C1 C2 XT0 XT1 C G khz Crystal 1 *1 2 OSC0 OSC1 V SS V DD V DDI V DD1 V DD2 V DD3 V DD4 V DD5 V DDH V DDL A C a C b C c C d C e C h C l V V V V V V V C a, C b, C c, C d, C e, C l, C 12 : 0.1 µf C b12, C h : 1 µf C G : 15 pf C L0 : 30 pf C L1 : 30 pf Ceramic Resonator : CSA2.00MG (2 MHz) CSB1000J (1 MHz) (Murata MFG.-make) *1 RC Oscillator R OS C L0 C L1 1 2 Ceramic Oscillator 1 Ceramic Resonator 2 Measuring circuit 2 V IH *3 *2 INPUT OUTPUT A V IL V SS V DD V DDI V DD1 V DD2 V DD3 V DD4 V DD5 V DDH V DDL *2 Input logic circuit to determine the specified measuring conditions. *3 Measured at the specified output pins. 25/34

26 Measuring circuit 3 *4 A INPUT OUTPUT V SS V DD V DDI V DD1 V DD2 V DD3 V DD4 V DD5 V DDH V DDL Measuring circuit 4 V IH *4 INPUT OUTPUT Waveform Monitoring V IL V SS V DD V DDI V DD1 V DD2 V DD3 V DD4 V DD5 V DDH V DDL *4 Measured at the specified input pins. 26/34

27 AC Characteristics (Serial Interface, Serial Port) (V DD = 0.9 to 5.5 V, V DDH = 1.8 to 5.5 V, V SS = 0 V, V DDI = 5.0 V, Ta = 20 to +70 C unless otherwise specified) (1) Synchronous Communication Parameter Symbol Condition Min. Typ. Max. Unit TXC/RXC Input Fall Time t f 1.0 µs TXC/RXC Input Rise Time t r 1.0 µs TXC/RXC Input L Level Pulse Width t CWL 0.8 µs TXC/RXC Input H Level Pulse Width t CWH 0.8 µs TXC/RXC Input Cycle Time t CYC 2.0 µs TXC/RXC Output Cycle Time t CYC1(0) CPU in operation state at 32 khz 30.5 µs t CYC2(0) CPU in operation at 2 MHz V DD = V DDH = 2.7 V to 5.5 V 0.5 µs TXD Output Delay Time t DDR Output load capacitance 10 pf 0.4 µs RXD Input Setup Time t DS 0.5 µs RXD Input Hold Time t DH 0.8 µs Synchronous communication timing ( H level = 4.0 V, L level = 1.0 V) t CYC TXC (PC.1)/ RXC (PC.2) t r t f 5 V (V DDI ) 0 V (V SS ) t CWH t CWL t DDR t DDR TXD (PC.3) 5 V (V DDI ) 0 V (V SS ) t DS t DH t DS RXD (PC.0) 5 V (V DDI ) 0 V (V SS ) 27/34

28 (2) UART Communication Parameter Symbol Condition Min. Typ. Max. Unit Transmit Baud Rate T BRT T BRT = 1/f BRT T CR = 1/f OSC T BRT T CR T BRT T BRT + T CR s Receive Baud Rate R BRT R BRT = 1/f BRT R BRT 0.97 R BRT R BRT 1.03 s FBRT: Baud rates (1200, 2400, 4800, 9600 bps) UART communication timing ( H level = 4.0 V, L level = 1.0 V) T BRT TXD (PC.3) 5 V (V DDI ) 0 V (V SS ) R BRT RXD (PC.0) 5 V (V DDI ) 0 V (V SS ) 28/34

29 AC Characteristics (External Memory Interface) (V DD = 0.9 to 5.5 V, V DDH = 1.8 to 5.5 V, V SS = 0 V, V DDI = 5.0 V, Ta = 20 to +70 C unless otherwise specified) (1) Reading from External Memory (a) When CPU operates at khz Parameter Symbol Condition Min. Typ. Max. Unit Read Cycle Time t RC 61.0 µs RD Output Delay Time t OE 5.0 µs Output Valid Time t OHA 5.0 µs External Memory Output Delay Time t DO 5.0 µs (b) When CPU operates at 2 MHz (V DDH = 2.7 to 5.5 V) Parameter Symbol Condition Min. Typ. Max. Unit Read Cycle Time t RC 1.0 µs RD Output Delay Time t OE 100 ns Output Valid Time t OHA 100 ns External Memory Output Delay Time t DO 150 ns AC characteristics timing ( H level = 4.0 V, L level = 1.0 V) S1 MOVXB obj, xadr16 MOVXB obj, [RA] S2 S1 S2 S1 S2 System clock t RC P7 - P4 (A15 - A0) Port setup value Address output Port setup value 5 V (V DDI ) 0 V (V SS ) P8.0 (RD) t OE t OHA 5 V (V DDI ) 0 V (V SS ) PA, P9 (D7 - D0) Port setup value Input data Port setup value 5 V (V DDI ) 0 V (V SS ) t DO 29/34

30 (2) Writing from External Memory (a) When CPU operates at khz Parameter Symbol Condition Min. Typ. Max. Unit Write Cycle Time t WC 61.0 µs Address Setup Time t AS 30.5 µs Write Time t W 15.3 µs Write Recovery Time t WR 15.3 µs Data Setup Time t DS 45.8 µs Data Hold Time t DH 15.3 µs (b) When CPU operates at 2 MHz (V DDH = 2.7 to 5.5 V) Parameter Symbol Condition Min. Typ. Max. Unit Write Cycle Time t WC 1.0 µs Address Setup Time t AS 0.4 µs Write Time t W 0.2 µs Write Recovery Time t WR 0.2 µs Data Setup Time t DS 0.7 µs Data Hold Time t DH 0.2 µs AC characteristics timing ( H level = 4.0 V, L level = 1.0 V) MOVXB [RA], obj or MOVXB xadr16, obj S1 S2 S1 S2 S1 S2 System clock t WC P7 - P4 (A15 - A0) Port setup value Address output Port setup value 5 V (V DDI ) 0 V (V SS ) PA, P9 (D7 - D0) Port setup value Output data Port setup value 5 V (V DDI ) 0 V (V SS ) t DS t DH P8.1 (WR) 5 V (V DDI ) 0 V (V SS ) t AS t W t WR 30/34

31 APPLICATION CIRCUITS Crystal khz XT0 COM1-16 LCD SEG0-63 OSC0 RC oscillation is selected as high-speed oscillation. Ports are powered from external memory power source. C V is an IC power supply bypass capacitor. Values of C a, C b, C c, C d, C e, C I, C b12, C 12, C h and C G are for reference only. C G 5 to 25 pf 1.5 V C h 1.0 µf XT1 V DDH OSC1 R OS V DD C v C b12 C l C e C d C c C b C a C 12 Buzzer 0.1 µf 1.0 µf 0.1 µf CB1 CB2 V DDL V DD5 V DD4 V DD3 V DD2 0.1 µf 0.1 µf 0.1 µf 0.1 µf 0.1 µf V DD1 C1 0.1 µf Push SW C2 RESET TST1 TST2 MD P3.3 P3.2 P3.1 P3.0 P2.3 P2.2 P2.1 P2.0 P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.0 V DDI SW Matrix (8 8) MDB V SS P4-7 P9, PA P8.0 P8.1 V DD A15-0 External D7-0 Memory RD (64K 8 bits) WR V SS 5.0 V Note: V DDI is the power supply pin for the input, output, and input-output ports. Be sure to connect the V DDI pin either to the positive power supply pin (V DD ) of this device or to the positive power supply pin of the external memory. Application Circuit Example with Power Supply Backup 31/34

32 C G V DD 5 to 25 pf Crystal khz XT0 XT1 COM1-16 LCD SEG0-63 OSC0 OSC1 Ceramic oscillation is selected as highspeed oscillation. Ports, external memory, and IC share their power supply. C V is an IC power supply bypass capacitor. Values of C a, C b, C c, C d, C e, C I, C 12, C G, C L0 and C L1 are for reference only. C L0 30 pf Ceramic Resonator (Example: 1 MHz) 5.0 V V DDH C L1 30 pf V DD C v C l C e C d C c C b C a C 12 Buzzer 0.1 µf Open 0.1 µf 0.1 µf 0.1 µf 0.1 µf 0.1 µf 0.1 µf 0.1 µf Push SW CB1 CB2 V DDL V DD5 V DD4 V DD3 V DD2 V DD1 C1 C2 RESET TST1 TST2 MD P3.3 P3.2 P3.1 P3.0 P2.3 P2.2 P2.1 P2.0 P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.0 V DDI SW Matrix (8 8) V DD MDB V SS P4-7 P9, PA P8.0 P8.1 V DD A15-0 External D7-0 Memory RD (64K 8 bits) WR V SS Note: V DDI is the power supply pin for the input, output, and input-output ports. Be sure to connect the V DDI pin either to the positive power supply pin (V DD ) of this device or to the positive power supply pin of the external memory. Application Circuit Example with No Power Supply Backup 32/34

33 PACKAGE DIMENSIONS LQFP176-P BK (Unit: mm) Mirror finish 5 Rev. Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating ( 5µm) Package weight (g) 1.87 TYP. No./Last Revised 3/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 33/34

34 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd. 34/34