A System-On-Board Approach for Impedance-Based Structural Health Monitoring

Transcription

1 A Syste-On-Board Approah for Ipedane-Based Strutural Health Monitoring Jina Ki *a, Benjain L. Grisso b, Dong S. Ha a, and Daniel J. Inan b a Virginia Teh VLSI for Teleouniations Laboratory Departent of Eletrial and Coputer Engineering, Virginia Teh, Blaksburg, VA b Center for Intelligent Material Systes and Strutures Virginia Teh, 31 Durha Hall MC 261, Blaksburg, VA 2461 ABSTRACT Currently, uh of the fous in the strutural health onitoring ounity is shifting towards inorporating health onitoring tehnology into real world strutures. Deployent of strutural health onitoring systes for peranent daage detetion is usually liited by the availability of sensor tehnology. Previously, we developed the first fully self-ontained syste that perfors ipedane-based strutural health onitoring. This digital signal proessor based syste effetively replaes a traditional ipedane analyzer and all of the anual analysis usually required for daage deterination. The work desribed here will fous on iproving this hardware. Efforts are ade to redue the overall power onsuption of the prototype while at the sae tie iproving the overall perforane and effiieny. By introduing a new exitation ethod and ipleenting a new daage detetion shee, reliane on both analog-todigital and digital-to-analog onversion are iruvented. These new atuation and sensing tehniques, along with the underlying hardware, are desribed in detail. The redution of power dissipation and iproved perforane are douented and opared with both traditional ipedane tehniques and the previous prototype. Keywords: strutural health onitoring, self-sensing atuator, ipedane ethod, digital signal proessor, syste-on-board, low-power dissipation 1. INTRODUCTION The strutural health onitoring (SHM) researh ounity is shifting their fous towards inorporating SHM tehnology into real world strutures, and onsequently opat hardware with low power dissipation beoe deanding features for a SHM syste. A sall for-fator an inrease the physial robustness, as well as lower the deployent and aintenane osts, of SHM systes. Low power dissipation akes it possible to use power harvesting units exploiting abient vibration and teperature gradients, whih ontributes to ost redution. Previously, we have developed the first fully self-ontained prototype that perfors ipedane-based SHM, whih onsists of a digital signal proessor (DSP) evaluation odule (EVM), an analog-to-digital onverter (ADC) EVM, and a digital-to-analog onverter (DAC) EVM [1,2]. This DSP based ulti-board syste effetively replaed a traditional ipedane analyzer and anual analysis required for daage assessent. The proedures of strutural exitation, data aquisition, and daage assessent are perfored in a atter of seonds, and daage in a struture an be deteted alost instantaneously. However, as this prototype is ipleented on three evaluation boards, it has liitation on pratial deployent due to high power dissipation and a large for fator. There has been an effort to develop a opat hardware for SHM and sensor diagnostis utilizing an ipedane onverter / network analyzer integrated iruit (IC) AD5933 fro Analog Devies [4]. Though a SHM syste with a usto printed iruit board (PCB) whih is apable of aquiring ipedane easureents and wirelessly transitting the raw data was developed, it ust still rely on a separate oputer for daage assessent. We have proposed a new algorith, digital low-power SHM, that perfors SHM operations with binary signaling [3] to redue oputational oplexity, siplify hardware ipleentation, and aordingly lower the power dissipation. This digital low-power SHM algorith opletely eliinates the reliane on analog signaling for strutural exitation, and, * jiki4@vt.edu; phone ; fax ; vtvt.org Sensors and Sart Strutures Tehnologies for Civil, Mehanial, and Aerospae Systes 27, edited by Masayoshi Toizuka, Chung-Bang Yun, Vitor Giurgiutiu, Pro. of SPIE Vol. 6529, 6529O, (27) X/7/$18 doi: / Pro. of SPIE Vol O-1

2 onsequently, data aquisition an also be perfored using a binary forat. Therefore, ipleenting a SHM syste without inorporating an ADC or a DAC to ahieve opat hardware developent with lower power dissipation beae possible. In this paper, we present prototype developent for the digital low-power SHM algorith utilizing binary signaling in detail. The binary signaling algorith is briefly desribed and opared with the previously utilized analog based algorith. By using a set of test strutures, the funtionality is verified and the perforane, in ters of daage detetion and power dissipation, is evaluated. The prototype deonstrates the feasibility of ipleenting a SHM syste on a single PCB. 2. OPERATION AND ARCHITECTURE Ipedane-based SHM perfors three ajor operations: exitation signal generation, sensor atuation and sensing, and daage assessent. An exitation signal an be generated by a traditional funtion generator or by a DSP. The exitation signal generated by a DSP is transitted to a self-sensing atuator bonded to the struture. A self-sensing atuator, whih is ade fro piezoeletri aterials, generally utilizes MFC (Miro-Fiber Coposite) or PZT (Lead Zironate Titanate) pathes. A PZT path is adopted for our prototype. One the exitation signal fro the DSP reahes the self-sensing atuator, the strutural response indues stress on the atuator to produe a response signal, whih is altered fro the exitation signal aording to the struture s ehanial ipedane. The response signal an be sensed by a traditional ipedane analyzer or by a DSP. The reorded strutural response is post-proessed to reate a signature and alulate a daage etri, either in a oputer using a general purpose oputing software suh as MATLAB, or in a DSP. A signature is a frequeny doain representation of the strutural response that varies depending on the struture s ehanial ipedane, and the first signature, alled a baseline, is stored as a referene under the assuption that the struture is initially in a healthy ondition. The strutural response is easured a ertain nuber of ties, and their average generates an ipedane signature. The daage etri, a differene between the baseline and the urrent signature, is opared to a preset threshold value to deterine if the struture has been daaged. Sine our ultiate goal is to develop an SHM syste on a single board, we have proposed to use a DSP as an exitation signal generator, strutural response sensor, and a post-proessor to effetively eliinate one neessary equipent suh as a funtion generator, an ipedane analyzer, and a oputer out of the SHM syste [1-3]. In developing our first prototype desribed in detail in [1,2], we have used a sin wavefor to exite the struture, whih is an ipulse-like signal ontaining ultiple frequeny oponents fro DC to very high frequeny depending on the sapling speed of the ADC. The sin wavefor is generated by a DSP and sent out through a DAC to the PZT bonded to the struture. The strutural response is then easured through an ADC to provide an estiated voltage level to the DSP. Finally, the DSP perfors a fast Fourier transfor (FFT) on the reeived voltage sequene to reate the baseline or a signature, and alulates the root ean squared deviation (RMSD) daage etri between the baseline and a urrent signature. The digital low-power SHM algorith proposed in [3] is applied to this syste-on-board approah prototype developent, and the overall arhiteture is shown in Figure 1. Instead of the sin wavefor used in our previous prototype, digital retangular pulse trains of various frequenies, generated by the pulse width odulation (PWM) signal generator of the DSP, are proposed to exite the struture. Sine the exitation signal is a binary sequene, the reliane on a DAC is iruvented. Strutural response through the PZT is also sensed with only the sign (positive or negative) of the voltage rather than ultiple voltage levels, and this hange results in the eliination of ADC use. As illustrated in Figure 1, there are two signal paths in perforing sensor atuation and sensing: a referene signal path and a easuring signal path. The referene signal path is a route through whih the exitation signal fro the PWM is diretly fed bak into the DSP, and the easuring signal path is the atual exitation and sensing signal path through an Opap and a oparator. Both signal paths are going into general purpose input output (GPIO) pins of the DSP for oparison. Variations between the two signals are ainly aused by the ehanial ipedane of the struture. These differenes an be represented in ters of a variation ount by ounting the nuber of differenes between the reeived referene path sequene and easuring path sequene at eah frequeny oponent. An enseble average of a ertain nuber of variation ounts produes a signature. Finally, the daage etri is alulated as a su of absolute differenes between the baseline and a signature through the frequeny oponents and is opared with the preset threshold value to deterine whether the struture is daaged. Pro. of SPIE Vol O-2

3 D2b qq OblO Cowb9L9oL qq 2lflCflL6 b qq bmv Ob vwb + Figure 1 Overall Arhiteture 3. IMPLEMENTATION 3.1 Hardware Charateristis Our prototype ipleenting digital low-power SHM is based on the TMS32F2812 EVM fro Texas Instruents [5]. TMS32F2812 is a 32-bit fixed point DSP supporting up to 15 illion instrutions per seond (MIPS) operation. The axiu ore operating lok frequeny is 15 MHz and an be redued down to 15 MHz by hanging the phase loked loop (PLL) ultiplier setting. The peripheral lok frequeny an be seleted as high as the ore operating lok frequeny or as low as the ore operating lok frequeny divided by 14. The supply voltage for the DSP ore is 1.8 V at 13 MHz and 1.9 V at 15 MHz. For Input/Output utilization, the supply voltage is 3.3 V, while the reoended supply voltage for the entire EVM is 5 V. Our digital low-power algorith relies on binary signaling rather than ultiple voltage levels for strutural exitation, requires siple auulation instead of FFT operations whih involves intensive ultipliations for signature generation, and takes advantage of subtration instead of a square root operation for daage etri alulations. Hene, we an eploy a low-power, relatively slow 32-bit fixed point DSP, while the previous sin wavefor based prototype required a power-hungry 225 MHz 64-bit floating point DSP. In addition to the DSP, there are two ore IC devies involved for PZT exitation and sensing operation. The exitation and sensing operation requires two buffers, a oparator, and an Opap. A four-hannel Opap OPA4342 fro Texas Instruents is eployed to ipleent two buffers and a oparator, and a single-hannel Opap TLV277 fro Texas Instruents is adopted for the Opap [6-7]. Soe isellaneous oponents, suh as resistors and an LED, are also inluded. One buffer is onneted between the digital output fro the DSP and the PZT on the easuring path, and the other buffer is onneted between the digital output fro the DSP and the digital input to the DSP on the referene path to avoid loading effets. If a buffer is not inserted between two oponents on a signal path, a voltage drop ours due to the voltage dividing between the output ipedane of the oponent transitting the signal and the input ipedane of the oponent reeiving the signal. Thus, a buffer, whose ideal input ipedane is infinite and ideal output ipedane is zero, is inserted between the to ensure axiu voltage transfer. A oparator is onneted to the output of the Opap to onvert the strutural response into a digital signal to be easured by the DSP. This oparator perfors the funtion of a buffer as well. In the previous prototype, we did not have to insert buffers beause the DAC EVM and ADC EVM had buffers on-board. For this digital ethod prototype, we effetively replae high-power onsuing DAC EVM and ADC EVM with a buffer and a oparator, whih resultantly redues power dissipation signifiantly and iniaturizes the for fator. The prototype is shown in Figure 2. TMS32F2812 EVM is 7.62 X 12.7, and the external bread board onsists of Opap ICs, resistors and an LED. The LED is turned on and off to indiate strutural daage based on the detetion result alulated by the DSP. Pro. of SPIE Vol O-3

4 Figure 2 Prototype using TMS32F2812 EVM 3.2 Test Struture and Detetion Frequeny Range To verify the funtionality and evaluate the perforane of the prototype, we oposed a test struture as shown in Figure 3. The test struture onsists of three aluinu beas of the sae diension but in different ehanial daage states. The exat diensions of three beas and their daage are illustrated in Figure 4. The first bea without a hole represents a healthy referene ondition, and the other two beas with a hole in the iddle deonstrate daage on the struture. These three beas are onneted to a rotary swith, so by rotating the swith a struture with a different ehanial ondition an be seleted. As opposed to reovable daage, suh as tightening and loosening bolts or applying agnets, a struture with peranent daage that an be hosen using a swith provides us the exat sae ehanial harateristis of healthy or daaged strutural onditions throughout the test bl bl ow ow Figure 3 Test struture 2ILflCIflLG IFJ!CKUG22 bl IFJ!CKUG22 ww Figure 4 Test struture diension (not in sale) Sine the DSP utilized in our prototype has liited data eory size, it is effiient to fous on a frequeny range sensitive to the strutural exitation. Ipedane analysis is perfored on the PZT bonded to the test struture using a HP 4194A ipedane analyzer to deterine the detetion frequeny range. The ipedane easureent frequeny range is fro 1 Hz to 1 KHz with a frequeny step size of 1 Hz. To alleviate noise effets, 35 easureents were taken, and the axially ourring value was seleted at eah frequeny through a histogra analysis. Values of resistane and reatane, the real and iaginary parts of the easured ipedane, at three different strutural onditions are shown in Figure 5 and Figure 6, respetively. After analysis, it is observed that the frequeny range fro 12 KHz to Pro. of SPIE Vol O-4

5 25 KHz is highly sensitive to exitation, and different daage harateristis alter the ipedane at ertain frequenies by arbitrary aounts. Therefore, based on this easured ipedane, the detetion frequeny range for the prototype is seleted as 12 KHz to 25 KHz. (Oh) (Oh) (Oh) Resistane (Real Part of the Ipedane) 1 Healthy Daage Daage Frequeny (Hz) Figure 5 Resistane (real part of the ipedane) (Oh) (Oh) (Oh) Reatane (Iaginary Part of the Ipedane) -5 Healthy Daage Daage Frequeny (Hz) Figure 6 Reatane (iaginary part of the ipedane) 3.3 Frequeny Resolution The frequeny resolution in the detetion frequeny range ainly depends on the available data eory size and the peripheral lok frequeny. Meory allowane for user data in TMS32F2812 is bit. Sine a signature is an enseble average of ertain nuber of variation ounts, a ertain nuber of onseutive variation ounts at eah frequeny oponent should be stored in the eory. The baseline, urrent signature, and the differene between the also have to be stored for a daage etri alulation. Thus, the required eory spae N e is N = (3 + N ) N (1) e avg freq where N avg is the nuber of variation ounts per signature and N freq is the nuber of frequeny oponents per variation ount. Setting N avg as eight, we obtain the axiu nuber of frequeny oponents per variation ount N freq,max as 87 fro the following relationship. N freq, MAX 96 = = 87 (3+ 8) The exitation frequeny is ontrolled by hanging the pulse width of the PWM output, and the pulse width is anaged by dereenting the nuber of peripheral lok yles per pulse. For exaple, when the default lok onfiguration is used, the peripheral lok frequeny is 75 MHz. As the pulse width of the lowest frequeny oponent 12 KHz is 83 µse and that for the highest frequeny oponent 25 KHz is 4 µse, the nuber of peripheral lok yles per pulse width is 625 and 3, respetively. To iniize the oputational oplexity of alulating the pulse width for eah frequeny oponent, the nuber of peripheral yles per pulse width is dereented by a onstant aount, instead of alulating dereent yles to generate linearly inreasing exitation frequeny. As the axiu nuber of frequeny oponents per variation ount alulated based on the eory allowane is 87 fro equation (2), the iniu dereent of pulse width, in ters of the nuber of peripheral lok yles N plk,min, is N plk, MIN ( Nplk, low Nplk, high) (625 3) = = = 38 N 87 freq, MAX where N plk,low and N plk,high are the nuber of peripheral lok yles for the lowest detetion frequeny and the highest detetion frequeny. N plk,low and N plk,high are 625 and 3, respetively, in this exaple. (2) (3) Pro. of SPIE Vol O-5

6 Figure 7 shows the nuber of peripheral lok yles versus alulated exitation frequeny and the frequeny resolution at eah exitation frequeny oponent. Sine the nuber of peripheral lok yles is dereented linearly, the exitation frequeny does not linearly inrease. The frequeny resolution inreases as the exitation frequeny inreases instead of providing a onstant frequeny resolution within the detetion frequeny range. The average frequeny resolution through the exitation frequeny range is 151 Hz, in this exaple Exitation Frequeny (Hz) Frequeny Resolution (Hz) Period (# peripheral lok yles) Exitation Frequeny (Hz) Figure 7 Exaple alulated exitation frequenies and frequeny resolution Peripheral lok frequeny is 75 MHz and the nuber of frequeny oponents in the detetion frequeny range is PERFORMANCE ANALYSIS 4.1 Daage Detetion To prove the daage detetion apability of the presented digital low-power prototype, easureents have been prefored with varying ore operating lok frequenies and peripheral lok frequenies. As a referene perforane for verifiation purposes, RMSD values are alulated fro the easured ipedane shown in Figure 5. The real part of the ipedane is used as it reflets the strutural daage ore learly than iaginary part of the ipedane [8]. The alulated RMSD value for Daage 1, whih is the iddle bea with a saller hole in Figure 3, is 98.16, and that for Daage 2, whih is the first fro the right with a larger hole, is Therefore, we are expeted to observe larger daage etri fro Daage 1 than fro Daage 2, as well as larger daage etri fro daaged struture than fro the healthy struture. For this experient, the nuber of saples, equivalent to four periods of the exitation signal with the lowest detetion frequeny, is output through the PWM. The tie period of eah exitation frequeny reains the sae to exite the struture with the sae aount of the energy for eah frequeny oponent. Table 1 suarizes the daage etri with different ore operating lok frequenies and peripheral lok frequenies. The peripheral lok frequeny was kept as the default value. For eah etri shown, the daage etri was easured ten ties, and the average of the ten alulations is displayed. Coparing the daage etri of the daaged strutures to that of healthy struture, we an observe that the peripheral lok frequenies fro 75 MHz to 7.5 MHz an detet daage as expeted in aordane with the RMSD values alulated fro the easured ipedane. Also notieable is the iniu ore operating lok frequeny of 15 MHz an fully support all operations for exitation signal generation and daage assessent. Pro. of SPIE Vol O-6

7 Table 1 Core operating lok frequeny and daage detetion perforane Core Operating Clok Peripheral Clok Daage Metri (MHz) (MHz) Healthy Daage 1 Daage Sine it was shown that the slowest operating lok frequeny an support the digital low-power algorith, another experient was perfored at the slowest operating lok frequeny while varying the peripheral lok frequeny. Table 2 shows the daage etri oparison with lower peripheral lok frequenies at a 15 MHz ore operating lok frequeny. The nuber of frequeny oponents and pulse width dereent are alulated based on equation (1) and equation (3), and the average frequeny resolution is onsequently deterined. Clearly, the peripheral lok frequeny of 1.25 MHz still an detet daage, and only 55 frequeny oponents in the 12 KHz to 25 KHz detetion frequeny range, with an average frequeny resolution of 24 Hz, are suffiient for daage detetion. Core Operating Clok Peripheral Clok Table 2 Peripheral lok frequeny and daage detetion perforane Daage Metri # Frequeny Coponents Pulse Width Dereent Average Frequeny Resolution (MHz) (MHz) Healthy Daage 1 Daage 2 (# Peripheral Clok Cyles) (Hz) Power Dissipation Power dissipation with different ore operating lok frequenies is opared as shown in Table 3. The power dissipation was alulated based on the easured urrent dissipation and the EVM supply voltage. When the ore operating lok frequeny is 15 MHz, the power dissipation is ranged fro 1.7 W to 1.8 W depending on the strutural ondition. When there is daage on the struture, the indiation LED is turned on, and the power dissipation inreases by 15 W. It is notieable that the whole SHM syste an operate under 1 W with a ore operating lok frequeny of 15 MHz, regardless of the existene of daage on the struture. Even when the LED is on, the power dissipation is only 9 W. The total power dissipation will be further redued when we enlose the isellaneous external iruitry on to a single PCB and utilize iniaturized oponents, suh as surfae ount resistors and LEDs as well as sall outline pakaging for Opap ICs. In our previous prototype, it was observed that the power dissipation inrease by turning on a surfae ount LED was insignifiant. Table 3 Core operating lok frequeny and power dissipation Core Operating Clok Supply Voltage Current Consuption Power Consuption (MHz) (V) (A) (W) LED Off LED On LED Off LED On Pro. of SPIE Vol O-7

8 The power dissipation of our previous prototype using sin exitation ipleented on ultiple evaluation boards is opared with that of the presented digital low-power prototype. For a fair oparison, the power dissipated for exitation signal generation, sensor atuation and sensing, and daage assessent are opared. The previous prototype inorporates a DSP EVM, a DAC EVM and an ADC EVM, while the presented prototype involves a DSP EVM with isellaneous supporting iruitry. As suarized in Table 4, the previous prototype onsues total 4.1 W. Under an assuption that the struture reains in healthy status ost of the tie, the typial power dissipation of the presented prototype is 79 W, whih is only 2 % of the total power dissipation of the previous prototype. By adapting the digital low-power SHM algorith, the power dissipation fro the ADC and DAC has been opletely eliinated, and the siple algorith ade it possible to use a lower perforane DSP to derease the power dissipation fro the DSP itself. Table 4 Power dissipation oparison Coponent Power Dissipation (W) Previous Sin Exitation Presented Digital Exitation DSP DAC.75 N/A ADC 1.68 N/A Total CONCLUSION We have presented the ipleentation of a self-ontained digital low-power SHM syste using a DSP EVM. The digital low-power algorith apitalizes on a digital retangular pulse train for strutural exitation and easures the strutural response in a digital forat to eliinate the use of both a DAC and ADC. The DAC is effetively replaed by a buffer, and a oparator substitutes the ADC. The typial power dissipation is 79 W, whih is only 2 % of the power dissipation of our previous prototype. The 8 % redution on the power dissipation is obtained by developing the SHM syste on one board with isellaneous external iruitry eliinating DAC and ADC. Another fator reduing the power dissipation is the relaxed ore operating lok frequeny ahieved by siplifying the exitation signal generation and daage assessent operation. Measureent results obtained using the test struture proved that the developed SHM prototype provides reliable perforane. This prototype utilizing digital low-power SHM algorith suessfully deonstrated the feasibility of syste-on-board ipleentation of the SHM syste. ACKNOWLEDGEMENT This aterial is based upon work supported by the National Siene Foundation under Grant No Any opinions, findings, and onlusions or reoendations expressed in this aterial are those of the authors and do not neessarily reflet the views of the National Siene Foundation. REFERENCES 1. B.L. Grisso and D.J. Inan, Developing an Autonoous On-Orbit Ipedane-Based SHM for Theral Protetion Systes, International Workshop on Strutural Health Monitoring, pp , Septeber D.J. Inan and B.L. Grisso, Towards Autonoous Sensing, SPIE International Syposiu on Sart Strutures and Materials, vol. 6174, pp , February J. Ki, B.L. Grisso, D.S. Ha, and D.J. Inan, All-Digital Low-Power Strutural Health Monitoring Systes, IEEE Conferene on Tehnologies for Hoeland Seurity, May T.G. Overly, G. Park, C.R. Farrar, and R.J. Alleang, Copat hardware Developent for SHM and Sensor Diagnostis using Adittane Measureents, SEM International Modal Analysis Conferene, February TMS32F2812 Digital Signal Proessor Data Manual, Texas Instruents In., May OPA4342 Low-Cost, Low-Power, Rail-to-Rail Operational Aplifiers, Texas Instruents In., August 2. Pro. of SPIE Vol O-8

9 7. TLV277x Faily of 2.7-V High-Slew-Rate Rail-to-Rail Output Operational Aplifiers with Shutdown, Texas Instruents In., February G. Park, H. Sohn, C.R. Farrar, and D.J. Inan, Overview of Piezoeletri Ipedane-Based Health Monitoring and Path Forward, The Shok and Vibration Digest, vol. 35, no. 6, pp , Noveber 23. Pro. of SPIE Vol O-9