A High-Speed Low-Complexity Modified Processor for High Rate WPAN Applications

Transcription

1 IEEE TRASACTIOS O VERY LARGE SCALE ITEGRATIO (VLSI) SYSTEMS, VOL. 21, O. 1, JAUARY [4] J. A. de Lima and C. Dualibe, A linearly tunable low-voltage CMOS transconductor with improved common-mode stability and its application to gm-c filters, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 48, no. 7, pp , Jul [5] U. Yodprasit and C. C. Enz, A 1.5-V 75-dB dynamic range third-order Gm/C filter integrated in a 0.18 m standard digital CMOS process, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp , Jul [6] L. Acosta, M. Jiménez, R. G. Carvajal, A. J. López-Martín, and J. Ramírez-Angulo, Highly linear tunable CMOS Gm-C low-pass filter, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 10, pp , Oct [7] A. Zeki, Low-voltage CMOS triode transconductor with wide-range and linear tunability, Electron. Lett., vol. 35, no. 20, pp , Sep [8] R. G. Carvajal, J. Ramírez-Angulo, A. J. López-Martín, A. Torralba, J. A. Galan, A. Carlosena, and F. M. Chavero, The flipped voltage follower: A useful cell for low-voltage low-power circuit design, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, pp , Jul [9] Z. Y. Chang, D. Haspeslagh, and J. Verfaillie, A highly linear CMOS Gm-C bandpass filter with on-chip frequency tuning, IEEE J. Solid- State Circuits, vol. 32, no. 3, pp , Mar [10] J. Silva-Martínez, M. S. Steyaert, and. C. Sansen, A 10.7 MHz 68-dB SR CMOS continuous-time filter with on-chip automatic tuning, IEEE J. Solid-State Circuits, vol. 27, no. 12, pp , Dec A High-Speed Low-Complexity Modified Processor for High Rate PA Applications Taesang Cho and Hanho Lee FFT Abstract This paper presents a high-speed low-complexity modified radix point fast Fourier transform (FFT) processor using an eight data-path pipelined approach for high rate wireless personal area network applications. A novel modified radix 2 FFT algorithm that reduces the hardware complexity is proposed. This method can reduce the number of complex multiplications and the size of the twiddle factor memory. It also uses a complex constant multiplier instead of a complex Booth multiplier. The proposed FFT processor achieves a signal-to-quantization noise ratio of 35 db at 12 bit internal word length. The proposed processor has been designed and implemented using 90-nm CMOS technology with a supply voltage of 1.2 V. The results demonstrate that the total gate count of the proposed FFT processor is 290 K. Furthermore, the highest throughput rate is up to 2.5 GS/s at 310 MHz while requiring much less hardware complexity. Index Terms Fast Fourier transform (FFT), modified radix 2,orthogonal frequency-division multiplexing (OFDM), wireless personal area network (PA). I. ITRODUCTIO ith the ever increasing demand for multimedia applications using wireless transmissions over short distances, the millimeter wave (mmave) 60 GHz wireless personal area network (PA) has been intensively researched for many years. Currently, the IEEE Task Group ad (IEEE ad) is developing a standard for the Manuscript received July 18, 2011; revised ovember 11, 2011; accepted December 07, Date of publication February 03, 2012; date of current version December 19, This work was supported by Inha University. The authors are with the Department of Information and Communication Engineering, Inha University, Incheon , Korea ( hhlee@inha.ac.kr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TVLSI mmave wireless local area network (LA) and PA systems. 1 High rate PA systems will be provided for various high speed multimedia applications such as home network systems and real time video streaming services in short range indoor environments. One key advantage of IEEE ad over the other standardization activities in the 60 GHz arena is that it builds on the existing strong market presence of i-fi in the 2.4/5 GHz bands. In the PHY layer design of high rate PAs, the orthogonal frequency division multiplexing (OFDM) modulation has been adopted, and the fast Fourier transform (FFT) processor is a key component. The FFT/IFFT processor has a high hardware complexity in the OFDM modulation of high rate PA systems. One OFDM symbol in the IEEE ad standards consists of a length of 512 subcarriers. Therefore, FFT processor conducts the FFT computation with 512-point arithmetic and should provide a high throughput rate of at least GS/s. In recent years, there has been some research in the design of multi-path pipelined FFT processors that provide a high throughput [1] [7]. Many FFT processor architectures are introduced in order to utilize the OFDM transmission, such as a single path delay commutator (SDC), multi-path delay commutator (MDC), single path delay feedback (SDF), and multi-path delay feedback (MDF). Among the various FFT architectures, the MDF architecture is frequently used as a solution to provide a throughput rate of more than 1 GS/s [3] [5]. However, for applications that provide a throughput rate of over 2 GS/s, the number of data-paths can be increased to 8 or 16, which increases the hardware cost. The area becomes even larger because the memory modules are duplicated for the 16 data path approach. In order to reduce the area and power consumption, several FFT algorithms and dynamic scaling schemes have been proposed [2] [6]. The radix of the algorithm greatly influences the architecture of the FFT processor and the complexity of the implementation. A small radix is desirable because it results in a simple butterfly. evertheless, a high radix reduces the number of twiddle factor multiplications. The radix r k algorithms simultaneously achieve a simple butterfly and a reduced number of twiddle factor multiplications [8]. The radix-2 algorithm is a well known simple algorithm for FFT processors, but it requires many complex multipliers. The radix-4 algorithm is primarily used for high data throughput FFT architectures, but requires a 4-point butterfly unit with high complexity. Recently, the radix FFT algorithm and architecture have been studied in order to reduce the number of complex multipliers [2], [4]. In this brief, a novel modified radix FFT algorithm and a 512-point FFT/IFFT processor architecture, which can provide a high throughput of 2.5 GS/s and SQR of 35 db for16-qam applications, are proposed. The key concepts for achieving a high data throughput, reduced hardware complexity and higher SQR performance are described. The organization of this brief is as follows. Section II describes the proposed modified radix02 5 FFT algorithm, and Section III describes the proposed 512-point radix02 5 FFT architecture. In Section IV, the implementation and comparison are presented. Finally, conclusions are provided in Section V. II. MODIFIED Radix FFT ALGORITHM A discrete Fourier transform (DFT) of length is defined as follows: 01 X(k) x(n) nk ; k 0; 1;...;0 1 (1) n0 1 [Online]. Available: /$ IEEE

2 188 IEEE TRASACTIOS O VERY LARGE SCALE ITEGRATIO (VLSI) SYSTEMS, VOL. 21, O. 1, JAUARY 2013 where is the twiddle factor and denotes the th primitive root of unity, with its exponent evaluated modulo. k is the frequency index and n is the time index [2]. The radix 0 2 k algorithm has the same butterfly structure regardless of the k value. However, the twiddle factor multiplication structure is varied with a factor k. The 512-point FFT computation with radix02 k algorithm consists of nine arithmetic stages. The radix 0 2 k algorithm is formulated using k-dimensional linear index mapping. The radix algorithm can be expressed as various formulas using a common factor algorithm. The radix algorithm is given as follows. Applying a 6-D linear index map n 1 ;n 2 ;n 3 ;n 4 ;n 5 0; 1 n 2 n1 + 4 n2 + 8 n n n5 +n6 n 6 0; 111; k hk 1 +2k 2 +4k 3 +8k 4 +16k 5 +32k 6i k 1 ;k 2 ;k 3 ;k 4 ;k 5 0; 1 k 6 0; 111; 0 1: (2) 32 The radix algorithm is reformulated into two decomposing methods (Method 1 and Method 2), which are called the modified radix algorithm. The common factor algorithm takes the form of X(k 1 +2k 2+4k 3 +8k 4+16k 5+32k 6) n 0 n 0 n 0 n 0 n 0 n 0 2 x 2 n n n n n 5 +n 6 nk 01 n 0 J (n 6 ;k 1 ;k 2 ;k 3 ;k 4 ;k 5 ) n (k +2k +4k +8k +16k ) 2 n k : (3) The method 1 of the modified radix algorithm is expressed as follows: ( n + n + n + n + n +n )(k +2k +4k +8k +16k +32k ) Stage 1TF Stage 2TF n (k +2k ) 8 Stage 1BU Stage 2BU Stage 3TF Stage 4TF (2n +n )(k +2k +4k ) 3 Stage 3BU Stage 5BU Stage 5TF Stage 4BU n (k +2k +4k +8k +16k ) n k : (4) The signal flow graph for the Method 1 of the 64-point modified radix algorithm is shown in Fig. 1(a). The common factor algorithm using other factoring method takes the form of X(k 1+2k 2 +4k 3+8k 4 +16k 5+32k 6) n 0 n 0 n 0 n 0 n 0 n 0 Fig. 1. Signal flow graph of (a) Method 1, (b) Method 2 for the 64 point modified radix 2 algorithm. 2x 2 n n n n n 5 +n 6 nk 01 n 0 K (n 6 ;k 1 ;k 2 ;k 3 ;k 4 ;k 5 ) n k n k : (5) The Method 2 of the modified radix algorithm is expressed as follows: ( n + n + n + n + n +n )(k +2k +4k +8k +16k +32k )

3 IEEE TRASACTIOS O VERY LARGE SCALE ITEGRATIO (VLSI) SYSTEMS, VOL. 21, O. 1, JAUARY TABLE I SEQUECE OF THE 512-POIT FFT TIDDLE FACTOR COMPUTATIO FOR RADIX-2 FFT ALGORITHMS TABLE II HARDARE COMPLEXITY COMPARISO OF THE EIGHT PARALLEL DATA-PATH 512-POIT MDF FFT PROCESSORS Stage 1TF Stage 2TF (2n +n )(k +2k ) 16 Stage 1BU Stage 3TF Stage 2BU Stage 4TF (16n +n )(k +2k +4k +8k ) Stage 3BU Stage 5TF Stage 4BU Stage 5BU n k 2 n k : (6) Fig. 1(b) shows a signal flow graph for the Method 2 of the 64-point modified radix algorithm. Each method has butterfly computation and twiddle factor multiplication at each stage. Equations (4) and (6) show the butterfly stages and twiddle factor multiplications of each stage. The twiddle factors n 32 and n 16 in (4) and (6) have complex numbers. If each radix decomposing methods (Method 1 and Method 2) are used independently for the 512-point FFT computation, the number of twiddle factor multiplications tends to increase. However, the number of twiddle factor multiplications can be reduced by combining the Methods 1 and 2 of the modified radix algorithm, which is called mixed method. Table I shows the sequence of the 512-point FFT twiddle factor computation at each stage for the several radix02 k FFT algorithms. Generally, programmable complex multiplier is used for complex multiplications; however, if the twiddle factor has a small number of coefficients, then the complex constant multiplier can be used for the twiddle factor multiplications. The complex multiplication of the twiddle factors, n 32, n 16, and n 8, can be implemented in the canonic signed digit (CSD) constant multiplier, which contains the fewest number of non-zero digits [10]. Hence, the area and power consumption of the complex multipliers can be reduced. The radix algorithm has similar complex multiplication pattern repeatedly every five stages. A 512-point FFT computation using radix algorithm consists of nine stages. As shown in Table I, the stage 2 in Method 2 has twiddle factor 16, which has higher hardware complexity compared to 8 in Method 1. Stages 7 and 8 in Method 1 has twiddle factors 8 and 32, which require higher hardware complexity compared to 16 in Method 2. Thus, the first five stages and the other three stages use Method 1 and Method 2, respectively to reduce the hardware complexity of complex multipliers, as shown in Table I. Table II shows a comparison of the hardware complexity for several eight parallel data-path 512-point radix 0 2 k MDF FFT architectures. Compared with the conventional architectures, the proposed architecture requires only a half of the number of complex Booth multipliers. In addition, the twiddle factor LUT requires a much smaller size compared to the other radix 0 2 k algorithms. To compare the hardware complexity, the complex multipliers were synthesized and then the area CR denotes the complex registers in the feedback path. CA denotes the complex adders. CBM denotes the complex Booth multiplier. CCM denotes the complex constant multiplier. A denotes the normalized area. of each multiplier was normalized. If it is assumed that the area of the complex Booth multiplier is 1, then the normalized area of the complex constant multipliers for the twiddle factor multiplications of 8, 16, and 32 is 0.12, 0.28, and 0.46, respectively. The results show that the proposed FFT processor using the mixed method of the modified radix algorithm has the lowest total normalized area of complex multiplier and smallest LUT size of twiddle factor. Thus, it has best area efficiency as compared to the other FFT processors. III. PROPOSED ARCHITECTURE In this brief, an eight parallel data-path 512-point modified radix FFT processor is proposed, as shown in Fig. 2. There are two modules based on the modified radix02 5 algorithm that reduce the number of twiddle factor multiplications. The first module, which consists of five processing elements (PEs), is realized using Method 1 of the modified radix algorithm, and the second module is realized using Method 2. The proposed architecture consists of butterfly units, complex Booth multipliers, complex constant multipliers, first-in first-out (FIFO), and a control unit. A. Butterfly Units The butterfly units shown in Fig. 3 perform complex additions and subtractions of two input data: x[n] and x[n + 2]. The behavior of the butterfly units is as follows. All input values are saved into the FIFO until the 2 th input is entered. Then, the butterfly units conduct calculations between the input values and FIFO outputs, after entering the (2) + 1 st input. During the last 2 clock cycles, all butterfly calculations are performed at each stage. Among the butterfly outputs, the complex addition outputs are fed to the next stage. And, the complex subtraction outputs are saved in the FIFO, and then during the next 2 clock cycles, the FIFO outputs are fed to the next stage. Butterfly

4 190 IEEE TRASACTIOS O VERY LARGE SCALE ITEGRATIO (VLSI) SYSTEMS, VOL. 21, O. 1, JAUARY 2013 Fig. 2. Block diagram of the proposed eight parallel data-path 512-point modified radix 2 FFT/IFFT processor. Fig. 3. Block diagram of (a) butterfly unit 1 (BU1), (b) butterfly unit 2 (BU2). unit 1 (BU1) conducts complex additions and subtractions only. However, butterfly unit 2 (BU2) includes twiddle factor 4 multiplication utilizing the multiplexers and control signals. B. Complex Booth Multiplier ith Error Compensation The twiddle factor multiplication is conducted using fixed width complex multipliers. The twiddle factor values stored in the read-only memory (ROM) are used as the multiplicand in the complex Booth multiplier. The modified Booth algorithm is used widely for high speed multiplications. Since the maximum clock rate of the FFT processor depends on the critical path of the complex Booth multiplier, three-level pipelined complex Booth multiplier is used for high-speed operation. Because quantization errors affect the signal-to-noise ratio (SR) performance of the system, an error compensation method [9] is used to reduce the quantization error. C. Complex Constant Multiplier The proposed FFT processor uses constant multipliers based on the canonical signed digit (CSD) representation for the complex multiplication arithmetic in stages 2, 3, and 7. The twiddle factor 8 has only one coefficient, but twiddle factors 16 and 32 have three and seven coefficients, respectively. Mostly the existing research is using complex Booth multipliers for the twiddle factor 32 multiplication. However, in our design, the complex CSD constant multiplier has been used for the twiddle factor 32 multiplication. Also, the common sub-expressions sharing (CSS) technique reduces the hardware complexity Fig. 4. Constant multiplier for twiddle factor multiplications (,, and ). of the complex CSD constant multipliers [10], as shown in Fig. 4. The constant multiplier using the CSS technique is implemented using the common calculation patterns X1, X2, and X3. The proposed FFT processor applied CSD constant multiplier instead of complex Booth multiplier at several stages. Thus, the hardware complexity of complex multiplier is decreased by at least 54% in comparison with using complex Booth multiplier. In addition, the twiddle factor LUT size is reduced to 50% compared to the designs using the complex Booth multipliers. IV. RESULTS AD COMPARISO The appropriate word length and quantization error performance evaluation of the proposed FFT processor is determined using a fixed-point simulation prior to the hardware implementation. In the fixed-point simulation result, the output SR was saturated at a 12-bit word length; thus, the 12-bit word length was determined in both real and imaginary parts. The SQR can reach 35 db for 16-QAM

5 IEEE TRASACTIOS O VERY LARGE SCALE ITEGRATIO (VLSI) SYSTEMS, VOL. 21, O. 1, JAUARY modulation with a 12-bit word length without using a data scaling approach. Although the data scaling approach provides a higher SQR performance with a lower internal word length, it requires a data scaling block in each stage which involves higher hardware complexity. The architecture of the proposed FFT/IFFT processor was designed in Verilog HDL and simulated to verify its functionality. Both the simulation and synthesis steps were performed using the SYOPSYS design tool and 90 nm CMOS technology optimized for a 1.2 V supply voltage. Table III shows the performance comparisons between the proposed FFT/IFFT processor and the existing FFT/IFFT processors for PA applications [3], [5], [6]. The results show that the proposed FFT processor obtains much better SQR performances compared with those of previous FFT processors. The proposed processor has 290 K gate count and the operating clock frequency is 310 MHz. The core area of the proposed architecture is 0.78 mm 2 after layout. The throughput rate of the proposed architecture is up to 2.5 GS/s at 310 MHz, which is enough to meet the specification of IEEE ad standard. Both designs presented in [3] and [5] are 2048-point FFT processors for OFDM-based PA applications, which do not target the existing specific standards. Although the number of parallel data-paths in the proposed design is double than that of the four parallel 2048-point FFT processor presented in [3], the proposed architecture requires only 80% core area, which indicates a more competitive and lower hardware complexity as compared to the conventional architectures. Also, considering the proposed architecture obtains a much better SQR performance for the supporting 16-QAM modulation, the core area of the proposed architecture requires only 67% of the size of the existing eight parallel data-path 2048-point FFT processor [5]. V. COCLUSIO In this paper, the modified radix algorithm and the eight parallel data-path 512-point modified radix FFT processor have been proposed with 2.5 GS/s for OFDM-based PA applications. The number of complex Booth multipliers and twiddle factor LUTs are reduced using the modified radix algorithm. The proposed modified radix FFT processor is the most area-efficient architecture for the eight parallel 512-point MDF FFT processors. The highest throughput rate is up to 2.5 GS/s at the clock frequency of 310 MHz. In addition, SQR can reach 35 db for 16-QAM modulations with a 12 bit word length. The proposed architecture has potential applications in high-rate OFDM-based PA systems. REFERECES [1] Y. Lin, H. Liu, and C. Lee, A 1-GS/s FFT/IFFT processor for UB applications, IEEE J. Solid-State Circuits, vol. 40, no. 8, pp , Aug TABLE III PERFORMACE OF THE PROPOSED FFT PROCESSOR COMPARED ITH PREVIOUS IMPLEMETATIOS [2] J. Lee and H. Lee, A high-speed two-parallel radix 2 FFT/IFFT processor for MB-OFDM UB systems, IEICE Trans. Fundam., vol. E91-A, no. 4, pp , Apr [3] Y. Chen, Y. Tsao, Y. ei, C. Lin, and C. Lee, An indexed-scaling pipelined FFT processor for OFDM-based PA applications, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 2, pp , Feb [4] M. Shin and H. Lee, A high-speed four-parallel radix 2 FFT processor for UB applications, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2008, pp [5] S. Tang, J. Tsai, and T. Chang, A 2.4-GS/s FFT processor for OFDMbased PA applications, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 6, pp , Jun [6] S. Huang and S. Chen, A green FFT processor with 2.5-GS/s for IEEE c (PAs), in Proc. Int. Conf. Green Circuits Syst. (ICGCS), 2010, pp [7] T. Cho, H. Lee, J. Park, and C. Park, A high-speed low-complexity modified radix 2 FFT processor for gigabit PA applications, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2011, pp [8] A. Cortes, I. Velez, and J. F. Sevillano, Radix FFTs: Matrical representation and SDC/SDF pipeline implementation, IEEE Trans. Signal Process., vol. 57, no. 7, pp , Jul [9] K. Cho, K. Lee, J. Chung, and K. Parhi, Design of low-error fixedwidth modified booth multiplier, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp , May [10] R. I. Hartley, Subexpression sharing in filters using canonic signed digit multipliers, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 43, no. 10, pp , Oct