A Partially Operated FFT/IFFT Processor for Low Complexity OFDM Modulation and Demodulation of WiBro In-car Entertainment System

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1 D.-S. Kim et al.: A Partially Operated FFT/IFFT Processor for Low Complexity OFDM Modulation and Demodulation of WiBro In-car Entertainment System A Partially Operated FFT/IFFT Processor for Low Complexity OFDM Modulation and Demodulation of WiBro In-car Entertainment System 4 Dong-Sun Kim, Member, IEEE, Seung-Yerl Lee and Duck-Jin Chung, Member, IEEE Abstract Wireless broadband (WiBro) systems can provide high data rate wireless internet access with personal subscriber station under the stationary or mobile environment. It is the orthogonal frequency division multiple access (OFDMA) in time division duplex (TDD) system with 6 useful subcarriers over a nominal bandwidth of.5 MHz at. GHz band and each frame is composed of 4 OFDM symbols, corresponding to 5ms. For modulation and demodulation in the WiBro communication system, the fourier fast transform (FFT) processing is the most speed and power consumption critical path. In this paper, we describe 496 points FFT and inverse FFT processor for mobile in-car entertainment systems. To obtain low complexities, small computation power and distributed memory, partially operated over-sampling architecture is developed to meet the requirement of non-stopping and high-speed data throughput. From experiment results, we can show that our methods reduce the complexity about.% and it is suitable to implementation in mobile devices for WiBro consumer application which is required small area and low-power such as multimedia data service. Index Terms FFT algorithm, OFDMA, broadband mobile internet access, VLSI. I. INTRODUCTION Recently, the demand for portable internet service with high quality multimedia data via various mobile terminals such as notebook PCs, PDAs and cellular phones at anywhere and anytime is rapidly increasing. Such strong market needs are leading the innovation of standard and technology that enables physically distant users to have access to the high-speed broadband wireless service with a relatively inexpensive cost comparing to existing cable and satellite solutions. Because the current cellular system and wireless local area network (WLAN) have many limitations to the meet demand for portable internet access, the IEEE has finalized the.6e standard, which specifies a set of different physical (PHY) and medium access control (MAC) layers of mobile broadband wireless access systems [], []. Wireless broadband (WiBro) system is a subset of IEEE.6e standard and stably provides all-ip packet services, such as streaming video, music, and broadcasting at ground speeds up to 6km/h. Among Dong-Sun Kim is with the Department of Advanced Mobile Technology Research Center, Korea Electronics Technology Institute, Korea ( dskim@ keti.re.kr). Seung-Yerl Lee and Duck-Jin Chung are with the school of Information and Communication Engineering, INHA University, Incheon, Korea. Contributed Paper Manuscript received April 4, 9 6//$. IEEE various physical layer schemes to organize a frame in.6e, WiBro system only adopts orthogonal frequency division multiple access (OFDMA) in time division duplex (TDD) mode. The TDD frame length is 5 ms and segmented into the sequence of small fixed duration logical units, called symbols. The frame structure is fixed as symbols for the downlink subframe and 5 symbols for the uplink subframe [4], [5]. WiBro system supports seamless IP-based service while users move from one cell to other and Fig. shows an in-car entertainment consumer application based on WiBro system for providing multimedia data service. In-car entertainment system using WiBro will make possible to provide perfect TV, video, music and internet service everywhere on the road under cars driving even more than 6km/h. In OFDMA systems, inverse FFT (IFFT) and FFT are used to realize multi-carrier modulation and demodulation, which greatly reduces the complexity of OFDM systems [5]. FFT and IFFT directly affect the accuracy of the channel estimation and symbol demapper. As the data transmission rate of OFDMA systems increases, generating OFDMA symbols with high data rate requires very high speed FFT processor [6], []. In case of WiBro communication system, it needs 4 FFT and IFFT computation during a 5ms frame time. In this reason, efficiently implementing the FFT/IFFT processor with low power and high speed is very important especially for some mobile instruments [], []. For FFT and IFFT implementation for OFDMA systems, pipelining can deal with the data throughput in real-time [9], while it consists of log r N stages for radix-r and each stage has one butterfly Fig.. In-car entertainment system using WiBro computation unit, one commutator shift register and one complex twiddle multiplier. Therefore, the pipelining leads to much more silicon area [6]-[]. In this paper, we propose a partially operated IFFT and FFT architecture for low complexities, small

2 4 IEEE Transactions on Consumer Electronics, Vol. 54, No., MAY computation power and distributed memory. We also present 496 points over-sampling IFFT and FFT to remove the aliasing and signal distortion for removing digital filter in conventional 4 points WiBro systems. This paper is organized as follows. In section II, the algorithm and architecture of partially operated over-sampling IFFT and FFT processor is described. The complexity and computation of proposed architecture are evaluated in Section II. Section III explains implementation results and conclusions are presents in section IV. II. A PARTIALLY OPERATED OVER-SAMPLING IFFT AND FFT PROCESSOR A. Partially Operated IFFT Algorithm and Architecture The proposed architecture is basically radix single delay feedback (R SDF) which is the most commonly used and has the smaller computation for multiplication and addition than other algorithms in IFFT and FFT processor [9], []. The R SDF consists of three radix single delay feedback (RSDF) and one constant multiplier as shown in Fig.. The N-point inverse discrete fourier transform (IDFT) is defined as N = nk π x ( n) X ( k) W N, W N = exp j () k= N (b) R SDF architecture Fig.. The basic architecture of proposed IFFT and FFT processor x '( n, k 4 x '( n, n, n, k x '( n, n x '( n, n, n, n ) = k = k = k= k = x( k, k x '( n, n, n, k x '( n, k x '( n, n nk n n nk n k k kkk 496 nk k 5 nk 64 From Eq. (4), we can suppose that each equation corresponds to R SDF and the first equation only performs RSDF operation. Therefore, Eq. (4) can be represents into data flow as shown in Fig. and Fig. 4 shows the architecture of partially operated IFFT processor. (4) Where W N is the twiddle factor, N is the IFFT length. Since the proposed IFFT only used 4 effective data of 496, the Eq. () can be described as x ( n) X ( k) W, k =,,,...,, n =,,,..., 495 () = k= nk 496 In order to decompose the proposed IFFT using R SDF algorithm covering point, we apply 4-dimemsional linear index map and the indexes n and k are represented as n = 5n + 64n + n + n, n = n = n = n =,,,..., () k = 5k + 64k + k + k, k =,, k,,,..., = k = k = Substituting the Eq. () for () and we can obtain below derivation [5]. j Fig.. Data flow a partiaaly operated IFFT (a) RSDF architecture

3 D.-S. Kim et al.: A Partially Operated FFT/IFFT Processor for Low Complexity OFDM Modulation and Demodulation of WiBro In-car Entertainment System 4 Fig. 4. Architecture of proposed IFFT processor The total radix- stage for 496 points IFFT is in conventional R SDF method. Since the input number of oversampling IFFT is 4 data and the rest is value, first and second stage only processes the data counterpart or j without conventional radix- butterfly operation. The rest stages of IFFT are operated by the same method of conventional R SDF IFFT. Therefore, the proposed IFFT architecture needs just radix- stage. Because butterfly operation and memory accessing of first and second stages is not used, it reduce two complex adders,,44 real additions and 4 memories. As shown in Fig. 4, the role of data commutator is storing the serial data of next IFFT symbol in the SRAM during the current symbol of 4 data is stored in the SRAM. Input data stored in SRAM is directly distributed into every butterfly of third stage except of first and second stages. Therefore, input value of third stage is X()- X(), X()-X(5), (X(5)-X() j, X()-X(), X()-X(5) and (X(5)-X() j. B. Partially Operated FFT Algorithm and Architecture The effective data number of FFT operation input is 496 and it is differ from IFFT operation. After FFT operation, the effective data number of post-fft stage is 4 and discrete fourier transform (DFT) can be represented as Using the characteristic of index k is or and the index k of FFT output is just from to, the data flow of proposed FFT can be decided as shown in Fig. 5. The part- in stage presents effective input data of current butterfly for next stage and part- shows the non-existing data. The dashed lines between stages show the input and output of butterfly operation in 496 points over-sampling FFT. Because the effective output data is X() to X() and it is a decimation in frequency (DIF) [], the required butterfly operation is just dotted box except of first and second stage. The butterfly operation in first and second stage is similar with conventional 496 points R SDF FFT algorithm []. However, proposed partially operated FFT algorithm can ignore the second output of butterfly operation, because the data of index 4 to 495 in second stage and the data of index 4 to 495 is not exist. Due to such characteristic, the proposed partially operated FFT has the similar computation with 4 points FFT and the memory for FFT pipelining is not required as conventional 496 point FFT processor. Fig. 6 shows the memory accessing of proposed FFT architecture. Since the second output of butterfly operation need not to be stored in memory, butterfly operation of stage in stage can use the memory of stage and the third stage butterfly operation is possible to use the memory of stage as shown in Fig. 6. Memory accessing from next stages need to have 496 FFT memory size Since memory accessing of the fourth stage and next symbol in stage is overlapped. Fig. shows the proposed FFT architecture using modified R SDF. The dotted line and circle show that some butterfly operation in R SDF is unnecessary. A. Computation and complexity analysis of IFFT and FFT Several architectures have been proposed for the pipelined FFT processor such as multi-path delay commutator (MDC), single delay feedback (SDF) and single delay commutator (SDC) []-[]. Among several pipelined FFT, R SDF has X ( k) x( n) W, n =,,,..., 495, k =,,,..., (5) = 495 n= nk 496 The indexes n and k for FFT is same as Eq. () and the FFT derivation is as follows 4 4 4, n, n, n, k, n, n, n, k ) = n = n = n = n = x( n, n, n, n, n kn, n, n, n, k, n, n kn kn kn knnn 496 knn 5 kn 64 (6) 496 stage 4 5 part- : existing data for butterfly operation part- : non-existing data Fig. 5. Data flow of proposed FFT algorithm Authorized licensed use limited to: Inha University. Downloaded on July, at :5: UTC from IEEE Xplore. Restrictions apply.

4 44 IEEE Transactions on Consumer Electronics, Vol. 54, No., MAY reached the minimal requirements of not only complexity but also computation of multiplication and addition. Table I and Table II show the complexity and computation of proposed IFFT and FFT. It is compared with conventional SDF pipelined FFT with 4 point and 496 point. One complex multiplication is processed by 4 real multiplications and real additions. For one constant multiplication of twiddle factor, ±. ±. j, it needs real multiplications and real additions. Table show that the adder of proposed IFFT and FFT is smaller than conventional FFT algorithms with 496 point and the memory size is approximately half of conventional FFT algorithms. The multiplication of proposed IFFT is same as the conventional FFT with 496 points and the addition is smaller than conventional FFT as shown in Table II. But, the multiplication of proposed FFT is preferably smaller than 4 points and the addition is larger than 4 points FFT. TABLE I COMPLEXITY COMPARISON OF PROPOSED IFFT AND FFT complex multiplier complex adder memory RSDF 4 point 496 point point 4 R SDF 496 point point R SDF 496 point Proposed IFFT Proposed FFT 559 TABLE II COMPUTATION COMPARISON OF PROPOSED IFFT AND FFT real multiplication real addition RSDF[6] 4 point point point 6 54 R SDF[] 496 point point R SDF[] 496 point 44 9 Proposed IFFT Proposed FFT (a) Proposed FFT architecture (b) Modified R SDF Fig.. The proposed FFT architecture and modified RSDF algorithm. III. EXPERIMENTS RESULTS Fig. shows block diagram of WiBro OFDM modulation and demodulation block using partially operated oversampling IFFT and FFT, windowing, cyclic prefix (CP) block and control block. In case of downlink, the received 4 I/Q data from channel coding block enter in IFFT block and IFFT operation is processed with zero data. Output data of IFFT block are transmitted using. GHz radio frequency (RF) by way of CP insertion and windowing block. In case of uplink, received CP I/Q data from radio frequency (RF) block is removed and entered in FFT block. The FFT outputs of index to are used by the post-fft stage such as demodulation and channel decoding. Fig. 6. Memory accessing of proposed FFT Fig.. OFDM modulation and demodulation in WiBro systems

5 D.-S. Kim et al.: A Partially Operated FFT/IFFT Processor for Low Complexity OFDM Modulation and Demodulation of WiBro In-car Entertainment System Table III shows the FPGA implementation results of conventional and proposed over-sampling IFFT/FFT for WiBro OFDMA system. The proposed methods reduce the complexity about.% than conventional method. We fully test the WiBro FFT/IFFT evaluation board for in-car entertainment system and Fig. 9 shows the evaluation results of FPGA prototype board. TABLE III FPGA IMPLEMENTATION RESULTS multiplier RAM slice 45 (a) Prototype evaluation Board Conventional method Proposed method filter IFFT/FFT total 6 56 Proposed 496 IFFT 4 Proposed 496 FFT 5 (b).45ghz uplink RF spectrum IV. CONCLUSION WiBro systems are recently attached for portable packet service such as streaming video, music, online gaming and broadcasting. In this paper, we proposed a partially operated over-sampling IFFT and FFT for low complexity WiBro in-car entertainment systems. Proposed FFT and IFFT architecture remove the interpolation filter for RF and reduce the implementation complexity of OFDMA system. Therefore, proposed partially operated over-sampling IFFT and FFT is also suitable for portable terminal device such as notebook PC, PDAs and cellular phones for WiBro applications. Pilot signals (c) Downlink transmit signals QPSK symbols Pilot signals REFERENCES [] Angela Doufexi, David Redmill, David Bull, and Andrew Nix, MPEG- Video Transmission using the Hiperlan/ WLAN Standard, IEEE Trans. Consumer Electronics, vol. 4, no., pp. 54-6, Aug.. [] Tanmoy Debnath, Nicola Cranley, and Mark Davis, Experimental Comparison of Wired versus Wireless Video Streaming over IEEE.b WLANs, Irish Signals and Systems Conference, pp. 5-4, June 6. [] Yifeng He, Ivan Lee, Xijia Gu, and Ling Guan, Centralized Peer-to- Peer Video Streaming over Hybrid Wireless Network, IEEE International Conference on Multimedia and Expo, pp , July 5. [4] IEEE P.6e/D, Air Interface for Fixed and Mobile Broadband Wireless Access Systems: Amendment for Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands, IEEE, April 5. [5] [6] Xiaojin Li, Zongsheng Lai, and Jianmin Cui, A Low Power and Small Area FFT Processor for OFDM Demodulator, IEEE Trans. Consumer Electronics, vol. 5, no., pp. 4-, MAY. [] Haining Jiang, Hanwen Luo, Jifeng Tian, and Wentao Song, Design of an Efficient FFT processor for OFDM Systems, IEEE Trans. Consumer Electronics, vol. 5, no. 4, pp. 99-, Nov. 5. [] Chi-Hong Su, and Jen-Ming Wu, Reconfigurable FFT Design for Low Power OFDM Communication Systems, IEEE Trans. Circuits Syst. Video Technol., vol. 6, no., pp. 9-99, Apr. 6. (c) Uplink received signals Fig. 9. Evaluation results of prototype board Authorized licensed use limited to: Inha University. Downloaded on July, at :5: UTC from IEEE Xplore. Restrictions apply.

6 46 IEEE Transactions on Consumer Electronics, Vol. 54, No., MAY [9] Hasan, M., Arslan, T. and Thompson, J. S., A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications, IEEE Trans. Consumer Electronics, vol. 49, no., pp. -4, Feb.. [] Y Jung, H. Yoon, and J. Kim, New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications, IEEE Trans. Consumer Electronics, vol. 49, no., pp. 4-, Feb.. Dong-Sun Kim (M 99) was born in Incheon, Korea, in 9. He received the B.S and M.S degrees in the school of Electronics and Electrical Engineering in 99 and 999, respectively, from INHA University, Incheon, Korea. On 5, he received Ph.D. degree in the school of Information and Telecommunication Engineering from INHA University, Incheon, Korea. Since 999, he was with the Korea Electronics Technology Institute (KETI), Gyeonggi-do, Korea and working on R&D at the Advanced Mobile Technology Research Center, where he currently is a senior researcher and team leader. He is a member of IEEE. His research interests are in the areas of wireless/wired communication systems, wireless sensor network, VLSI & SoC design, multimedia codec design, the computer architecture and the embedded system design. Seung-Yerl Lee received the B.S. and M.S degrees in the school of Information and Telecommunication Engineering from the INHA University, Korea, in and 5, respectively. He is currently a Ph.D. candidate in the school of Information and Telecommunication Engineering in INHA University. His research interests are the wireless communication hardware design, WPAN, WLAN and VLSI & SoC design. Duck-Jin Chung was born in Korea on Feb., 94. He received the B.S degree from the Seoul National University of Electrical Engineering, Korea on 9, and M.S. degree from Utah State University on 94. On 9, he received Ph.D. degree from University of Utah. He is currently a professor at the school of Information and Communication Engineering of INHA University, Incheon, Korea. He is a member of IEEE. His research interests are the VLSI & SoC design, the computer architecture and the embedded system design.