Design of Reconfigurable FFT Processor With Reduced Area And Power

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1 Design of Reconfigurable FFT Processor With Reduced Area And Power 1 Sharon Thomas & 2 V Sarada 1 Dept. of VLSI Design, 2 Department of ECE, 1&2 SRM University Sharonthomas05@gmail.com Abstract Fast fourier transform (FFT) is an efficient implementation of the discrete fourier transform (DFT). The main objective of the project is to implement a reconfigurable FFT processor with reduced power and area in order to provide system designers and engineers with the flexibility to meet different system requirements. This paper proposes a low power and area efficient FFT architecture using Single Delay Feedback (SDF). The proposed methodology is based on Radix factorization which is the main technique for achieving high energy efficiency with flexibility, followed by architecture parallelism. The flexibility is provided by reconfigurable processing units that support radix-2/4/8/16 factorizations. An FFT processor design methodology with optimal power-area trade-off using feasible parallel architectures and radix factorizations is obtained. I. INTRODUCTION Orthogonal frequency division multiplexing (OFDM) technologies have become more and more significant in modern communication systems. The key concept of OFDM technique makes use of the multicarrier modulation. OFDM signal consists number of subcarriers that are modulated by using phase shift keying (PSK) or quadrature amplitude modulation (QAM).Nowadays, OFDM technique is widely used for high-speed digital communications, such as xdsl, DAB, DVB-T/H, and WLAN. The OFDM technique is advantageous because it uses channels efficiently, overcomes multi-path fading, and has simpler equalizers. For WiMAX system, the OFDM technology can increase the efficiency of spectrum utilization and provide the transmission capability in the non-line-ofsight (NLOS) environment. In OFDM system, Discrete Fourier transform (DFT)/Inverse-DFT is used andsystems need the FFT and IFFT processors to perform real-time operations for the orthogonal multicarrier modulations and demodulations. Since DFT/IDFT computation requires a huge amount of arithmetic operations, we need an efficient FFT algorithm which can reduce the number of arithmetic operations to meet real time computation in OFDM systems. There are many types of FFT architectures used in OFDM systems. They are mainly categorized into three types namely the parallel architecture[1],the pipeline architecture[2] and the shared memory architecture[lee et al. 2006]. The high performance of a parallel and pipelined architecture is achieved by having more butterfly processing units but they consume larger area than the shared memory architecture. On the other hand, the shared memory architecture requires only one butterfly processing unit and has the advantage of area efficiency. But the shared memory architecture has a drawback of low throughput and requires a complex circuit design of memory address controller. Fortunately, the lower throughput of the shared memory architecture increases dramatically if the high radix algorithm is used. But the high radix algorithm has defects of more complex memory scheme and FFT n length (N) must be only powers of radix- r r. The pipelined FFT/IFFT processor architecture which has been designed in OFDM communication system has been studied since the 1970 s. There are many kinds of the methods to implement the FFT hardware architecture. All hardware implementations of pipelined FFT can be categorized into three kinds of pipelined architectures, which include multiple delay commutator (MDC), single delay commutator (SDC), and single delay feedback (SDF) architectures. Among three pipelined architectures, the SDF architecture is more suitable and its advantages are listed as follows, (1) The SDF architecture is very convenient to implement the different length FFT. (2) The number of the required registers in SDF architecture is\ smaller 81

2 than that in MDC and SDC structures. (3) The controller of SDF architecture is easier than the other structures. We propose an FFT design methodology that jointly considers algorithm, architecture, and circuit parameters. We contribute with insights on how to use FFT radix structure for highly energy- and area efficient implementations. Hundreds of architectures for 128- to 2048-point FFT exist by varying the degree of parallelism and radix factorization, as will be explained in this paper. Apart from parallelism and radix, delay buffers need to be efficiently implemented. Memory size partition and memory elements for delay lines of different lengths are evaluated. Our approach provides a cross-layered FFT design methodology to jointly optimize above parameters. For illustration, we will design for minimum power-area product (PAP). We will show an FFT processor that achieves the lowest energy per FFT operation, comparable area and much fewer processing cycles as compared to prior work. This paper is organized as follows. II. FFT ALGORITHMS The N -point discrete Fourier transform (DFT) of an input sequence is defined as (1) Where k=0,1,2... N-1 and W N = e -j2 π/n is known as twiddle factor. Direct implementation requires N 2 complex multiplication and N(N-1) complex additions. In case of radix-4 decimation-in-time FFT We split or decimate the N-point input sequence into four subsequences, x(4n),x(4n+1), x(4n+2), x(4n+3), n = 0, 1,..., N/4-1. The numbers at the input represent the index of the input sequence, whereas those at the output are the frequencies, of the output signal X[k]. Finally, each number =nk, in between the stages indicates a rotation As a consequence, samples for which do not need to be rotated. Likewise, if the samples must be rotated by 0, 270, 180, and 90, which correspond to complex multiplications by 1, -j, 1 and j, respectively. These rotations are considered trivial, because they can be performed by interchanging the real and imaginary components and/or changing the sign of the data. A. Reconfigurable Architecture Based on the pipelined SDF architecture, a reconfigurable FFT architecture can be implemented by cascading several radix-2 4 stages in order to accommodate different FFT sizes. The signal-flow graphs for radix-2 to radix- 2 4 butterflies are shown in Fig. 2. The minus signs in the butterfly modules are omitted for simplicity. The highlighted inter-stage multiplications are implemented as constant (complex) multipliers as opposed to using full (complex) multipliers. The radix-2 4 can be realized by cascading several atomic processing units (PUs) as in Table I. The PUs are shown in Fig. 3. Looking at the cost of the constant multipliers (shown in brackets in Fig. 2) in terms of the number of equivalent adders, we discovered that radices beyond are impractical, because the increasing number and complexity of required constant multipliers makes them no longer advantageous over full multipliers. In addition, full multipliers need extra ROMs to store the coefficients as opposed to locally computed coefficients of constant multipliers. Therefore, radix-2 to radix-2 4 is the proper level of granularity for mixed-radix FFT implementations. Fig 2. Various radix butterfly operations. 82

3 As shown in Fig. 3(a), each PU contains a basic butterfly module and a set of constant multipliers. The butterfly module is initialized to the data-switch mode until the delay buffers are loaded by the valid inputs and then switched to the butterfly mode for FFT operation. The required constant multipliers for PUs 1 4 are shown in Fig. 3(b). Only half the twiddle factors (dark-filled circles) are generated in the PUs, the other half (grayfilled circles) are created using the symmetry property. The PUs with lower index can be deduced from the Pus with higher index. For example, PU4 can serve as PU3, PU2 or PU1. This back-compatibility is useful for reconfigurable designs. All the intra-stage multipliers inside the PUs for a -point FFT are constant multipliers. Full multipliers are only used for the inter-stage twiddle factors. Since the inter-stage full multipliers cost more than the intra-stage constant multipliers, radix factorization should minimize the number of full multipliers. and a lower clock frequency improve the energy efficiency of a parallel architecture. Since timemultiplexing is inherently applied to SDF architecture, parallelism is used to improve its energy efficiency and adjust the design point in the area-energy delay plane [8]. Fig 3. Reconfigurable processing units III. POWER AND AREA MINIMIZATION We propose a systematicmethodology to explore FFT powerarea tradeoff. FFT realizations are systematically explored in three steps. First, architecture parallelism combined with FFT decomposition is used to explore the power-area space. radix factorization is explored for a given FFT size. The third step consists of shift and add module of multiplier implemented using canonic signed digit representation. A. Parallel Architecture with FFT Decomposition Parallelism is an effective technique to increase throughput [10] or to reduce power consumption of an FFT processor. For a fixed throughput, scaled voltage Fig. 4. (a) Reference N -point N=MxL FFT architecture. (b) A P way parallel architecture requires replicas of the L -point FFT. (c)when (P=L), the L-point FFT can be shared across the P streams, which leads to a reduced hardware area. An area-efficient parallel architecture is possible by leveraging FFT decomposition. As shown in Fig. 4(a), an N -point FFT is decomposed into M -point FFT and L -point FFT. Straightforward P-way parallel architecture, Fig. 4(b), requires P M -point FFTs And P L -point FFTs, increasing the area by a factor of (neglecting the overhead of the serial-to-parallel and parallel-to-serial blocks). When P =L, the single-input SDF FFTs can be combined into a single -input parallel FFT, as in Fig. 4(c), to reduce area. This architecture simplification is possible since the M -point FFTs can be computed first and combined into the L-point (L=N/M) output stage to compute an N-point FFT. B. Shift Add Module of a Multiplier The block diagram of the shift add module shown in fig.3performs multiplication by shift and adds method. higher-radix structures can be made more area efficient by judiciously replacing full multipliers with constant multipliers. These constant multipliers are implemented using canonic signed digit (CSD) representation as shown in Fig. 3. The canonical signed digit (CSD) representation is one of the existing signed digit (SD) representations with unique features which make it useful in certain DSP applications focusing on low- power, efficient-area and high-speed arithmetic [1]. 83

is, two nonzero digits are not adjacent. The first property implies a minimal Hamming weight, which leads to a reduction in the number of additions in arithmetic operations.

4 The CSD code is a ternary number system with the digit set {1 0 1}, where 1 stands for 1. Given a constant, the corresponding CSD representa- tion is unique and has two main properties: (1) the number of nonzero digits is minimal, and (2) no two consecutive digits are both nonzero, that is, two nonzero digits are not adjacent. The first property implies a minimal Hamming weight, which leads to a reduction in the number of additions in arithmetic operations. The second property provides its uniqueness characteristic. How- ever, if this property is relaxed, this representation is called the minimal signed digit (MSD) representation, which has as many nonzeros as the CSD representation, but which provides multiple representations for a constant A 10-bit twiddle factors are assumed shown in table1. Each of the constant factors requires no more than 4 additions, which leads to a large area reduction. The area of constant multipliers is minimized using the symmetry property of twiddle factors and sharing of common sub-expressions. Twiddle Factor CSD realization No. Of adders ( )-( ) Table1: CSD realization of twiddle factors 4 Fig 4: butterfly module IV. PROPOSED ARCHITECTURE A reconfigurable FFT processor using SDF architecture is designed and implemented which is can b used as FFT core in 3GPP LTE standard. The proposed architecture satisfies the requirements of 3GPP LTE wireless standard with reduced area and power. Starting from FFT decomposition and architecture parallelism, the maximum-size 2048-point FFT is decomposed into M=256 and L=8 to achieve minimum power area product The 8-path 256-point SDF FFT architecture is shown in Fig. 5. It can support 16 to 256 points by reconfiguring the data-path inter-connection between the PUs. To support 1536 points, a 6-point FFT module is constructed by sharing hardware resources with the 8- point FFT. Fig 3.Constant multipliers use canonic signed digit (CSD) C. Butterfly module The butterfly expressions shown in fig.4 are implemented here. Two complex numbers(a+bj) and (c+dj) are used as inputs. Adders and inverters were used to get outputs ( a + c ), (a - c ), ( b + d), ( b d ). The real and imaginary equations were computed simultaneously and in parallel with just inputs a, b, c, d. The output from stage1 was then multiplied with the twiddle co-efficient, shuffled using a shuffling unit and then sent to stage2 that will calculate the equations in a similar fashion. Fig 5. Block Diagram of proposed architecture Proposed architecture is reconfigurable point FFT architecture as shown in fig 5. The method called architecture parallelism is used to achieve this. In architecture parallelism an N point FFT is divided into M and L point FFT (N=M*L). For P way parallel architecture, first stage comprises of P M- point FFTs and second stage with P L- point FFTs. When P=L, the single input SDF FFTs can be combined into a single L 84

input parallel FFT. The first stage pipelined 256 point FFT is reconfigurable to support 16-256 points. The second stage parallel FFT support 8 or 6 points.

fourier transform (FFT) based on various radix technique that performs pipelining, which achieve drastic performance improvement.

5 input parallel FFT. The first stage pipelined 256 point FFT is reconfigurable to support points. The second stage parallel FFT support 8 or 6 points. The overall FFT meets the 3GPP-LTE standard specification (128, 256, 512, 1024, 1536, 2048 points). V. SIMULATION AND IMPLEMENTATION Fig.6 Modelsim Output. fourier transform (FFT) based on various radix technique that performs pipelining, which achieve drastic performance improvement. For randomly generated test examples, we showed that the proposed method compute FFT in a effective way to achieve maximum speed of computation. VII. REFERENCES 1. Chia-Hsiang Yang, Tsung-Han Yun and Dejan Marković, Power and Area Minimization of Reconfigurable FFT Processors : A 3GPP-LTE Example, IEEE Journal of solid state circuits,vol.47,no.3,march Reza Sadegh Azad, A custom FFT hardware accelerator for wave fields synthesis MSc thesis 3. Magandeep Kaur, Pragathi Kapoor, Analysis of R2 2 SDF pipelined architecture in VLSI, IJESAT,vol2 may Guatavo A. Ruiz, Mercides Granda Efficient canonic signed digit recording ELSVIER microelectronics journel. 5. Y.-T. Lin, P.-Y. Tsai, and T.-D. Chiueh, Lowpower variable-length fast Fourier transform processor, IEE Proc. Comput. Digit. Tech., vol. 152, no. 4, pp , Jul K. K. Parhi, VLSI Digital Signal Processing Systems. NewYork: Wiley, S. W. Reitwiesner, Binary arithmetic, Advances in Computers, pp , A. Wenzler and E. Luder, New structures for complex multipliers and their noise analysis, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 95), May 1995, vol. 2, pp Fig.7 Hardware Implementation of Shift Add Module VI. CONCLUSION An FFT processor design methodology yielding optimal power-area tradeoff is explored by examining feasible parallel architectures and radix factorizations. The use of constant multipliers for intra-stage twiddle factors enables substantial area and power savings compared to the use of full multipliers. Radix factors up to 16 should be used. Radices beyond 16 are ineffective due to a large number of constant multipliers required. In this paper we developed highly reconfigurable radix and multiplier less arithmetic operations. After completing the arithmetic design we carried out a Fast 85

A Novel Approach in Pipeline Architecture for 64-Point FFT Processor without ROM

A Novel Approach in Pipeline Architecture for 64-Point FFT Processor without ROM A.Manimaran, Dr.S.K.Sudheer, Manu.K.Harshan Associate Professor, Department of ECE, Karpaga Vinayaga College of Engineering