An Efficient FFT Design for OFDM Systems with MIMO support

Transcription

1 An Efficient FFT Design for OFDM Systems with MIMO support Maheswari. Dasarathan, Dr. R. Seshasayanan Abstract This paper presents the implementation of FFT for OFDM systems to process the real time high speed data streams. It is based on Radix- 2 2 single path delay feedback architecture supporting single and multiple input data streams (MIMO). The proposed design also provides flexibility in adjusting the resolution of FFT computation. The supported FFT resolutions are 64, 256, 1024 and 4096 points. Efficiency is achieved by means of reducing a real multiplier in complex multiplication. The hardware description is developed using Verilog and synthesized using Xilinx Virtex 5 FPGA family, achieving an operating frequency of 157MHz for 1024 point FFT size. Keywords Fast Fourier Transform (FFT), Radix 2 2 Single Path Delay Feedback (SDF), Orthogonal Frequency Division Multiplexing (OFDM), Multiple-Input Multiple-Output (MIMO), configurable resolution M I. INTRODUCTION OBILE high speed application uses Orthogonal Frequency Division Multiplexing (OFDM), which is famous for its robustness against frequency selective fading channel. OFDM is a multi-carrier modulation scheme which divides a high bit rate data stream into multiple parallel low bit rate streams modulated to different carrier tones. The orthogonal property between the tones is achieved by selecting the sub-carries whose frequency satisfies the integer number of cycles in the symbol period, with inter-carrier spacing equal to the ratio of bandwidth, BW to the number of sub-carriers, N. OFDM uses multiple access technique called Orthogonal Frequency Division Multiple Access (OFDMA), where by multiple users are allocated different subsets of OFDM tones exploiting frequency diversity, multiple user diversity thus improving the system capacity [8]. It is observed that the OFDM signal is equivalent to the inverse discrete Fourier transform (IDFT) of data samples take N at a time, thus making the implementation of OFDM system easier in discrete time using inverse fast Fourier transform (IFFT) and fast Fourier transform (FFT). The size of FFT is determined by the key parameters like protection against Maheswari Dasarathan is with the College of Engineering, Anna University, Chennai, Tamil Nadu, India, pursuing the Masters in Applied Electronics ( mahe.dasarath@gmail.com). Dr. R. Seshasayanan is with the College of Engineering, Anna University, Chennai, Tamil Nadu, , India. He is the Assistant Professor with the Department of Electronics and Communication ( seshasayanan@annauniv.edu). multipath, Doppler shift, and design cost/complexity. Though larger FFT size reduces sub-carrier spacing yielding protection against multi-path delay spread, is vulnerable to inter-carrier interference owing to Doppler spread. Hence the selection of FFT size should balance the influence of all the key parameters. To enable the system to operate at high data rate applications like video streaming, with constrained power resource, low power techniques are adopted in the proposed design. Moreover OFDM systems aimed at interoperability the implementation with lesser gate count is inevitable. The support for different FFT resolutions becomes important when the OFDM receiving system experiences handovers across base stations operating at different bandwidths. The proposed design incorporates data reordering buffer, which enables the reuse of design for IFFT applications [6]. Also the design handles multiple data streams from different receive antennas, which make the design suitable for MIMO systems. Thus the proposed design is based on Radix 2 2 architecture with other significant features, making it efficient. The next section describes the architecture, followed by the support for MIMO 2Rx configuration in section III. Section IV describes the handling of different FFT sizes with the same hardware. Section V adds details on the inbuilt testability support. Section VI details the hardware implementation of the design in VERILOG Hardware Description Language. Finally we conclude with the synthesis results of 1K FFT. II. ARCHITECTURE A. Radix 2 2 FFT Algorithm The Discrete Fourier Transform (DFT) X(k), k=0,1,2, N-1 of a sequence x(n), n=0,1,2, N-1 is defined as: NN 1 XX(kk) = xx(nn). WW NN nnnn Where N is the transform size, j = 1 nn =0 (1) WW NN = ee jj 2ππ NN According to the decomposition method of [1] that done by substituting with, and 70

2 nn = NN 2 nn 1 + NN 4 nn 2 + nn 3 NN TABLE I TEST MODE SELECTION VIA IO PADS kk = kk 1 + 2kk 2 + 4kk 3 NN IO PAD[1:0] value Description This yield NN 4 1 nn 3.kk 3 2 b00 Normal Mode 2 b01 Mode with Impulse Input 2 b10 Mode with rectangle Input 2 b11 Mode with Ramp Input XX( kk 1 + 2kk 2 + 4kk 3 ) = HH(kk 1, kk 2, nn 3 ). WW NN nn 3 (kk 1 +2kk 2 ). WW NN 4 nn 3 =0 Where, (2) HH(kk 1, kk 2, nn 3 ) = xx(nn 3 ) + ( 1) kk 1xx nn 3 + NN 2 + ( jj) (kk 1+2kk 2 ) xx nn 3 + NN 4 + ( 1) kk 1. xx nn 3 + 3NN 4 (3) On simplification, the resultant is the set of four DFTs of length N/4. Each term in equation (3) represent a Radix-2 butterfly (BFI), and the whole equation also represents Radix- 2 butterfly (BFII) with the trivial multiplication by j. A hardware oriented Radix 2 2 algoritm is developed by integrating a twiddle factor decomposition technique in divide and conquer approach to the algorithm to the cascading delay feedback structure [2] [4]. III. MIMO The concept of MIMO (Multiple Input, Multiple outputs) is well applied in wireless communication to reduce the error rate by combining the signals from multiple receive chains as in Fig. 1. In order to support this feature the FFT module should handle the incoming signals from multiple receive chains separately [9]. In the proposal each Radix 2 2 butterfly, BF-I and BF-II shown in the diagram, include two separate buffers respective to the receive chains. Fig. 1 MIMO Model The proposed architecture is implemented for the samples of the input chains arrive at FFT in interleaved manner as shown in Fig. 2. This enables to distinguish the sample of the respective input chain and passed through the appropriate buffers provided in each of the butterfly stages. Fig. 2 Interleaved Data Stream for 2Rx IV. CONFIGURABLE FFT POINTS In order to target wide range of applications, it is necessary to have flexible configuration of FFT resolution [3]. Depending on the OFDM application domain the FFT size varies, ADSL (512 points), VDSL (8192/4096/2048/1024/512 points), DVB-T (2048/8192 points), DVB-H (4096 points), IEEE a (64 points), IEEE a WiMAX (256/512/1024 points) and LTE (128/256/512/1024/2048 points). The different FFT sizes involve different number of stages to transform the input samples. The proposed architecture deploys five stages required to support the maximum FFT size, 4096 points. To perform the transformation for the lower FFT size the input samples are fed directly to the i th FFT stage bypassing the initial stages as shown in Fig. 7. This gives the flexibility to support different FFT sizes with same hardware. V. INBUILT TEST SIGNAL GENERATION The proposed design includes test signal generation logic which is used as the input vector in the test mode. Impulse, rectangle and ramp signals are the supported test signals. Two IO PADs are required for supporting the test mode. The selection of test mode and the test signals are encoded as shown in Table I. This feature reduces the validation efforts, thus resulting in a smart testing at the cost of extra hardware. VI. HARDWARE ARCHITECTURE The hardware structure of single butterfly stage is shown in Fig. 3. Each stage has two input data bus each 10bits, for real and imaginary part of the sampled signal. 71

3 DRAIN state the input samples of the next set is not expected. Fig. 3 Single Butterfly stage hardware structure The BF I and BF II are the butterfly structures, controlled by the state machine BF-FSM shown in Fig.4. The Twiddle ROM addresses generation logic takes care of selecting the appropriate twiddle ROM for the configured FFT size. The sample counter counts the input sample and helps in proper state transitions of the butterfly state machines as shown in Fig.4. The complex multiplier is implemented using three real multipliers as shown in Fig.8. The samples are buffered at each butterfly structures inside the butterfly RAMs. The design is parameterized in order to support different FFT resolution. The parameters include FFT_MODE, FFT_SIZE, DATA_WIDTH, BFI_RAM_DEPTH, BFII_RAM_DEPTH, TW_ROM_DEPTH, etc. A. The Butterfly FSM The FFT controller state machine keep track of the sample count and undergo state transition across the stages: IDLE, STORE, COMPUTE and DRAIN. B. BF I and BF II structure with MIMO support The hardware architecture of BFI and BFII supporting two receive chains is shown in Fig.5 and Fig.6. In BFI structure the sample routing muxes and demuxes at the input and output of the BF_RAMs are controlled based on c2 and c3 control signals while the computation unit is controlled by c1 control signal. The control signals are issued by the BFI controller. Depending on the programming of number of receive chains the extra BF_RAMs are enabled. WiMAX supports 1Rx and 2Rx, LTE supports 1Rx, 2Rx and 4Rx. Based on the requirement extra buffers can be extended to the existing BF structure. Fig. 5 BFI structure with 2 Rx support Since the handling -1, +j and -j multiplication is handled inside the BFII structure, two control signals c1 and c2 are used in the basic computation unit. The muxes and the demuxes are controlled by c3 and c4 control signals. The product with -j term is implemented by swapping the real and imaginary part considering the sign of the sample. Fig. 4 Butterfly Controller State Machine When no samples arrive the state machine is in IDLE state. Until N/2 samples [0: N/2-1] the state machine keeps buffering the data in the BF_RAMs, and it said to be in STORE state. On the N/2 sample arrival the state machine transits to COMPUTE state where the buffered sample 0, say a, and the new sample N/2, say b, enters the computation part of the butterfly unit. The output of each computation cycle result in two output (a+b) and (a-b), out of which a+b leaves for the next stage, while a-b is buffered again in the same location in the BF_RAM. This computation continues till N-1th sample. From (N-1) to (N+N/2-1) the state machine enters the DRAIN state where the already computed values inside the buffer gets drained out. During this phase the counter keeps running based on the FFT clock. During the Fig. 6 BFII structure with 2 Rx support 72

4 Fig.7 FFT Hardware supporting multiple resolutions stages [7]. C. Simplification to Complex Multiplication The complex multiplication is implemented using three real multipliers [5], thus reducing the hardware and the power. The simplification is as follows. A+ jb = (X+ jy) (L+ jm) Real Part: A = ( L M ) Y + L ( X Y ) Imaginary Part: B = ( L + M ) X - L ( X - Y ) Fig. 8 Complex Multiplier Hardware VII. RESULTS AND DISCUSSIONS The design is implemented using Xilinx ISE 12.1 tools for synthesis in a Virtex 5 FPGA and simulation. The synthesis results are shown in Table I and II. The maximum operating frequency of 157MHz is achieved for 1K FFT implementation. The RTL implementation was verified with the MATLAB model for different input data. The performance of the proposed design is analyzed at data width set to 10bits. For applications requiring better bit error rate (BER) a higher data width can be selected. The synthesis snapshots are added in Fig.9 and Fig.10. Fig. 9 Synthesis Snapshot TABLE II DEVICE UTILIZATION SUMMARY ON 5VLX220TFF Logic Utilization Used Available Utilization Number of slice registers % Number of slice LUTs % Number of Bounded IOs 4 6 6% Number of Block RAM/FIFOs % Number of BUFG/BUFGCTRLs % Number of DSP48Es % VIII. CONCLUSION AND FUTURE WORK This paper presented a very efficient FFT architecture based on Radix 2 2 algorithm. A fully pipelined processing core of configurable FFT resolutions 64-point, 256-point, point and 4096 point FFT sizes. The synthesis results demonstrate the high operating frequency and low latencies for both FPGA and VLSI implementations. Future work includes the improvement to current architecture with low power design methodologies [3] like clock gating and using single twiddle table across all FFT TABLE III TIMING SUMMARY ON 5VLX220TFF Timing Summary Maximum Frequency Maximum Period Minimum Input arrival time Minimum output required time after clock Hz/ns MHz 6.346ns 2.561ns 2.826ns 73

5 Fig. 10 Design Summary REFERENCES [1] S. He and M. Torkelson, A new approach to pipeline FFT processor, in Proc. 10 th Int. Parallel Processing Symp./ 1996, pp [2] K. Harikrishna, T. Rama Rao, and Vladimir A. Labay, FPGA Implementation of FFT Algorithm for IEEE e (Mobile WiMAX), International Journal of Computer Theory and Engineering, vol. 3, No. 2, April [3] Muniandi Kannan, and Srinivasa Srivatsa, Hardware Implementation Low Power High Speet FFT Core, International Arab Journal of Information Technology, vol. 6. No. 1, January [4] Ahmed Saeed, M. Elbably, G. Abdelfadeel, and M. I. Eladawy, Efficient FPGA implementation of FFT/IFFT Processor, International Journal of circuits, systems and signal processing, vol. 3, [5] Siva Kumar Palaniappan, and Tun Zainal Azni Zulkifli, Design of 16- point Fast Fourier Transform in 0.18um CMOS Technology, American Journal of Applied Sciences 4(8); , [6] M. Mohamed Ismail, M. J. S. Rangachar, and Ch. D. V. Paradesi Rao, An Area Efficient Mixed-Radix 4-2 Butterfly with Bit Reversal for OFDM Application, European Journal of Scientific Research, ISBN X vol. 40 No. 4 (2010), pp [7] Chen- Fong Hsiao, Yuan Chen Member IEEE and Chen-Yi Lee, Memebr IEEE, A Generalized Mixed-Radix Algorithm for Memory- Based FFT Processors, IEEE Transl. II:Ecpress Briefs,, vol. 57, January [8] Jeffrey G. Andrews, Arunabha Gosh, Rias Muhamed, Fundamentals of WiMAX Understanding Broadband Wireless Networking, Published by Pearson Education, Inc, publishing as Prentice Hall, copyright 2007 D. Maheswari was born in the year 1984 in India. Currently she is pursuing her Masters in Applied Electronics in College of Engineering, Guindy, Anna University. She earned B.E in Electronics and communication from Anna University in She has work experience in Semiconductor Industry as Front End Design and Verification engineer. She has worked on SoCs developed for Networking, Automobile and Mobile applications. Her areas of interests include Mobile Communication, Signal Processing, Microprocessors, Micro controllers, Power PC processors and JTAG. Dr. R. Seshasayanan was born in the year 1958 in India and received his B.E degree from College of Engineering, M.E. degree from Anna University in the year 1980 and 1983 respectively. He received his PhD from Anna University. He is presently working as Assistant Professor in the Department of Electronics and Communication, Anna University, and his area of interests are VLSI Design, Reconfigurable architecture and Low power design. 74