PAPER A High-Speed Two-Parallel Radix-2 4 FFT/IFFT Processor for MB-OFDM UWB Systems

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1 1206 IEICE TRAS. FUDAMETALS, VOL.E91 A, O.4 APRIL 2008 PAPER A High-Speed Two-Parallel Radix-2 4 FFT/IFFT Processor for MB-OFDM UWB Systems Jeesung LEE, onmember and Hanho LEE a), Member SUMMARY This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-2 4 FFT/IFFT processor for MB-OFDM ultrawideband UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using a two-parallel data-path scheme and a single-path delayfeedback SDF) structure. The radix-2 4 FFT algorithm is also realized in our processor to reduce the number of complex multiplications. The proposed FFT/IFFT processor has been designed and implemented with μm CMOS technology in a supply voltage of 1.8 V. The proposed twoparallel FFT/IFFT processor has a throughput rate of up to 900 Msample/s at 450 MHz while requiring much smaller hardware complexity and low power consumption. key words: Fast Fourier transform FFT), radix-2 4, SDF, multiband orthogonal frequency-division multiplexing MB-OFDM), ultrawideband UWB) 1. Introduction Ultrawideband UWB) communication systems, which enable the delivery of data from a rate of 110 Mb/s at a distance of 10 m to a rate of 480 Mb/s at a distance of 2 m in a realistic multipath environment, are ideally suited to application in short range wireless communications because they can share a frequency band with existing narrowband systems and offer a higher data rate than or Bluetooth [1], [2]. One of the communication methods for IEEE a standard is Multiband Orthogonal Frequency Division Multiplexing MB-OFDM), which offers 528 MHz bandwidth [3], [4]. To minimize power consumption and provide multiple simultaneous operating piconet satisfying the Federal Communications Commission regulatory, a MB-OFDM UWB system has been proposed. This system transmits OFDM symbols using a different carrier frequency from symbol to symbol according to time frequency codes [3], [4]. MB- OFDM-based UWB not only has reliably high-data-rate transmission in time-dispersive or frequency-selective channels without having complex time-domain channel equalizers but also can provide high-spectral efficiency. The FFT/IFFT processor is one of the modules having high computational complexity in the physical layer of the MB-OFDM UWB system. The present paper proposes a high-speed, low-complexity FFT/IFFT processor with a novel two data-path parallel pipelined architecture for high- Manuscript received December 20, Manuscript revised October 31, The authors are with School of Information and Communication Engineering, Inha University, Incheon, , Republic of Korea. a) hhlee@inha.ac.kr DOI: /ietfec/e91 a throughput applications. This paper is organized as follows. Section 2 describes the design issues of MB-OFDM UWB communication systems. Section 3 describes the 128-point radix-2 4 FFT/IFFT algorithm. Section 4 provides details of the proposed FFT/IFFT architecture. In Sect. 5, the hardware cost and throughput rate of the proposed FFT/IFFT architecture is compared with that of the existing 128-point FFT/IFFT architecture for MB-OFDM UWB applications. Conclusions are presented in Sect Design Issue of the FFT Processor for the MB- OFDM UWB Systems A block diagram of the proposed physical layer of MB- OFDM UWB systems is shown in Fig. 1 [3], [4]. In the MB- OFDM UWB system, the data rate is from 53.3 to 480 Mb/s with code rates of 1/3, 11/32, 1/2, 5/8, and 3/4. In order to implement the physical layer of the MB-OFDM UWB system more efficiently, the four data-path approach has been adopted to reduce the data sampling rate from the analogdigital converter such that, after the serial-to-parallel converter, the data sampling rate of each path can generally be reduced to 132 Msamples/s [5], [6]. However, the hardware cost is also increased significantly, because more memory and complex multipliers are needed to allow multiple data to be operated simultaneously. Various FFT architectures, such as multi-path delay commutator and single-path delay feedback SDF) in the radix-2 and radix-4 algorithms, have been proposed over the past 3 decades [6], [7]. The architectures listed above have a) b) Fig. 1 Block diagram of the MB-OFDM UWB system, a) transmitter, and b) receiver. Copyright c 2008 The Institute of Electronics, Information and Communication Engineers

2 LEE and LEE: A HIGH-SPEED TWO-PARALLEL RADIX-2 4 FFT/IFFT PROCESSOR FOR MB-OFDM UWB SYSTEMS 1207 distinctive advantages and some common requirements, as has been well described in [6], [7]. The main motivation of this paper is to design a novel two-parallel data-path pipelined radix-2 4 SDF FFT/IFFT architecture that offers high throughput and low hardware complexity. The proposed FFT processor is not only appropriate for the MB- OFDM UWB physical layer but also can provide an available throughput rate to meet the MB-OFDM UWB specifications. The approach is described in more detail in Sects Radix-2 4 Algorithm A Discrete Fourier Transform of length is defined as follows: 1 Xk) = xn)wn, k k = 0, 1,..., 1 1) n=0 where W n, the so called twiddle factor, denotes the -th primitive root of unity, with its exponent evaluated modulo. k is the frequency index and n is the time index. In order to derive the radix-2 4 algorithm, consider the following first 4 steps of decomposition. Applying a 5-dimensional linear index map n = 2 n n n 3 + n 4 + n 5 2) k = k 1 + 2k 2 + 4k 3 + 8k 4 + k 5 The Common Factor Algorithm CFA) takes the form of Xk 1 + 2k 2 + 4k 3 + 8k 4 + k 5 ) = x 2 n 1+ 4 n 2+ 8 n 3+ ) n 4+n 5 W nk n 5 =0 n 4 =0 n 3 =0 n 2 =0 n 1 =0 1 = n 5 =0 [G n 5, k 1, k 2, k 3, k 4 ) W n 5k 1 +2k 2 +4k 3 +8k 4 ) ]W n 5k 5 The twiddle factors can be expressed in the form of W nk = 1)n 1k 1 j) n 2k 1 +2k 2 ) W 2n 3+n 4 )k 1 +2k 2 +4k 3 ) 1) n 4k 4 W n 5k 1 +2k 2 +4k 3 +8k 4 ) W n 5k 5 The fourth butterfly unit has the expression of G n 5, k 1, k 2, k 3, k 4 ) = Hn 5 ) + 1) k 4 W k 1+2k 2 +4k 3 ) +W 2k 1+2k 2 +4k 3 ) H H n 5 + ) 8 + 1) k 4 W 3k 1+2k 2 +4k 3 ) H n n 5 + ) where Hn) denotes the second butterfly unit. Hn)= Hn, k 1, k 2 )= Bn, k 1 )+ j) k 1+2k 2 ) B ) 3) 4) 5) n+ ) 4, k 1 Fig. 2 SFG of the 128-point radix-2 4 SDF FFT algorithm. where Bn, k 1 ) denotes the first butterfly unit as follows. Bn, k 1 )= xn)+ 1) k 1 x n+ ) 2 The twiddle factor W n in Eq. 5) has four complex numbers. The algorithm can take a complex constant multiplier instead of a programmable complex multiplier. Hence, the complex multiplication of twiddle factors, W n, can be implemented in the Canonic Signed Digit CSD) constant multiplier, which contains the fewest number of non-zero bits. As such, the area and power consumption can be reduced [8]. Figure 2 shows the signal flow graph SFG) of the 128-point radix-2 4 SDF R2 4 SDF) FFT algorithm. 4. Proposed Radix-2 4 FFT Architecture A block diagram of the proposed two-parallel data-path 128- point R2 4 SDF FFT/IFFT processor is shown in Fig. 3. The proposed architecture consists of a memory block, butterfly

3 1208 IEICE TRAS. FUDAMETALS, VOL.E91 A, O.4 APRIL 2008 Fig. 3 Proposed 2-parallel data-path 128-point radix-2 4 SDF FFT/IFFT processor. a) Fig. 5 Block diagram of Module1. Fig. 4 b) Radix-2 4 butterfly units a) BF1, W n and b) BF2. units BF1, BF2), complex Booth multipliers, CSD complex constant multipliers, register files, and some multiplexers. The operation of the FFT/IFFT processor is controlled by the control signal, IFFT/FFT sel, asshownin Fig.3. The output results of butterfly units are complex addition and complex subtraction of two input data x[n] and x[/2 + n], where = 128, as shown in Fig. 4. The BF1 stores all of /2-th input data in RAM. When /2 + n)-th input data are fed to BF1, the input data x[n] stored in RAM are read and are added by new input data. And then the subtracted output data x[n] x[/2 + n]) are stored in the location of previous input data x[n]. Whenthenewsetof input dataare fed to BF1after the -th input operation, the new input data are stored in the RAM and x[n] x[/2 + n]) data stored in RAM at previous cycle are read from the RAM. The BF2 architecture is almost same with the BF1 architecture except the operation of 3/4-th input data multiplying of j. Module1 consists of four /4) 10 bits RAMs, adders, subtractors and some multiplexers, as shown in Fig. 5. Module1 operation has two-parallel data path operation with memory. First, for the two-parallel data path operation, the two of the complex inputs are stored in the RAM. When /2-th input data are stored in the RAM, the previously stored input data x[2n 1] are read from the RAM and generates the outputs, which are added and subtracted by x[2n 1] and the new input data x[/2 + 2n 1] simultaneously. And the input data x[/2+2n] fed to Module1 is stored in the location in which the previous x[2n 1] data was stored. After x[] datais stored in the RAM, data x[2n] andx[/2 + 2n], which are read from the RAM, are added and subtracted in the Module1 at the next cycle simultaneously. The last BF1 in Fig. 3 is 64-point butterfly unit because it needs to wait the input data of even time. Meanwhile other BF units need just half point of butterfly, because the input data of odd times and even times operate separately. Two complex Booth multipliers are needed in the two-parallel approach to implement the radix-2 4 FFT algorithm. Figure 6 shows the complex Booth multiplier, which needs a ROM to store the multiplicand. Since only 1/8 period of cosine and sine waveforms are needed, kinds of the twiddle factors, which is 1/8 out of 128 points, are stored in ROM [9]. Thus, the ROM stores all 32 bytes

4 LEE and LEE: A HIGH-SPEED TWO-PARALLEL RADIX-2 4 FFT/IFFT PROCESSOR FOR MB-OFDM UWB SYSTEMS 1209 Table 1 The CSD binary representation of twiddle factor 1 = 1). a) b) Fig. 6 a) Complex booth multiplier and b) 8 8 Dadda reduction network with error-compensation circuit. 8 2 bits) twiddle coefficients. To reduce the truncation error, the fixed-width Dadda multiplier with the error compensation method was used. For the complex Booth multiplier, the Dadda reduction network with error-compensation circuit [10], [11] was used in the proposed FFT processor, as shown in Fig. 6b). The value of 1st table shown in Fig. 6b) is obtained from the Partial Product Generator PPG), in which the sign-bit pre-calculation vector value is The signals y at 6th column, which are the output of error-compensation circuit, are the inversion of the zero signals from Booth encoder. For rounding operation, 1 must be added at the 6th column. The horizontal segment of 2nd table represents the carry and sum output from the full-adder or half-adder. In other words, the crosswise segment represents 2,2) or 3,2) counter. The dot ) at 2nd table means the values copied from 1st table, which is located in the same column. From 1st table to last table, the data reduction method reduces the number of row consecutively. The A, B vector at the last table represents 8-bits 2 s complement number. In comparison of conventional Wallace tree, proposed Dadda reduction network with error-compensation circuit can reduce full adder about 50% relatively. The radix-2 4 FFT algorithm based two-parallel datapath architectures has fewer multipliers than those of lower radix FFT algorithms. For example, the radix-2 4 algorithm has the same number of multipliers as the radix-2 2 algorithm but can reduce the degree of multiplicative complexity by means of replacing a half of the full complex multipliers with trivial constant multipliers [7]. The twiddle factors, W8), W), W24), and W48) correspond to the trigonometrical functions of cosπ/8), sinπ/8) and cosπ/4), respectively. Table 1 shows the twiddle factor, which represents the 8-bits coefficients in the decimal format, the 2 s complement, and the CSD format. Radix-2 4 algorithm can take complex constant multiplier instead of programmable complex multiplier. The Canonic Signed Digit CSD) constant multiplier contains the fewest number of non-zero bits, so it can reduce the area and power consumption [8]. Figure 7 shows the structure of the CSD complex constant multipliers for cosπ/8), sinπ/8), and cosπ/4). To efficiently compensate for the quantization error, the truncated bits are divided into two groups major group and minor group) depending upon their effects on the quantization error. The error compensation bias is first expressed in terms of the truncated bits in the major group. The effects of the other truncated bits in the minor group are then handled by a probabilistic estimation [8]. The total compensation bias, C, circuit is shown in Fig. 7. Table 2 shows the scheduling of the twiddle factor in each data path, in which the multiplication of twiddle factor is separated with 1st data-path and 2nd data-path due to 2-parallel data-path operation. The CSD complex constant multiplier block consists of six CSD constant multipliers, 2 s complement logics, and multiplexers as shown in Fig. 8. Each real value and imaginary value of the output data are outputted by six CSD constant multipliers. When the real and imaginary values of twiddle factors are same, the two CSD constant multipliers are used and theirs two outputs are added to generate the output of the CSD complex multiplier. Otherwise, when the real and imaginary values are not same,

5 1210 IEICE TRAS. FUDAMETALS, VOL.E91 A, O.4 APRIL 2008 a) sinπ/8) = Fig. 8 CSD complex constant multiplier block. b) cosπ/8) = Fig. 7 Table 2 c) cosπ/4) = The proposed CSD constant multiplier. Scheduling of the twiddle factor. the four CSD constant multipliers are used for the multiplication of input and twiddle factors. If inputs don t need to multiply with twiddle factor in case of X in Table 2), the output results are generated from the input directly. 5. Implementation and Performance Evaluation The appropriate word length in the proposed 128-point twoparallel pipelined R2 4 SDF FFT/IFFT processor is determined by a fixed-point simulation before hardware imple- Fig. 9 Simulation result for SR versus the internal word length. mentation. Figure 9 shows the simulation results for the relation of SR with the internal word length of the FFT/IFFT processor. The detailed explanation is described in our previous paper [12]. Based on the simulation results, we determined the word length of the proposed FFT/IFFT processor to be 10 bits in both real and imaginary parts. In addition, the SQR of the proposed 128-point R2 4 SDF FFT/IFFT processor is about 33 db. After the appropriate word length of the proposed FFT/IFFT processor was chosen, the FFT/IFFT processor was implemented using a standard-cell based design methodology and the 0.18-μm MagnaChip Components library plus full-custom memory and register file blocks. The performance and hardware cost of the pipelined FFT/IFFT processor are increased as a result of using the multiple data-path approach. In general, conventional FFT architectures have used a four-parallel data-path approach [5], [6], which requires higher hardware cost. However, the proposed two-parallel data-path pipelined R2 4 SDF FFT/IFFT processor provides higher throughput rate with higher clock frequency while the hardware cost is reduced significantly. Table 3 shows performance comparisons between the proposed two-parallel R2 4 SDF FFT/IFFT processor and the existing 128-point FFT/IFFT processor [6]. The twoparallel R2 4 SDF FFT/IFFT processor consists of 70,000

6 LEE and LEE: A HIGH-SPEED TWO-PARALLEL RADIX-2 4 FFT/IFFT PROCESSOR FOR MB-OFDM UWB SYSTEMS 1211 Table 3 Performance of the 128-point pipelined FFT/IFFT architectures. gates excluding memories, and the operating clock frequency is about 450 MHz. Although the number of registers in our design is greater than previous four-parallel architecture, it is implemented by two bits RAM, which requires small area cost. Also, it not only has a significantly reduced number of complex multiplication and complex addition but also can provide the highest clock frequency 450 MHz due to two-parallel data-path and pipelined complex Booth multiplier. The highest throughput rate of our proposed architecture is up to 900 Msample/s at 450 MHz. [3] A. Batra, et al., Multi-band OFDM physical layer proposal for IEEE task group 3a, IEEE P /268r3, March [4] A. Batra, J. Balakrishnan, G.R. Aiello, J.R. Foerster, and A. Dabak, Design of multiband OFDM system for realistic UWB channel environment, IEEE Trans. Microw. Theory Tech., vol.52, no.9, pp , Sept [5] C.-H. Shin, S. Choi, H. Lee, and J.-K. Pack, Design and performance of 4-parallel MB-OFDM UWB receiver, IEICE Trans. Commun., vol.e90-b, no.3, pp , March [6] Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, A 1-GS/s FFT/IFFT processor for UWB applications, IEEE J. Solid-State Circuits, vol.40, no.8, pp , Aug [7] J.-Y. Oh and M.-S. Lim, Fast fourier transform algorithm for low-power and area-efficient algorithm, IEICE Trans. Commun., vol.e89-b, no.4, pp , April [8] S.-M. Kim, J.-G. Chung, and K.K. Parhi, Low error fixed-width CSD multiplier with efficient sign extention, IEEE Trans. Circuits Syst. II, vol.50, no.12, pp , Dec [9] L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, A new VLSI-oriented FFT algorithm and implementation, Proc. 11th Annu. IEEE Int. ASIC Conf., pp , Sept [10] L. Dadda, On parallel digital multipliers, Alta Frequenza, vol.45, pp , [11] K.J. Cho, K.C. Lee, J.G. Chung, and K.K. Parhi, Design of lowerror. Fixed-width modified booth multiplier, IEEE Trans. Very Large Scale Integr. VLSI) Syst., vol.12, no.5, pp , May [12] J. Lee, H. Lee, S.-I. Cho, and S.-S. Choi, A high-speed, lowcomplexity radix-2 4 FFT processor for MB-OFDM UWB systems, IEEE Inter. Symp. on Circuits and Systems, pp , May Conclusion In this paper, a novel two-parallel data-path pipelined 128- point radix-2 4 SDF FFT/IFFT processor for a MB-OFDM UWB system has been proposed. In the proposed architecture, high-speed data processing and low hardware complexity can be achieved due to two-parallel data-path structure and high clock speed. Furthermore, the number of complex Booth multipliers is effectively reduced by using a radix-2 4 SDF FFT algorithm. The performance results show that the data processing rate is as high as 900 Msamples/sat 450 MHz while requiring small hardware complexity. The proposed architecture is expected to be incorporated in highspeed, low-complexity MB-OFDM UWB systems. Acknowledgments This research was supported by the MIC Ministry of Information and Communication), Korea, under the ITRC Information Technology Research Center) support program supervised by the IITA. References [1] J. Foerster, E. Green, S. Somayazulu, and D. Leeper, Ultrawideband technology for short-or medium-range wireless communications, Intel Technology Journal Q2, 2001.S.B. Wicker, Error Control Systems for Digital Communication and Storage, Prentice Hall, [2] T. Domain, UWB applications, demonstration & regulatory update, Sept 2001 Workshop, March Jeesung Lee received B.S. degree in Electrical & Computer engineering from Inha University in 2005 and M.S. degree in information & communication engineering from Inha University, Incheon, Korea, in 2007, respectively. His research interests are digital VLSI circuits and systems design for communications. Since March 2007, she has been with the LIG ex1 as the member of engineering staff. Hanho Lee received Ph.D. and M.S. degrees, both in Electrical & Computer Engineering, from the University of Minnesota, Minneapolis, in 2000 and 1996 respectively, and a B.S. degree in Electronics Engineering from Chungbuk ational University, S. Korea, in In 1999, he was a Member of Technical-Staff-1 at Lucent Technologies, Bell Labs, Holmdel, J. From April 2000 to August 2002, he was a Member of Technical Staff at the Lucent Technologies Bell Labs Innovations), Allentown, where he was responsible for the development of VLSI architectures and implementation of high-performance DSP multiprocessor SoC for wireless infrastructure systems. From August 2002 to August 2004, he was an assistant professor at the Department of Electrical & Computer Engineering, University of Connecticut. Since August 2004, he has been with the School of Information and Communication Engineering, Inha University, where he is presently an Associate Professor. His research interests include design of VLSI circuits and systems for communications, System-on-a-Chip SoC) design, reconfigurable architecture, and forward error correction coding.