BINARY FSK TX AND RX CHAIN IN VSS

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1 By: Christos Komninakis, Ph.D BINARY FSK MODULATION IN VSS This application note outlines some of the VSS capabilities demonstrated when building and simulating a complete transmitter-channel-receiver chain for Binary Frequency Shift Keying () transmission. Designers can interchangeably use a black box FSK modulator (called FSK_SRC in the VSS model library and denoted as CP- in Figure 1), or create the modulator using a cascade of more elementary blocks. The modulated data are sent through an Additive White Gaussian Noise channel (AWGN), and then a receiver, also constructed from elementary blocks, demodulates the bits. The errors in this demodulation process caused by the noise are measured so that Bit-Error-Rate plots can be produced against channel Signal-to-Noise Ratio (SNR). Specific descriptions for the building blocks used in this simulation and relevant VSS plots are included. TRANSMITTER FUNCTIONALITY The simple transmitter produces a modulated signal at a rate of 1000 bits/sec, and is composed of elementary blocks, shown in the lower left-hand corner of Figure 1. The modulated signal then passes through an AWGN channel and is demodulated at the receiver. In Figure 1, the transmitter is made out of more elementary blocks, and its spectrum is identical to the composite FSK_SRC block with corresponding settings (see Figure 2). The signal after addition of AWGN is demodulated by a discriminator receiver, consisting of a filter (PLSSHP), an FM discriminator (FM_DSCRM), an integrate-and-dump block (INTG_DMP), and an ADC block which also acts as a slicer here. The input bits are appropriately delayed and compared to the demodulated bits in the BER meter, and a BER curve vs. Visual System Simulator 1

2 Transmitter Functionality E b /N 0 is produced. Binary Digital Source (RND_D) RN D_D ID= A 5 M=2 RATE=1000 CP- D SI N_C ID =A6 AMP L=5 PH SO FF=0 Deg OFFFRQ=0 khz CTRFRQ=1e4 khz DAC ID =A7 FSK_SR C ID = A1 MOD=2-FSK OUTLVL=0 db OLVLTYP=Bit Energy (db) RA TE= CTRFRQ=1e4 khz MODID X=0.707 PLSTYP=Rectangular AL PHA =0. 35 L= PL SLN= A DAC Tx LO TP ID=Data 1 2 TP I D=C PFSK FM_MOD ID=A3 KF=0.707/2* Eb_No = sweep(stepped(0,12,2)) AWGN ID=A13 P WR= -E b_ No db P W RTYP=N 0 (db) TP ID = FM Modulator PLS SHP ID=F1 PLS TYP=G auss ian (BT) ALP HA=0.5 PLS LN = NRMTY P=Unit Pulse Gain IMPTYP=Auto DL Y_ SMP ID =A2 DL Y=1 5 IV AL=0 FM_DSCRM ID = A4 GAIN=2/0.707 TP ID=Discrim SMP SYM= NFFT= N AVG= WNDTYP=Auto INTG_DMP ID=A10 N=8 INTGTYP=Sum*Time Step dt TP ID =I NT_Du mp SMPSY M= NFFT= NAV G= WNDTYP=Auto WNDPAR= SLDFR C=0.5 WNDWHN=Auto MSKTYP=P as s-symmetric AWGN Filter Discriminator Integrate & Dump ADC Delay (Compensate for System) A AD C ID =A15 M=2 D TP ID=ADC B UFSZ= BER _EX T ID =B ER1 SW PVAR =Eb_N o SW PTYP=Eb/N 0 BER BER Meter Figure 1. System Diagram Depicting a Complete Tx-Rx Chain for Binary FSK in VSS The elementary transmitter blocks are RND_D for the random generation of bits, a DAC block to convert the bits into antipodal NRZ square pulses, and an analog FM modulator (FM_MOD in the VSS Element Browser). The transmitted waveform out of the cascade of these blocks is identical to the waveform produced by a more compact general FSK transmitter, parameterized to also produce the same modulated Binary FSK with modulation index h = and square frequency shaping pulse. Behaviorally, the two configurations, namely the black box FSK_SRC and the transmitter composed of the elementary parts, are identical, as confirmed by overlaying their respective spectra, shown in Figure 2. Setting the parameters for those two distinct but behaviorally identical transmitters requires some care, since the FM_MOD (bottom) is an analog block requiring the setting of a Frequency Sensitivity parameter, KF (in Hz/Volt). Also, the amplitude of the -modulated sinusoid coming out of FM_MOD is set by the amplitude of Tx LO (see Figure 1), while the transmitted amplitude of FSK_SRC (denoted CP-) is set by the Bit Energy parameter of that block. In brief, to achieve identical waveforms as shown in Figure 2, the Amplitude of Tx LO must be 5.0 (to match the Bit Energy of 0 db in FSK_SRC). Also, the frequency sensitivity of the FM_MOD must be h K f = , where h is the modulation index specified in FSK_SRC, and 2 2 Visual System Simulator

3 Transmitter Functionality the symbol-rate (or baud-rate, or, in our binary modulation case, the bit-rate) is 1000 symbols/sec. More specific information about the amplitude and frequency scaling of the modulated signal performed by FM_MOD (an analog block) and how it corresponds to modulation similar to that performed by the block FSK_SRC is found in the Appendix. Spectrum 20 DB(PWR_SPEC[TP.,512,10]) (dbm) 0 DB(PWR_SPEC[TP.CPFSK,512,10]) (dbm) Frequency (khz) Figure 2. Spectra from CPFSK Block (FSK_SRC) in VSS (magenta) and Transmitter Note in Figure 2 that the spectrum from the composite CP- block with parameter settings corresponding to binary FSK is identical to the spectrum from the transmitter composed of more elementary parts (i.e., a random binary data source RND_D, a DAC, and an FM modulator FM_MOD). Having confirmed that the two different ways to set up the transmitter lead to identical waveforms, it is informative to overlay the plot of the random bits being modulated, and the plot of the phase produced by the FM (or FSK) modulator. This is done in Figure 3, where we observe that the transmitted phase behaves exactly as is expected in a binary FSK transmission scheme with rectangular frequency shaping pulse (a ramp in phase, which is the integral of instantaneous frequency). Figure 3 shows that the phase of the modulated waveform increases in a ramp when the input bit is 1, and decreases in a ramp with the same slope when the input bit is a 0. Notice that the phase remains continuous between different bit intervals, and the phase jumps in the plot are only the Application Notes 3

4 Transmitter Functionality effect of the wrap-around when the phase exceeds ±π. 2 TX Waveforms Re(WVFM[TP.Data,20,4,1]) (L) Ang(WVFM[TP.,20,4,1]) (R, Deg) Time (ms) -200 Figure 3. Data Waveform and Phase Waveform In Figure 3, the data waveform (binary 1 s and 0 s) is plotted on the left axis in brown, while the phase waveform taken from the FM modulator is shown in blue on the right. Observe the phase increase if the data symbol is 1 and the decrease if the data symbol is 0, including the obvious wrap-around when the phase value reaches +180 or -180 degrees. 4 Visual System Simulator

5 Channel and Noise Scaling CHANNEL AND NOISE SCALING Having explored the transmitter functionality, we next discuss the channel and receiver. The channel is a plain Additive White Gaussian Noise channel, simulated via the VSS AWGN block. The power of the noise is set to equal the global variable EbNo (in db), because we will run a Bit-Error-Rate (BER) simulation sweep with different noise powers, corresponding to different ratios of Bit Energy to Noise Power Spectral Density digital communication systems. E b N 0, a common figure of merit of You can get this variable to be swept across different values by adding an equation to the simulation (choose Diagram > Add Equation and place it inside the system diagram shown in Figure 1, or inside the Global Definitions window): EbNo = sweep( stepped( 1, 13, 2) ) (1) This equation instructs the simulator to produce successive runs, sweeping the design variable EbNo starting at 1 db, in steps of 2 db, up to and including 13 db. The duration of each of those simulation runs is controlled by the BER measurement block, but generally at each simulation point the simulation ends when enough errors are detected, and the simulator moves on to the next point specified in the sweep variable. This is changeable, depending on user-specified parameters in the BER block, to another stopping criterion for each individual simulation, corresponding in this case to the next particular value of E b N 0. For example, the BER block can be parameterized to stop every simulation after a certain maximum number of samples are simulated, independently of the number of errors found. Note that to produce an entirely equivalent evaluation of our transmitterreceiver chain we could have equally well scaled the Bit Energy of the transmitter, and kept the noise power constant. So, an equivalent BER simulation results from setting the amplitude of the Tx LO (which, recall, sets the output of the FM_MOD) to 5*10^(EbNo/20), and at the same time setting the noise power inside the AWGN block to 0 db. This has no effect on the Bit-Error-Rate simulation; the results are identical. Of course, to achieve identical spectra as shown in Figure 1, you would also have to specify the Bit Energy of the FSK_SRC as EbNo, such that signal amplitudes from FM_MOD and FSK_SRC match. In summary, there are two identical ways to run BER simulations against E b N 0 using the above sweeping instruction to the simulator. After adding Application Notes 5

6 Receiver and Demodulation equation (1) inside the system diagram to instruct the simulation to perform the sweep of the variable EbNo across all specified values, either of the following two steps can be taken: normalize the transmitter Bit Energy to 0 db inside FSK_SRC -or, equivalently, set the amplitude of the SIN_C acting as Tx LO for FM_MOD to A = 5.0- and set the noise power in AWGN to negative values in db, namely -EbNo. set the transmitter Bit Energy to EbNo db in FSK_SRC -or, equivalently, set the amplitude of the SIN_C acting as Tx LO for FM_MOD to A = 5.0*10^(EbNo/20)- and normalize the noise power inside the AWGN block to 0 db. RECEIVER AND DEMODULATION Before describing the BER measurement and its specifics in VSS, we describe the operation of the receiver, which is constructed out of elementary blocks. Note that it is not always necessary to construct receivers out of elementary VSS blocks. For many common modulation methods such as QAM, PSK, MSK and its variants like GMSK, OFDM and others, there are already corresponding demodulation receiver blocks in VSS, usually found under the Modulation category in the VSS Element Browser. These ready-made blocks can be directly used, avoiding set up of a receiver out of elementary VSS blocks if that is unnecessary. Furthermore, due to the internal propagation of parameters employed by the VSS simulation engine, when a transmitter and its corresponding receiver block are in the same system diagram, parameters such as the data rate need only be specified once in the transmitter. The receiving block is then automatically set up. For example, you can use the OQPSK_TX block under Modulation/ OQPSK to set up a transmitter for the modulation scheme called Offset-QPSK (also called staggered QPSK in the literature), which is a variant of QPSK with better peak-to-average power properties. After the transmitter parameters are set, including symbol rate and pulse shaping type and coefficient (e.g., rootraised cosine with a = 0.4), the receiver block OQPSK_RX is automatically configured to employ the matching filter pulse shape (e.g., another identical rootraised cosine filter with a = 0.4 in this case), and, even more conveniently, to delay and scale the received signal appropriately, such that the BER measure- 6 Visual System Simulator

7 Receiver and Demodulation ment can be performed without having to adjust received amplitude and delay. In this example we build the receiver from elementary VSS blocks for demonstration purposes. This type of receiver is called the discrimination receiver in the literature, and it can be shown to outperform even the coherent demodulator. This is not surprising, because it is in fact a non-linear demodulator, which can in some cases outperform optimum (under the linearity constraint) demodulators like the coherent correlation demodulator. Following the system diagram in Figure 1, the modulated signal after the AWGN block passes through a filter, an FM discriminator, and an Integrate-and-Dump block before it arrives at the ADC, where it is converted to demodulated bits RX Waveforms Re(WVFM(TP.Discrim,10,1,1)) (R) Re(WVFM(TP.INT_Dump,10,1,1)) (L) Time (ms) Re(WVFM(TP.ADC,10,4,0)) (L) Figure 4. Waveforms on Receiver Side In Figure 4, in red on the right y-axis, a snapshot of the phase discriminator output in low noise is shown for clarity. The dashed green waveform (in fact it is only samples at the symbol rate of 1000 Hz, i.e., every 1msec) shows the sampled output of the integrate-and-dump block. As expected, this is positive when the phase discriminator output is increasing, and negative otherwise. Finally, in black, observe the result of the ADC, which slices the output of the integrateand-dump for digital data. The scale for the two latter waveforms is on the left y-axis. Application Notes 7

8 BER Computation The filter (known as the pre-detection filter) is implemented using the PLSSHP block under the Filters category in the VSS Element Browser, which allows for a variety of filter shapes. We choose a Gaussian filter with BT=0.5, since this results in good performance for the discrimination receiver, as described in [1]. The FM_DSCRM block is implementing the FM discriminator, and its gain is set to h/2, where h is the chosen modulation index (h = 0.707). This, again, is because the FM discriminator FM_DSCRM is an analog block, usually (however, not in this case) used in conjunction with FM_MOD in the context of analog FM modulation, for which the modulation index has a definition different from the one used in the context of digital FSK modulation. After the discriminator, the post-detection filter is just a simple Integrate-and-Dump operation, implemented with the VSS INTG_DMP block, located in the Signal Processing category of the Element Browser. Figure 4 describes the observed waveforms, as measured by the Test Points (TP) introduced after each stage of the receiver (see Figure 1) and the meaning of those waveforms for the demodulation process. Observe that the ADC block acts as a slicer too, since it converts positive outputs of the Integrate-and-Dump filter to binary 1, while negative values at the output are interpreted as bit 0. It may be noteworthy that the output of the discriminator is still a continuous signal, always in the sense implied by a discrete-time simulator like VSS. So, the discriminator output is sampled 8 times per symbol (bit), while there is only one output from the Integrate-and-Dump for every bit, and that one sample per symbol is the one that is later sliced to convert to a bit by the ADC. BER COMPUTATION After demodulation as shown in Figure 1, the demodulated bits along with an appropriately delayed version of the transmitted bits enter the BER computation block (BER_EXT) under the Meters category and BER subcategory in the VSS Element Browser. For this block, you can specify the sweep type (whether it is an E b N 0 or an E s N 0 sweep, whereby the swept variable is Energyper-Symbol over noise Power Spectral Density). For binary modulation as in this application, the two quantities are the same, since bit and symbol are the same. For higher order (M-ary) modulations, such as 16-QAM for instance with M = 2 b = 16, we have E s N 0 = b E b N 0. 8 Visual System Simulator

9 BER Computation You can also specify the minimum number of errors that need to be detected before each simulation included in the sweep completes. This is important for simulation speed, because specifying fewer than errors may lead to unreliable BER results. Making this number very large, however, can delay the simulation significantly, particularly for higher SNR, since errors are more rare then. Also, you are allowed to specify the number of initial symbols to be ignored, since in a typical scenario there is some delay (i.e. K symbols) in the system between the transmitter and receiver, so the first K comparisons made by the BER block have no meaning and should be ignored. More variants of the BER_EXT block exist under the Meters category of the VSS Element Browser, some with capabilities to save results to files and to overlay different BER plots. Under the same Meters > BER subcategory in the VSS Element Browser, there are also BER and a SER (for Symbol-Error-Rate) blocks with only one input. In these cases the comparison to reference bits for error detection is done internally and automatically from the corresponding transmitter block. The explanatory note on the input (seen by moving the mouse over the input port) reads Digital Data to be Error Counted, implying that the reference is tacitly provided by the simulator internally. In this example, we plot the BER performance of our receiver against E b N 0, and the result follows. The simulation, as previously explained, sweeps through seven values of E b N 0, and plots the BER on a graph. An interesting capability is that BER plots from simulations can be overlaid against pre-stored theoretical results for some common modulations and receiver structures, taken from the literature. For instance, in this case, as shown in Figure 5, aside from our results in blue, we also plot the following reference curves, for perspective. All of those, and many more reference BER curves for other modulation types are found in the Measurement list when adding new measurements to existing plots under the System > BER category. The plots shown in Figure 5, however, represent: the performance of a non-coherent receiver, in black the performance of a coherent linear (correlation) receiver, in red the performance of the non-linear discrimination receiver, under some ideal assumptions, in green, as provided in [1]. Application Notes 9

10 BER Computation 1 BER.1.01 BER e-005 1e-006 1e-007 BER(BER_EXT.BER1) FSK_BERREF(BER_EXT.BER1,0,1,1) FSK_BERREF(BER_EXT.BER1,0,0,1) FSK_BERREF(BER_EXT.BER1,0,2,1) Eb_No Figure 5. Plot of BER vs. E b /N 0 for Discrimination Receiver Figure 1 also depicts three reference curves for the performance of a noncoherent, a coherent, and an ideal discriminator receiver in black, red and green respectively. The main assumption for this last curve is that the bandwidth of the IF predetection filter is sufficiently broad to allow us to ignore the distortion introduced to the signal. In practice, however, this is always a trade-off, because as the IF filter becomes wider, the signal distortion increases. At the same time more noise is introduced into the demodulator. This is the reason the performance of our simulated transmitter-receiver chain does not achieve this lower bound, although it is better than that of the coherent receiver for high SNR, for the reasons explained in Receiver and Demodulation. For more details on and the discriminator receiver, see [1] or other Communications textbooks. 10 Visual System Simulator

11 Appendix APPENDIX This appendix discusses signal scaling, both in amplitude and frequency, as it is performed by the FM_MOD analog block (primarily designed to perform analog FM modulation) so that the modulated waveform at its output corresponds to a digitally modulated sinusoidal waveform with a specific modulation index h. Amplitude and frequency scaling issues are addressed, as these are encountered in VSS, in the following two sections. The goal is to scale the two blocks (FM_MOD and FSK_SRC) appropriately by using their user-specified parameters, such that their respective output signals match and both correspond to the above modulation characteristics. Amplitude Scaling of FSK_SRC According to [2], the VSS FSK_SRC block, which can be configured to perform digital M-FSK modulation with any modulation index h and frequency shaping pulse, outputs an FSK-modulated sinusoid, with amplitude A given by: A = 2 log 2 M E b Z 0 SMPSYM where SMPSYM is a parameter of the simulation (the number of samples per symbol, which in our binary case is the same as a bit) and can be set by choosing Options > Default System Options. For this simulation we set this to SMPSYM = 8. Another system parameter in equation (2) is, the default impedance, set to Z 0 = 50Ω. The value of the bit energy is set from the user-specified parameter OUTLVL in FSK_SRC as: Z 0 (2) OUTLVL 10 E b = 2 10 (3) Using equations (2) and (3) and substituting Z 0 = 50Ω, M = 2, OUTLVL = 0 db, and SMPSYM = 8, we get A = 5.0 for the amplitude of the modulated sinusoid. Therefore, to get the amplitude from FM_MOD to exactly match that from FSK_SRC, you must set the amplitude of the sinusoid SIN_C connected at the second input of FM_MOD to A=5.0, because this controls the amplitude of the signal that the FM_MOD produces. Application Notes 11

12 Appendix Frequency Scaling for Modulation with FM_MOD The frequency scaling performed by the FM_MOD block is controlled through the Frequency Sensitivity parameter KF, specified in Hz/Volt. FM_MOD outputs a complex baseband equivalent of an FM modulated signal, as follows [2]: t FM() t = A exp LO j 2πf LO, OFF t + j 2π KF v( τ) dτ 0 (4) where A LO, and f LO, OFF are the amplitude and offset-frequency of the second input of the FM_MOD block, the Local Oscillator, denoted in Figure 1 as Tx LO. The signal is centered in frequency at the center-frequency of the LO. From equation (4), if the LO is set up to have a center-frequency of 10 KHz and zero offset-frequency (as is done in this simulation), then a constant modulating input of 1.0 to the FM_MOD block produces a tone which is offset from the 10 KHz center-frequency by KF Hz. Since VSS is a discrete-time simulator, instead of equation (4), in reality a sampled output is generated by FM_MOD as follows, ignoring the offset-frequency now, since it was set to zero inside the SIN_C block acting as the Tx LO in this simulation: k FM[ k] = A LO exp j 2π KF T s vm [ ] m = 0 where T s is the sampling period, equal to the inverse of the sampling frequency, not to be confused with T, which is the symbol (or, in this case, bit) interval and is equal to the inverse of the baud rate (or, in this case, bit rate). The relationship between the two is: T = SMPSYM T s This means that within one bit period T, in which the modulating signal is 1.0 (corresponding to bit 1), the phase of the FM modulated signal increases by: (5) (6) ϕ T = 2π KF T s SMPSYM = 2π KF T (7) 12 Visual System Simulator

13 References In the FSK_SRC block, with rectangular frequency pulse shape 1REC (see [1]), as specified in the parameter list for FSK_SRC, the frequency pulse shape is: gt () 1 = t T 2T, (8) and the phase change during a bit interval when a logical 1 is modulated is given by: T θ T = 2π h g( τ) dτ 0 SMPSYM 2π h T 1 = s T 1 = 2π h T s SMPSYM T = π h since, from equation (6) we have T = SMPSYM T s. (9) Therefore, by requiring that the phase changes caused for the same modulated bit (a logical 1) be the same, and combining equations (7) and (9), we get: ϕ T = θ T KF = h T (10) Since 1/T in equation (10) is the symbol rate, it is clear that to produce binary FSK with a certain modulation index h using the FM_MOD block, you must set h its frequency sensitivity to KF = -- SYMBOLRATE. Thus the decision in the 2 h Binary FSK Modulation in VSS section to set K f = is justified, 2 since the symbol rate in this simulation is 1000 bits/sec. REFERENCES [1] Fuqin Xiong, Digital Modulation Techniques, Artech House, Boston, [2] Applied Wave Research Inc., Visual System Simulator: System Block Catalog, El Segundo, CA Application Notes 13

DIGITAL COMMUNICATIONS SYSTEMS. MSc in Electronic Technologies and Communications

DIGITAL COMMUNICATIONS SYSTEMS MSc in Electronic Technologies and Communications Bandpass binary signalling The common techniques of bandpass binary signalling are: - On-off keying (OOK), also known as