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1 doi:.38/nture Mteril nd device stck optimiztion Lower electroforming voltges reduce the electricl stress s well s current overshoot during the forming, which is known risk fctor contriuting to device vriility 1. It hd een noticed tht lower forming voltges my e chieved in devices with higher conductivity, otined y comintion of oxide lyer thickness reduction nd stoichiometry djustment 2,3. In our experiments, the oxygen concentrtion ws continuously reduced y controlling the oxygen flow rte during the lyer growth to the point t which resistive switching nerly cesed. The switching voltges of such devices were close to, or less thn the electroforming voltge. However, mny devices could not e turned off fter switching nd insted were shunted, or in some cses exhiited spontneous complementry resistive switching. The oserved nonlinerity of the I-V curves of such devices ws lso not lrge enough for crossr opertion. To ddress these issues, n Al 2 O 3 lyer ws dded to the device stck. (Multilyers nd ilyers hd een used previously to improve device performnce 4,5.) An excessive increse of the Al 2 O 3 rrier thickness cuses n increse of the forming voltge, so tht n optimum thickness hd to e selected. As result of mteril nd stck optimiztion, the most suitle vlues of thicknesses for TiO 2-x nd Al 2 O 3 lyers hve turned out to e close to respectively, 3 nm nd 4 nm (Fig. S1). 2. Electricl chrcteriztion of single devices To perform electricl chrcteriztion, single 2 nm 2 nm devices of the dog-one geometry (Fig. S1) were fricted first. (The inset in tht figure shows the mteril stck prmeters; note tht they re slightly different from those in the crossr-integrted devices cf. the inset in Fig. 1 of the min text.) Figure S1 shows typicl switching curves of such single devices, otined y pplying ipolr voltge sweeps. (To exhiit the I-V curve nonlinerity etter, Fig. S1 lso shows Ohmic currents for severl resistnce vlues.) Figure S1c shows representtive endurnce test results for single devices. The dt re otined y repetedly (over 5, times totl) pplying sequence of set (-2 V, 5 µs), redout (.1 V, 1 ms), reset (2 V, 5 µs), nd gin redout voltge pulses to single device. The figure does not reflect the fct tht pproximtely 7% of the negtive pulses filed to switch off the device; however, this ehvior my e ttriuted to n imperfect endurnce setup rther thn ny deep device prolem. This conclusion is supported y the fct tht the device ws eing switched fter ech filure event. Some ging (in the form of slight degrdtion of the ON/OFF dynmic rnge) is lso visile, ut generlly the devices re rther roust. For exmple, during our experiments with the crossr circuit, ech of its memristors hd een sujected, on the verge, to 2, set/reset pulses even prior to the successful clssifiction experiment. As customry in nonvoltile memory technology, the retention test shown in Fig. S1d ws crried out with smple heted to 35 K. The device ws first switched into certin resistive stte, nd then its resistnce ws mesured repetedly y pplying mv is every 1

2 doi:.38/nture kω () 2 seconds during 5,-second time intervl. Such retention mesurements were crried out for ON (highly conductive), OFF (highly resistive), nd some intermedite sttes. Bsed kω on the -4 mesurements, the retention t room temperture is expected to exceed yers. kω 1 kω -6 Current (A) 1 MΩ Pt (25 nm) 4 kω Ti (15 nm) CurrentA (A) Current kω 6 TiO2-x (3 nm)-8 1 MΩ Al2O3 (4 nm) First Pt (35 nm) - T (5 nm) SiO2/Si Voltge V Voltge (V) c Current (A) A Resistnce 2V 2V Pulse Pulse # 4 5. Voltge (V) 5 On stte -5 Intermedite Off stte () d (A) 8 Lst Resistnce (Ω) Retention t Time (ks) Time ks 5 Figure S1. Isolted Pt/TiO2-x/Al2O3/Pt memristive devices: () typicl switching nd electroforming ehvior of -8 single device, () microgrph of single device nd its stck's structure, (c) switching endurnce under strem of ±2 V, 5-µs pulses, nd (d) retention of 3 initil sttes t 35 K. To highlight the dt trends, lrge mrkers on pnels (c) nd (d) show the results of every th mesurement t the endurnce test, nd of every 1,th mesurement t the retention test. Note tht pnel (d) shows significntly lower OFF stte currents (nd hence2 much higher ON/OFF current rtio) s compred to those of pnels () nd (c) due to higher voltges pplied to reset thetime device. (c) 3. Crossr circuit friction nd pckging.1v (Ω) (s)

3 doi:.38/nture14441 Crossr lines, 2 nm wide nd seprted y 4 nm gps, were formed on 4 silicon wfers covered y 2 nm of therml SiO 2. After the stndrd clening nd rinse, friction strted with n e-em evportion of T (5 nm)/pt (6 nm) ilyer over ptterned photoresist to form the ottom electrodes ( rows ). After liftoff, the wfer ws descum y ctive oxygen dry etching t 2 C for minutes. Then, lnket film consisting of 4-nm sputtered Al 2 O 3 rrier nd 3-nm TiO 2 switching lyer ws deposited from fully oxidized trget nd prtilly oxidized trget, respectively. This ilyer ws then removed y etching in n ICP chmer using CHF 3 plsm, while preserving it in the future crossr re y pre-deposited negtive photoresist. After stripping the photoresist in the 1165 solvent for 3h t 8 C, the wfer ws clened using mild descum procedure performed in RIE chmer for 15 seconds with mtorr oxygen plsm t 3 W. Next, the top electrodes ( columns ) consisting of 15 nm Ti nd 6 nm Pt were deposited nd ptterned using e-em evportion nd liftoff. Finlly, the wire onding pds were formed y e-em deposition of Cr ( nm) / Ni (3 nm) / Au (5 nm). All lithogrphic steps were performed using DUV stepper using 248 nm lser. After friction nd dicing, the dies were nneled in reducing tmosphere (% H 2, 9% N 2 ) for 3 minutes t 3 C. A single dye ws wire-onded (with gold wires) to the DIP4 pckge, using thermosonic onding process. The process ws simplified due to thicker Au metlliztion of the outer contcts, which lso helped to reduce overll wire resistnce. Figure S2 shows n opticl imge of dye mounted onto the pckge. It shows, in prticulr, 6 gold wires onded to the pds of ech chip side, with totl of 12 wires for the columns (top nd ottom sides of crossr) nd 12 wires for the rows (left nd right sides). Figure S2 shows n SEM imge of the crossr re of the chip. 4. Electricl chrcteriztion nd forming of crossr circuits A detiled electricl chrcteriztion ws performed on 8 section of the crossr, which ws lter utilized in the clssifiction experiment. All electricl chrcteriztions were performed using the Agilent B15A prmeter nlyzer. In ddition, the Agilent B525A switching mtrix ws employed for testing pckged crossr circuits nd crrying out the pttern clssifiction experiment. The prmeter nlyzer nd the switching mtrix were controlled y personl computer vi GPIB interfce using custom C code. All write nd red pulses were 5 μs long. For the memristor djustment, we used the V/2 scheme, in which the selected rows nd columns were voltge-ised t -V/2 nd +V/2, respectively. For device stte redout, we voltge-ised the selected column, connected the selected row to virtul ground, nd physiclly grounded ll the other lines. 3

4 doi:.38/nture mm um Figure S2. Microphotogrphs of the crossr with integrted Pt/Al 2 O 3 /TiO 2-x /Pt memristors: () the onded chip, nd () zoom-in on the crossr re. Figure 1 in the min text shows the further zoom-in on the crossr. Specificlly, we first chrcterized the virgin devices (not electroformed yet). Figures S3 nd S3 show the recorded mp of conductnces mesured t.1 V nd the corresponding histogrm, while Fig. S3c shows representtive set of dc I-V curves. After this chrcteriztion, the electroforming procedure ws performed. For the forming, qusi-dc current rmp ws pplied to the selected column line, while the selected row line ws grounded nd ll the remining (unselected) lines were kept floting. Such fixed-current technique prevents devices from n excessive stress during its electroforming, when device s resistnce drops shrply. To minimize the current lekge during forming, the lredy formed devices were switched to their low-conductive stte. More prticulrly, the devices of 2 2 surry were formed first. Then the devices in dditionl rows nd columns were formed, so tht the surry of formed devices ws grdully incresed: first to 3 3 devices, then to 4 4, nd so on. Figure S4 shows the mp of forming voltges for the working section of the crossr, while Fig. S4 shows the corresponding histogrm. Additionlly, Figure S4c shows the electroforming process dynmics (for the digonl devices, which were formed lst to complete forming of the corresponding surry) on the [I, V] plne. Following the electroforming procedure, we chrcterized the effective switching thresholds for ll devices in the working section of the crossr rry (Fig. S5). The threshold set / reset voltges were mesured y first progrmming devices to their high / low resistive sttes, nd then pplying sequence of 5-μs pulses of the pproprite polrity with grdully incresing mplitude to mesure the smllest voltge tht cused resistnce chnge y more thn 2 kω. The evolution of device conductnce during the reset nd set switching re shown in Figs. S5 nd S5, respectively, while Figs. S5c nd S5d show mps of the corresponding 4

5 Counts Current ( A) doi:.38/nture14441 effective reset nd set threshold voltges. Pnel (e) of Fig. S5 exhiits the dt from its pnels (c) nd (d) in the form of histogrms. The devices mrked with X in the threshold mps could not e switched with lrgest pplied voltges. 5.5E-7 3.7E-7 4.2E-7 3.5E-7 5.E-7 4.7E-7 4.4E-7 5.E-7 3.7E-7 3.6E-7 6.3E-7 3.7E-7 4.1E-7 4.2E-7 5.3E-7 3.3E-7 4.6E-7 5.7E-7 5.4E-7 4.9E-7 4.9E-7 4.2E-7 5.6E-7 6.E-7 4.6E-7 4.2E-7 3.6E-7 3.1E-7 2.7E-7 3.7E-7 4.4E-7 3.7E-7 3.5E-7 4.E-7 5.8E-7 4.8E-7 6.5E-7 4.1E-7 4.E-7 4.4E-7 4.5E-7 3.8E-7 5.4E-7 4.7E-7 5.9E-7 4.6E-7 4.7E-7 4.8E-7 3.6E-7 4.1E-7 4.5E-7 3.9E-7 5.E-7 3.6E-7 5.6E-7 4.8E-7 3.5E-7 4.E-7 4.3E-7 4.1E-7 3.5E-7 4.4E-7 4.6E-7 3.7E-7 4.9E-7 3.7E-7 6.E-7 3.6E-7 3.3E-7 5.1E-7 3.9E-7 4.2E-7 4.4E-7 3.3E-7 3.3E-7 4.E-7 3.9E-7 4.5E-7 4.3E-7 4.4E c 4 dev1 dev2 dev3 2 dev ( S) Voltge (V) Figure S3. Pre-formed (virgin smple) chrcteriztion of 8 section of the crossr: () color-coded conductnce mp of device conductnces mesured t.1 V, () the corresponding histogrm, nd (c) dc I-V curves of four representtive devices. The verge conductnce nd the stndrd devition of conductnces represented in pnels () nd (c) re.43 S nd.8 S, correspondingly. Of these dt, the fct most importnt for pplictions is tht the spred in effective switching voltges is nrrow enough to void the infmous hlf-select prolem. 6 For exmple, ppliction of voltge +1.4 V to ny device (esides those mrked with X) ensures its set djustment, while the hlf of tht voltge (i.e. +.7 V) is elow the smllest oserved set threshold voltge. This fct prevents disturnce of hlf-selected devices, connected to just one of voltge-ised lines. The switching threshold dt were lso importnt to identify rnge of 5

6 Count Current ( A) doi:.38/nture14441 resonle switching voltges, following two min criteri: lncing the set nd reset dynmics nd voiding permnent dmge of the devices nd hence prolonging their life c 2 3x3 4x4 5x5 6x6 7x7 8x8 9x Forming voltge (V) Voltge (V) Figure S4. Chrcteriztion of memristor electroforming in 8 section of the crossr. () Color-coded mp of the forming voltges, nd () their histogrm. (c) Typicl forming switching curves of the lst-formed devices in ech prtil rry (of the size indicted in the legend). The verge forming voltge nd the stndrd devition for the dt shown on pnels () nd (c) re, respectively, 1.91 V nd.7 V. The switching ehvior of crossr devices ws further chrcterized in stress conditions similr to those imposed y the used neuromorphic network trining procedure. In prticulr, we hve studied the evolution of device conductnce due to trin of rectngulr pulses of the sme voltge mgnitude. Figure S6 shows typicl results of such n experiment, for specific device. The experiment ws repeted three times, with different pulse mgnitudes, for oth set nd reset trnsitions. The plots show clerly sturtion effect: the conductnce chnge under the effect of single voltge pulse is grdully reduced (on the verge), so tht the conductnce reches certin vlue for ech prticulr pulse mgnitude. (This effect is summrized in Fig. 1c of the min text, which shows the finl conductnce chnge s the function of the initil conductnce.) The sturtion effect needs to e tken into ccount when conducting the neurl network 6

7 Count Conductnce ( S) Conductnce ( S) doi:.38/nture14441 experiment: s stted in the min text, it is much etter, in the eginning of network trining, to initilize devices in the middle of their dynmicl rnge, to chieve sustntil conductnce chnges in the eginning of the trining process Voltge (V) Voltge (V) c d x x x x x x e Threshold voltge (V) Figure S5. Chrcteriztion of the set nd reset thresholds of formed memristors: (, ) device conductnce dynmics under pplied voltge rmps of opposite polrities; (c, d) the effective threshold voltge mps for set nd reset trnsitions, nd (e) their histogrms. The histogrms on pnel (e) do not include the 3 devices tht could not e switched to the OFF stte with voltges ove -1.5 V; these devices re mrked with crosses on pnels (c) nd (d). The verge effective set/reset switching threshold voltges nd their stndrd devitions, for the dt shown on pnel (e) re, respectively.9 V/-1.17 V nd.1 V/.12 V. 7

8 Conductnce ( S) Conductnce ( S) doi:.38/nture V -1.2V -1.3V Pulse # V 1.2V 1.3V Pulse # Figure S6. Evolution of memristor's conductnce (mesured t.1 V) under the effect of 5-μs pulse trins of severl mgnitudes, for the () reset nd () set switching. Note tht unlike Figures S5 nd S5, this figure shows the chnge in conductnce for fixed-mgnitude pulses pplied repetedly to the sme device. The dshed lines re just guides for the eye. 5. Network trining result nlysis The key metric of neurl network clssifier trining is the difference it cretes etween network outputs induced y input ptterns elonging to different clsses. Two pnels of Figure S7 show such difference for our memristor crossr network. Nmely, these re the histogrms of the differences etween currents in the correct nd incorrect outputs for ech of 3 input ptterns. (Evidently, there re 6 such differences: for ech of 3 inputs in 3 clsses, there is one correct output nd two incorrect ones.) In perfectly trined clssifier, ll these differences hve to e positive. The top pnel shows tht efore trining, the differences re smll, nd hve rndom signs. During the trining the differences incresed, so tht, s the lower pnel shows, fter sufficient numer (in this prticulr cse, 21) of trining epochs, ll of them hve ecome positive, signling the % clssifiction fidelity. Figure S7 shows nother useful wy of understnding network dynmics during its trining, nmely the distriutions of conductnces t three phses of trining process. (Note tht the sme informtion, ut for only two phses, is presented in the inset of Fig. 4 of the min text.) For convenience, Fig. S7c shows the distriutions of the effective weights W, i.e. the differences etween the conductnces of devices tht form ech differentil pir, for the sme three phses of trining. As the dt show, the difference of the weight distriutions creted y the trining is less drmtic thn tht of the output signls, shown in pnel (), i.e. the trining imposes mostly reltive weight chnges (which re importnt for the correct clssifiction), rther thn their glol chnge. 8

9 Count Count Count Count doi:.38/nture Initil stte Epoch 21 Clss 1 'z' Clss 2 'v' Clss 3 'n' c I correct -I incorrect ( A) Device conductnce, G ( S) Initil stte Epoch 21 Epoch 54 Initil stte Epoch 21 Epoch Weight, W ( S) Figure S7. Additionl dt from prticulr pttern clssifiction experiment ( Run 1 ) for which the perfect clssifiction hs een chieved, for the first time, fter 21 trining epochs. () Histogrm of differences etween currents in the correct output (corresponding to input pttern s clss) nd other two chnnels. () Histogrm of device conductnces t the initil stte, mesured fter trining epoch 21, nd fter epoch 54 (for which clssifiction is lso perfect). (c) Histogrm of the differentil weights W defined y Eq. (3) of min text. In pnel (), the verge vlues / stndrd devitions of the mesured conductnces re 36.3 μs / 9 μs, 41.9 μs / 13 μs, nd 42.4 μs / 13.4 μs, when mesured in the initil stte, fter epoch 21, nd epoch 54, respectively. The corresponding verges / devitions of the weights in pnel (c) re -.24 μs / 2.83μS, μs / 16.8 μs, nd μs / 17.1 μs. Finlly, Figures S8 nd S9 show the weight mps mesured efore nd fter trining for 6 seprte trining experiments ( runs ). (The convergence grphs for these experiments re shown in Fig. 4 of the min text). The comprison of weight mps in Fig. S8 shows tht even though the initiliztion procedure ws similr in ll runs, there were some run-to-run vritions of the stte of sme device. (To quntify the vritions, Figs. S8 nd S9 show reltive stndrd devitions for ech of 3 weights.) 9

10 doi:.38/nture14441 Run 1 Run 2 Run E-6-1.3E E E E E E E E E E E E-6 1.5E E-6 3.1E E E E-6 6.5E E-6-3.E E E-6 2.7E E-6-2.3E E E-6-3.E E E E E E E E-6 3.3E E E E E E E-6-1.2E-7 7.5E E E E E E-6 4.6E E-5 6.E-7 8.6E E-6-2.8E E E E E E E E E E E E-6 7.E-8 3.2E-7-1.7E-6 1.9E E E E E E-7-3.8E E E E E-6 1.6E E E E E E E E E E E-6 5.5E E E-6 z v n z v n z v n Run 4 Run 5 Run E E E E E E-6-4.6E-6 4.E E-6-1.5E-7-4.6E-6 7.4E E E-6-3.5E E-6-7.6E E-6-1.2E E E E-6-2.6E E E E E E-6-7.9E-6 9.5E E-6-5.E E E E E E E E E E-6-5.8E E E E E E E E E-5-5.6E E-5-4.6E-5 5.5E E-7-1.2E-6 3.1E-6.E+ 3.5E E E E E E E E E E-6 8.E-8 8.5E E E E-7-1.3E E E E E E E E E E E-7 z v n z v n z v n Figure S8: Initil weight vlues: () the mps of initil weights W ij (in siemens) mesured in 6 seprte trining experiments ( runs ), nd () the corresponding reltive vrition, i.e. (stndrd devition)-to-(verge vlue) rtio for ech weight. On pnel (), red nd lue ckground colors indicte, respectively, negtive nd positive vlues of W ij, while on pnel (), the colors re used just to emphsize lower (greenish) nd higher (reddish) vlues. Nrrow columns with gry / white cells show positive / negtive input signls from noiseless imges of the clsses corresponding to the prticulr synptic columns - see Fig. 3 in the min text. Run 1 Run 2 Run E E E E E E E E E E E-5-2.8E-6 2.4E E-5 1.E E-6-2.6E E E E E E E E E E-6-1.5E-6 2.2E E-6-9.9E-6 1.6E E-5-6.E E-6 7.5E E E E E E-6-2.7E E E-6-1.2E E E E E E E E E E E E-7 4.9E E E E E E E E E E E E E E E E E E E E E E-5-2.8E-5 1.5E E E E E E-5 2.4E-6-7.9E-7-7.1E E E E E E-6-7.5E-6 z v n z v n z v n Run 4 Run 5 Run E E E-6-1.E-6 5.2E E E E E E E E E E-6 2.3E E E-5 1.3E E-6 7.5E-6-9.3E-6-2.5E E E-5 3.6E E E E E E E-6 2.2E E E E E-5 9.8E E E E E E E-6 1.2E-5-1.E E-6-4.3E E E E E E E-5-1.9E-5-5.2E E E E E-6 8.7E E E-5 2.6E E E E E-5 2.6E E E E-5-2.6E E E-5-2.9E E E E E E E E E E E E E-5 z v n z v n z v n Figure S9: Finl synptic weight vlues fter the network trining process convergence: () the mps of weights W ij (in siemens) mesured fter the perfect clssifiction hs een reched, for 6 seprte runs (fter, respectively, 21, 6, 33, 26, 35, nd 18 trining epochs for Runs 1, 2, 3, 4, 5, nd 6 see Fig. 4); () the corresponding reltive vrition for ech weight. The color coding is the sme s in Fig. S8.

11 doi:.38/nture14441 As Fig. S9 shows, fter trining the weights ecome mrkedly different - not only in their mgnitude, ut in mny cses lso in their sign, despite the fct tht ech finl distriution provides perfect clssifiction fidelity. This is in greement with the well-known fct tht the clssifier trining using the Delt Rule lgorithm nd its cousins (such s the Mnhttn Updte Rule used in this work) does not result in unique synptic weight distriution unless the initil weight vlues re exctly the sme in ech trining run. 6. Computer simultions We hve lso crried out extensive computer simultions of our neurl network, in order to understnd the impct of vrious prmeters, most importntly of the initil device conductnces, on clssifier s fidelity nd convergence speed. To perform the simultion, n pproximte device model ws derived from the dt shown on Fig. 1c of the min text. In this model, the conductnce increse (ΔG set ) y positive voltge pulse nd its decrese (ΔG reset ) y the negtive pulse re clculted s ΔG set (G) = + -3 ( 6 G 6 G min + vset / slope ) slope, ΔG reset (G) = - -3 (- 6 G + 6 G mx + vreset / slope ) slope, (S1) (S2) where constnt slope, for our specific pulse mplitude nd durtion ws tken equl to 2, while prmeters vset nd vreset were rndomly chosen from the rnge [1, 5.5] for every memristor efore ech run. Constnts G min = μs nd G mx = μs re the minimum nd mximum conductnce vlues; G is lwys clipped etween these vlues fter ech updte. Such simple model cptures two min fetures of the memristors, nmely the sturtion of the switching dynmics (Fig. 1c) nd switching threshold vritions (Fig. S5). Fig. S shows the most importnt results of these simultions. First, they hve confirmed tht the clssifier fidelity nd convergence speed re the est when the initil conductnces of the devices re in the middle of their dynmicl rnge. The second importnt simultion result is tht the performnce is rther insensitive to the choice of prmeter β, with the optiml vlue close to β = 2 5. As ws stted in the min text, these results hd een used t network trining. 7. Towrd prcticl pplictions We elieve tht our work is the first proof-of-concept tht pssively integrted memristive crossr circuits cn e used to perform clssifiction tsk. However, due to its smll size, this network is not y itself prcticl, nd severl mjor steps hve to e mde towrd lrger, useful neuromorphic networks. Besides the primry, self-evident tsk of friction much lrger crossrs with smller memristors of (t lest) similr qulity nd reproduciility, there is lso chllenge of their 11

12 <epochs to convergence> Convergence Convergence, 5 % epochs doi:.38/nture14441 efficient trining. For lrge crossr, the tch trining lgorithm descried in the pper would come with sustntil circuit overhed, if it is fully implemented on the sme chip s the network. In fct, in the tch mode, the trining circuit hs to hold t lest ~M 1 M 2 continuous intermedite vlues, for exmple numers ij, prticipting in Eq. (5), until the next weight updte. (Here M 1,2 re the liner sizes of the crossr rry.) Such trining circuit, implemented in the usul CMOS technology, would hve much lrger chip footprint thn the crossr itself β rf rf rf.2 rf β rf rf rf.2 rf Initil conductnce, initil stte G (μs) Initil conductnce, initil stte G (μs) Figure S: Mjor results of computer simultion of our neurl network, using relistic memristor model. () The numer of trining epochs required to chieve the perfect clssifiction, nd () the frction of trining experiments with the perfect convergence, s functions of the initil memristor conductnces. Ech point is n verge over runs; for ech run the weights were rndomly initilized within 5-μS conductnce window round the vlue indicted on the horizontl xis. If n experiment took more thn 5 epochs for convergence, for the purposes of pnel (), it ws considered filure. These "filed" experiments were excluded when clculting the error rs on pnel (). However, severl fctors mke this tsk less hopeless thn it my look. First of ll, for most importnt prcticl pplictions, neurl network is used repetedly for clssifiction of ptterns of the sme type. In these cses it needs to e trined only in the eginning, nd then my e used with the sme set of weights for long time. (In fct, this is the pproch used in most dvnced recent demonstrtions of neurl network hrdwre chips. 7,8 ) Such rre trining my e ssisted y externl (digitl) computers which, in prticulr, would store ll the intermedite vlues. According to our recent results, 9 this pproch hs sustntil dvntges over purely ex-situ trining in precursor softwre network, with the susequent synptic weight import into the crossr (s discussed, e.g., in Ref. 2 of the min text), ecuse the former procedure llows to mitigte detrimentl effects of memristor nd lso neuron circuits vriility. Another opportunity is to trin the network in situ, using locl online ( stochstic ) trining procedure, for which the requirements to externl memory would e sustntilly reduced. In this cse, just one circuit per ech line nd column of the memristive crossr, i.e. ~(M 1 +M 2 ) circuits per n M 1 M 2 memristors, my e sufficient to implement ll trining nd 12

13 # missclssified ptterns doi:.38/nture14441 neuron functions. As the crossr is scled up in future for more complex tsks (up to M 1.2 ~ 3-4 deemed necessry for some cognitive rchitectures), the reltive size of this circuit overhed would e much decresed. Figure S11 shows some results of our preliminry ttempt t implementing online trining lgorithm using the sme memristive crossr. Perfect clssifiction hs een chieved for the used smll set of input ptterns, ut unfortuntely, in its current form the online lerning requires too mny synptic updtes to chieve the perfect network performnce. Another importnt question which must e ddressed in prcticl ppliction is the generliztion performnce of the clssifier. As Fig. S11 shows, for online trining we could rech perfect clssifiction performnce on smll seprte test set. However, this trining ws too slow for our sic experiments with 3 imges in 3 clsses. As stted in the min text, these experiments were crried out without seprte test set, ut using the mesured vlues of weights recorded fter every trining epoch, we could use computer simultions to estimte network's generliztion ility, i.e. its possile clssifiction performnce on seprte test set (not used t trining). The set consisted of ll possile ptterns (36 ptterns in ech of 3 clsses) otined from the idel imges (Fig. 2c of min text) y flipping 2 pixels see Fig. S12. Though the clssifiction improved during trining (Fig. S12), typiclly it is not perfect y its end. This is not surprising, giving the fct tht the minimum Hmming distnces etween ptterns of the test nd trining sets re 2 nd 4, ccordingly. Indeed, even humn would hrdly e le to clssify ll these ptterns correctly plese hve one more look t Fig. S Trining set Test set x i Trining set Test set Itertion # c v Figure S11: Preliminry results for pttern clssifiction experiment using online ("stochstic") Mnhttn Rule trining: () Clssifiction convergence for the trining nd test sets, nd () used sets. On pnel (), "itertion" mens n ppliction of one pttern from trining set, followed y the corresponding weight updte. (There were 12 itertions in trining epoch.) Note tht here perfect clssifiction ws chieved on the (dmittedly, extremely smll) test set. (The evlution on this set ws performed only t the end of trining.) 13

14 # misclssified ptterns doi:.38/nture14441 As result, we elieve tht convincing demonstrtion of the generliztion ility is only possile on lrger input vectors, which in turn require lrger networks (nd hence lrger crossr rrys). Such demonstrtion remins one of our mjor future gols Test set 26% misclssifiction Trining set Epoch z v n Figure S12: Pttern clssifiction experiment (Run 1): () Clssifiction convergence for the trining nd test sets, nd () the used test set. (The trining set nd the trining method were the sme s descried in min text). The ottom figure on pnel () shows one of the curves (lck one) from Fig. 4, extended to the susequent trining epochs. References 1. Young-Fisher, K. G. et l. Lekge current-forming voltge reltion nd oxygen gettering in HfO x RRAM devices. IEEE Electron Device Lett. 34, (213). 2. Yng, J. J. et l. The mechnism of electroforming of metl oxide memristive switches. Nnotechnology 2, (29). 3. Lentz, F. et l. Current complince-dependent nonlinerity in TiO 2 RRAM. IEEE Electron Device Lett. 34, (213). 4. Goux, L. et l. Ultrlow su-5na operting current high-performnce TiN/Al 2 O 3 /HfO 2 /Hf/TiN ipolr RRAM chieved through understnding-sed stck-engineering. VLSI Symp. Technol. 12, (212). 5. Wu, H. et l. Resistive switching performnce improvement of T 2 O 5-x /TO y ilyer ReRAM devices y inserting AlO δ rrier lyer. IEEE Electron Device Lett. 35, (214). 6. Strukov, D. B., Likhrev, K. K. Reconfigurle nno-crossr rchitectures. Nnoelectronics nd Informtion Technology, Wser, R. (ed.), 3rd ed. (Wiley, Weinheim, Germny, 212). 7. Meroll, P. A. et l. A million spiking-neuron integrted circuit with sclle communiction network nd interfce. Science 345, (214). 14

15 doi:.38/nture Fret, C. et l. NeuFlow: A runtime reconfigurle dtflow processor for vision. CVPRW 11, (211). 9. Ktev, I. et l. Efficient trining lgorithms for neurl networks sed on memristive crossr circuits. sumitted to IJCNN 15, (215), ville online t