EFFICIENT FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF A CONVOLUTIONAL TURBO CODE FOR LONG TERM EVOLUTION SYSTEMS

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1 Électronque et transmsson de l nformaton EFFICIENT FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF A CONVOLUTIONAL TURBO CODE FOR LONG TERM EVOLUTION SYSTEMS CRISTIAN ANGHEL, CRISTIAN STANCIU, CONSTANTIN PALEOLOGU 111 Key words: Long term evoluton (LTE), Turbo codes, Feld programmable gate array (FPGA) mplementaton, Maxmum logarthmc (Max log) - maxmum a posteror probablty (MAP). Ths paper descrbes an effcent Feld programmable gate array (FPGA) mplementaton of a convolutonal turbo code (CTC) decoder for long term evoluton (LTE) standard, release 8, usng maxmum logarthmc maxmum a posteror probablty (Max Log MAP) algorthm. The consdered codng rate s 1/3 (the natve codng rate), the puncturng procedure not beng taen nto dscusson here, and the number of turbo teratons s chosen as 3, wthout reducng the generalty of the reported results. The hardware mplementaton targets a Xlnx Vrtex 5 XC5VFX70T devce, from a Xlnx ML507 evaluaton board. 1. INTRODUCTION Turbo codes were ntroduced by Berrou, Glaveux, and Thtmashma [1 3], but the ntal percepton of the method was not a promsng one, especally because of the good reported results compared wth the exstng forward error codng (FEC) solutons. Once the authors were able to prove the strengths and the valdty of the proposed archtecture, more and more standards started to nclude turbo codes, as recommended n the frst phase and fully mandatory afterwards. Ths evoluton was possble as the processng power ncreased and the complexty of the turbo codes versus the classcal convolutonal codes was not a bottlenec anymore. Nowadays, the computatonal power of devces such as dgtal sgnal processors (DSPs) or feld programmable gate arrays (FPGAs) allows the mplementaton of turbo encodng/ decodng, but the complexty of the general archtecture (for example, the entre dgtal baseband processng for an long term evoluton (LTE) base staton) requres further optmzaton for all the blocs n the scheme. Poltehnca Unversty of Bucharest, Iulu Manu 1 3, Sect 5, Bucharest, room B102, E:mal: {canghel, crstan, pale}@comm.pub.ro1 Rev. Roum. Sc. Techn. Électrotechn. et Énerg., 60, 2, p , Bucarest, 2015

2 164 Crstan Anghel, Crstan Stancu, Constantn Paleologu 2 One of the most mportant standardzaton groups whch early adopted the turbo codes s the thrd-generaton partnershp proect (3GPP) [4]. In the frst verson of Unversal Moble Telecommuncatons System (UMTS), released n 1999, turbo codes were ncluded for the frst tme as an FEC soluton, n addton to the tradtonal convolutonal codes. Along wth the evoluton of the UMTS standard, whch brought hgh data throughput once the hgh speed pacet access (HSPA) feature was ntroduced, the turbo codng archtecture remaned unchanged because of the elevated performance t provded. Furthermore, once the leap forward was made to the fourth generaton LTE [5, 6] technology, turbo codes ept ther core structure and ey role n reducng transmsson errors. In other words, the same consttuent encoder s currently used n both UMTS and LTE. The man dfference ntroduced by LTE refers to the nterleavng bloc, whch s now a quadratc permutaton polynomal (QPP), a bloc sutable for hgh data rates obtaned especally n parallel decodng archtectures. The arthmetcal propertes for the QPP nterleaver allow the parallelzaton of the decodng process nsde the algorthm, tang advantage on the man prncple ntroduced by turbo decodng,.e., the usage of extrnsc values from one turbo teraton to another. However, the goal of ths paper s to provde an effcent hardware mplementaton for the man ndvdual components of a turbo decodng archtecture, the QPP nterleaver, respectvely the Soft Input Soft Output (SISO), wth a drect mpact on both seral and parallel decodng schemes. On the same tme, no dscusson wll be made on the well-nown methods [7] used to reduce the decodng latency for the selected algorthm nsde a SISO unt. Ths paper s organzed as follows. Secton 2 ntroduces the LTE turbo codng structure. In Secton 3, the selected maxmum logarthmc - maxmum a posteror probablty (Max Log MAP) decodng algorthm s detaled, all the equatons for a bnary nput beng deduced. Secton 4 presents the proposed hardware decodng archtecture for a seral approach. In Secton 5, the decodng performances are dscussed n terms of bt error rate (BER) versus sgnal to nose rato (SNR) and speed versus requred hardware resources when targetng an XC5VFX70T FPGA chp [8] on the Xlnx ML507 [9] evaluaton board. Secton 6 presents the fnal conclusons and the perspectves of ths study. 2. LONG TERM EVOLUTION CODING STRUCTURE The LTE codng structure s a parallel concatenated convolutonal code (PCCC), comprsng of two consttuent encoders and one nterleavng bloc. Each ndvdual 8-state consttuent encoder has the followng transfer functon: G D) = [ 1, g ( D)/ g ( )], (1) ( 1 0 D where D denotes the elemental delay bloc and:

3 3 Feld programmable gate array mplementaton of a turbo decoder D g ( D) = 1+ D + D ; g ( D) = 1+ D +. (2) The natve codng rate of the encodng structure s 1/3 snce the nput sequence C ( = 1 K, where K denotes the length of the uncoded data bloc) s sent at the output of the encoder as the systematc sequence X and each ' consttuent encoder generates on ts own a party sequence Z, respectvely Z. The nterleaved sequence C ' s obtaned from C, after the nterleaver module reorganzes the nput bts ' C = C, = 1...K, π( ) (3) where the length K of the nput data and parameters f 1 and f 2 provded n Table n [6] are used to generate addresses: 2 π( ) = ( f + f ) mod K. (4) MAX LOG MAXIMUM A POSTERIORI DECODING ALGORITHM In terms of turbo decodng algorthms, the classcal MAP algorthm provdes the reference results, although t s not sutable for practcal mplementatons, ts man drawbacs beng the large dynamcal range of the varables and the prohbtve arthmetc complexty. Ths s the reason why suboptmal versons of the MAP algorthm were ntroduced and studed n the lterature. Some of the most popular alternatves to the reference MAP are log MAP (logarthmc MAP) [10, 11], ln log MAP (lnear logarthmc MAP) [12], const log MAP (constant logarthmc MAP) [13] and max log MAP. All these optons use logarthmc representatons n order to compensate for the frst mentoned drawbac. Furthermore, from the Jacob logarthm expresson [14]: ln(e x y y x + e ) = max( x, y) + ln(1 + e ), (5) the second rght term s approxmated by the dfferent methods mentoned above,.e., ether as a constant, lnear values from a pre-stored table or ust gnored (the max log MAP approach). For the LTE turbo codng, the theoretcal decodng scheme s presented n Fg. 1. Same decodng structure was presented n [15] for UMTS. One can notce the nput log lelhood ratos (LLRs) for systematc bts Λ X ) and for party bts ( ' Λ Z ) and Λ ( Z ), the output LLRs for decodng unt 1 (SISO 1) Λ ( X ), ( O 1

4 166 Crstan Anghel, Crstan Stancu, Constantn Paleologu 4 O ' 2 respectvely for decodng unt 2 (SISO 2) Λ ( X ), and the extrnsc value W ( X ). Also, the man prncple of the turbo decodng can be observed,.e., the nput of one decodng unt contans the prevously computed output of the other decodng unt. Fg. 1 LTE turbo decodng scheme. Fg. 2 LTE turbo coder trells. Insde each SISO unt, the max log MAP equatons for bnary nput are deduced from the correspondng consttuent encoder trells depcted n Fg. 2. There are 8 states on each stage of the trells and each dagram state permts 2 nputs and 2 outputs. Frst, the branch metrcs between states S and S are computed (2 such metrcs for each state from the total of 8 correspondng to each stage of the trells): γ = V ( X ) X (, ) + Λ ( Z ) Z(, ). (6) In concluson, there are 16 branch metrcs to be computed at each stage, but n realty there are only 4 possble values for these metrcs: γ γ 0 2 = 0, = Λ ( Z ), γ 1 γ = V ( X 3 = V ( X ) ) + Λ ( Z. (7) ) The next step n max log MAP algorthm s to execute the bacward recurson when the bacward metrcs are computed. The bacward metrc for the

5 5 Feld programmable gate array mplementaton of a turbo decoder 167 state S at the th stage sβ ( S ), 2 K + 3 and 0 7. The bacward recurson s ntalzed wthβ K + 3( S ) = 0, 0 7. From the stage = K+2 untl the stage = 2, the computed bacward metrcs are: βˆ {(β ( S ) + γ ), (β ( S ) γ )} = ( S ) max +, (8) + where βˆ ( S ) represents the un-normalzed metrc and S 1 and S 2 are the 2 states from stage +1 connected to state S at stage. Once that at each stage the metrc βˆ ( ) s computed, the rest of the 7 bacward metrcs are normalzed and stored: S 0 β 0 ( S ) = βˆ ( S ) βˆ ( S ). (9) In a smlar manner, the forward recurson s performed. For stage 0, the forward metrcs are ntalzed α 0 ( S ) = 0, 0 7, and then, from stage = 1 untl stage = K the un-normalzed/ normalzed forward metrcs are computed: αˆ α ( S ( S ) = max ) = αˆ {( α ( S ) + γ ), ( α ( S ) + γ )}, ( S -1 ) αˆ 1 ( S 0 No storng s needed for the forward metrcs. Once they are computed for stage, the decodng algorthm can compute n the same tme a LLR estmate for the data bts X. Ths LLR s found the frst tme by consderng that the lelhood of the connecton between the state S at stage -1 and the state S at stage s: ) λ 1 2 (10) (, ) = α ( S ) + γ + β ( S ). (11) The lelhood of havng a bt equal to 1 (or 0) s when the Jacob logarthm of all the branch lelhoods corresponds to 1 (or 0) and thus: { λ (, ) } max { λ (, )}. Λ 0 ( X ) = max (12) ( S S ): X = 1 ( S S ): X = 0 4. PROPOSED HARDWARE DECODING ARCHITECTURE The proposed hardware decodng scheme depcted n Fg. 3 represents an adaptaton of the theoretcal decodng structure presented n Fg. 1. It was ntroduced by the authors n [16] for an WMAX CTC turbo decoder. As prevously mentoned, the ey of the turbo decodng s the teratve usage of the decodng nformaton between the 2 SISO unts. A natural concluson arses,.e., whle one SISO unt s decodng the nput nformaton, the second one ust wats the fnsh of the process before startng ts own decodng phase. Moreover, snce the nterleaver/ denterleaver modules are processng the nformaton n a frame-

6 168 Crstan Anghel, Crstan Stancu, Constantn Paleologu 6 based manner, all the decoded data should be avalable before startng these procedures. In other words, only one SISO unt may be used n the decodng archtecture. In Fg. 3, there are 3 dotted-lne memory blocs. These are vrtual memores, added ust for a clear understandng of the scheme. In realty, these memory blocs are not needed snce the correspondng data s computed and further used n the same tme. Fg. 3 Proposed seral turbo decodng scheme. Also, one pont that should be mentoned s that the nterleaver and denterleaver blocs have the same hardware structure, ncludng a bloc memory and an nterleaver. The memory s wrtten wth the nterleaved addresses each tme a new data bloc s receved. The values are then used as read addresses (when nterleaver process s ongong) or as wrte addresses (when denterleaver process s ongong). More precsely, ths memory bloc used by the nterleaver s not a huge pre-stored ROM memory, but a K max (for LTE the value s 6144) locaton RAM memory, whch s wrtten offlne each tme a new encoded data bloc s receved. Ths memory bloc, together wth the 3 memory blocs from the left sde of the pcture (for the nput data) are swtched-buffers, allowng new data to be wrtten whle the prevous one s stll under decodng process, so that no addtonal delay to be added n the total decodng latency. The scheme mplements the relatons ncluded n Fg. 4. The most complex bloc of the nterleaver remans n ths case the modulo K bloc. One mplementaton soluton for ths bloc s to consder themodulo result as the remnder of a dvson. In ths case, the remnder results correspond to a classc dvder-for-ntegers scheme. The restorng nteger dvson scheme mght be a sequental one,.e., a new set of nputs can be receved only after the prevous one was processed. Ths reduced overall processng speed s not attractve, even though the scheme uses few resources (264 Flp Flop regsters and MHz for the Vrtex 5 targeted devce). An accepted soluton s a ppe-lne radx-2 nonrestorng nteger dvson [17]. Such a dvder s avalable n Xlnx Core Generator

7 7 Feld programmable gate array mplementaton of a turbo decoder [18], the prce for reduced latency beng the ncreased amount of used resources (the complete nterleaver wth such a dvder uses 1578 Flp Flop regsters and MHz for the Vrtex 5 targeted devce). Fg. 4 Proposed nterleaver scheme. The second bloc from Fg. 3 that s crtcal for decoder performances and costs s the SISO decodng unt. The proposed scheme for mplementaton s descrbed n Fg. 5. Fg. 5 Proposed scheme for SISO decodng unt. All modules are mplementng n a dedcated manner the relatons provded n Secton 3. Each gamma (branch metrc), beta (bacward metrc) and alpha (forward metrc) s computed wth a dedcated hardware. At each stage, 16 gamma values should be theoretcally computed, but n realty only 4 possble values exsts, one of them beng 0. Then the 2 sums from (8) are computed for each of the 8 states n BETA bloc. The correspondng max functon s appled n the MUX MAX bloc. Beng a recursve process, after normalzaton, the 7 obtaned beta values from one stage are used at the next one after beng delayed n the 7xD module and also are stored n the MEM BETA memory. For alpha values the procedure s smlar, except that no storng s needed snce rght after the LLRs are computed n the L module. The NORM bloc performs the fnal normalzaton before provdng the output LLRs.

8 170 Crstan Anghel, Crstan Stancu, Constantn Paleologu 8 5. PERFORMANCES AND IMPLEMENTATION RESULTS Ths secton presents the obtaned results for the proposed turbo decoder whle smulated n fnte/ nfnte precson, n dfferent rado envronment (AWGN or Raylegh channels), wth dfferent confguraton settngs (varable data bloc length K) and wth dfferent decodng parameters (1 to 5 turbo teratons). All pctures descrbe BER versus SNR. Fgure 6 depcts the decodng performances degradaton when fnte precson s used versus nfnte precson. For fnte precson, a 10 bts format s used, one bt for the sgn, 6 bts for the nteger part and 3 bts for the fractonal part. The results are provded for a 512 bts data bloc, wth quadrature phase shft eyng (QPSK) modulaton, after 3 turbo teratons over an AWGN channel. Fgure 7 compares the obtaned turbo decoder performances over an AWGN channel, respectvely over a Raylegh channel characterzed by slow fadng and frequency selectve fadng. Infnte precson was used for both curves, 512 bts data bloc, wth QPSK and 3 turbo teratons. Fgure 8 presents the dependency between the turbo decodng performances and the turbo teratons number, 512 bts data blocs and QPSK modulaton were used. 3 teratons provde best balance between latency and performances. Fgure 9 depcts the turbo decodng performances versus data bloc length QPSK, K=512, 3 teratons nfnte precson fnte precson 10-2 BER SNR [db] Fg. 6 Infnte vs. fnte precson QPSK, K=512, 3 teratons AWGN Raylegh 10-2 BER SNR [db] Fg. 7 AWGN vs. Raylegh channel.

9 9 Feld programmable gate array mplementaton of a turbo decoder QPSK, K=512, AWGN ter=1 ter=2 ter=3 ter=4 ter= BER SNR [db] Fg. 8 Varaton vs. number of teratons QPSK, 3 teratons, AWGN K=40 K=512 K= BER SNR [db] Fg. 9 Varaton vs. data bloc length. 6. CONCLUSION Ths paper presented n the frst part the prncples of LTE turbo codng and the general turbo decodng scheme. For the decodng algorthm, max log MAP equatons were then presented. Based on these equatons, an effcent FPGA mplementaton soluton for an LTE turbo decoder was proposed. The man two blocs of the archtecture were the nterleaver and the SISO decodng unt. For the nterleaver, a smplfed scheme was proposed, based on the usage of 3 smlar accumulators and one ppe-lne radx-2 non-restorng nteger dvsor. Even for ths smplfed scheme, our team contnues the efforts to reduce the complexty, manly provded by the dvder, by splttng the related arthmetc so that modulo result to be maxmum 2, scenaro that requres smplfed dvson scheme. The second bloc, the SISO decodng unt, was mplemented n an effcent manner by tang advantage on the repettve max log MAP equatons for computng branch metrcs, the bacward metrcs and the forward metrcs.

10 172 Crstan Anghel, Crstan Stancu, Constantn Paleologu 10 The obtaned decodng performances were provded, pontng on one hand the small degradaton ntroduced by a 10 bts numercal representaton format, and on the other hand comparng the smulaton results when the rado envronment was changed, when the transmsson parameters were modfed and when the decodng settng were also changed. Receved on December 6, 2014 ACKNOWLEDGMENTS The wor has been funded by the Sectoral Operatonal Programme Human Resources Development of the Mnstry of European Funds through the Fnancal Agreement POSDRU/159/1.5/S/ REFERENCES 1. C. Berrou, A. Glaveux, Near optmum error correctng codng and decodng: Turbo-Codes, IEEE Trans. Communcatons, 44, 10, pp , C. Berrou, M. Jézéquel, Non bnary convolutonal codes for turbo codng,electroncs Letters, 35, 1, pp. 9 40, C. Berrou, A. Glaveux, P. Thtmashma, Near Shannon lmt error-correctng codng and decodng: Turbo Codes, IEEE Proceedngs of the Int. Conf. on Communcatons, Geneva, Swtzerland, 1993, pp *** Thrd Generaton Partnershp Proect, 3GPP home page 5. F. Khan, LTE for 4G Moble Broadband, Cambrdge Unversty Press, New Yor, *** 3 rd Generaton Partnershp Proect; Techncal Specfcaton Group Rado Access Networ; Evolved Unversal Terrestral Rado Access (E-UTRA); Multplexng and channel codng (Release 8), Techncal Specfcaton, 3GPP TS V8.7.0 ( ). 7. S. Chae, A low complexty parallel archtecture of turbo decoder based on QPP nterleaver for 3GPP-LTE/LTE-A, 8.*** Xlnx Vrtex 5 famly user gude, 9.*** Xlnx ML507 evaluaton platform user gude, P. Robertson, E. Vllebrun, P. Hoeher, A Comparson of Optmal and Sub-Optmal MAP Decodng Algorthms Operatng n the Log Doman, Proc. IEEE Internatonal Conference on Communcatons (ICC 95), Seattle, 1995, pp C. Vladeanu, S. El Assad, Hybrd Maxmum-Lelhood Detector for Trells Coded Spatal Modulaton, Rev. Roum. Sc. Techn. Électrotechn. et Énerg., 57, 4, pp , J. F. Cheng, T. Ottosson, Lnearly approxmated log-map algorthms for turbo decodng, Vehcular Technology Conference Proceedngs, VTC 2000, Toyo; IEEE 51 st, 3, pp , S. Papaharalabos,P. Sweeney, B.G. Evans, Constant log-map decodng algorthm for duo-bnary turbo codes, Electroncs Letters, 42, 12, pp , J. H. Han, A. T. Erdogan, T. Arslan, Hgh Speed Max-Log-MAP Turbo SISO Decoder Implementaton Usng Branch Metrc Normalzaton, Proceedngs of the IEEE Computer Socety Annual Symposum on VLSI New Fronters n VLSI Desgn, May 2005.

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