Class-E power amplifier and its linearization using analog predistortion

Transcription

1 Indian Journal of Engineering & Materials Sciences Vol. 19, April 2012, pp Class-E power amplifier and its linearization using analog predistortion P Sampath* & K Gunavathi Department of Electronics & Communication Engineering, PSG College of Technology, Coimbatore , India Received 11 January 2011; accepted 9 April 2012 In this paper, power amplifier operating with center frequency of MHz, which can be used for the transmitter in beamforming systems, is proposed. The power amplifier implemented provides high power added efficiency (PAE) of % and low noise figure (NF) as low as The linearity of the power amplifier is improved by using square law and cubic law analog predistortion techniques. The power amplifier is designed and implemented using 0.35 µm CMOS technology. The power amplifier implemented provides high SNR of and the linearity is improved by suppressing the power in the 2 nd and 3 rd order harmonics. Keywords: Power amplifier, Linearization, PAE, NF, IIP3 Power amplifiers (PAs) are used in the transmitter to enable power amplification of baseband signals. The selection of power amplifiers for the transmitter is based on the efficiency and linearity of the amplifier. To achieve high efficiency, Class E power amplifiers are preferred. Class E power amplifiers operate with power losses lesser than class B or class C amplifiers. They can be constructed with silicon or gallium arsenide semiconductors in CMOS technology. Class E power amplifiers can be designed for narrowband operations and give maximum output power for 50% duty cycle. High power amplifiers in the base stations and the repeaters for wireless systems need extremely high linearity. But the drawback of Class E power amplifiers is the nonlinearity of the amplifier. This drawback can be improved by linearization techniques like analog predistortion, digital predistortion, feed forward predistortion etc. In this paper, an attempt is made to linearize the power amplifiers using analog predistortion method. CMOS Power Amplifiers Power amplifiers are designed to work with high efficiency using active devices like BJT, FET and MOSFET. Class-E power amplifiers were initially described using BJT as switching device 1. There is a major loss of power in these amplifiers due to power dissipation in the output active devices. Therefore. care has to be taken to minimize the power dissipation in power amplifiers designed to work at *Corresponding author ( sampathpalaniswami@gmail.com) high frequencies. To reduce the power dissipation, the voltage across the device can be minimized when current flows or the current through the device can be minimized when voltage exists across it. The comparison of different classes of power amplifiers 2 is given in Table 1. All the power amplifiers mentioned in Table 1 use active device for power amplification. In switching amplifiers Class-E has maximum efficiency, minimum Device utilization factor (DUF) and the power dissipation will be low. Hence, the implementation of Class E power amplifiers is considered in this paper. Efficiency is maximized in the amplifier by minimizing power dissipation, while providing a desired output power. The circuit of Class E PA is shown in Fig. 1. R L is the load resistor, f is the design frequency for the power amplifier, P a is the output power delivered to the load and Q L is the network loaded Q whose value is chosen as for 50% duty cycle 3. L, C 1 and C 2 form the load network. The output power depends on the effective dc supply voltage. The effective dc supply voltage is VD D VDS ( sat ), where V DD is the actual supply voltage and V DS(sat) is the MOSFET saturation offset Table 1 Comparison of different classes of power amplifiers Class DUF %Efficiency A B C D E F S

2 SAMPATH & GUNAVATHI: CLASS-E POWER AMPLIFIER 145 voltage. V DS(sat) is zero for MOSFET. This is another reason for choosing MOSFET as the active device for designing the power amplifier. V DD is 3.3 V for 0.35 µm CMOS technology. The design equations 3 for BJT are modified for NMOS and used for finding the circuit components of the Class E PA shown in Fig. 1 are as follows: 2 ( V 0.577( ) 2 DD V ( ) ) D 2 V S sat DD VDS ( sat ) RL = 2 = Pa π Pa (1) QL RL L = 2π f (2) 1 1 C1 = = 2 π π 2π frl π frl C = C 1+ QL QL (3) (4) The advantage of having MOSFET is that, the oxide layer between the gate and the channel prevents dc current from flowing through the gate. This reduces power consumption and gives very large input impedance, which enhances the digital switching. The insulating oxide between the gate and channel effectively isolates a MOSFET in one logic stage from earlier and later stages, which allows a single MOSFET output to drive a considerable number of MOSFET inputs. This isolation makes it easier to ignore to some extent loading effects between logic stages independently. MOSFET provides maximum power output capability (c p ) and allow a single MOSFET to function as a switch. As the output power capability c p increases, the maximum output power P O(max) also increases. The maximum output power P O(max) of an amplifier with a transistor having the maximum ratings of drain current I DM and drain to source voltage V DSM is P O(max) = cpidmvdsm (5) Class-E amplifier operating at center frequency of MHz suitable for beamforming systems at the transmitter of the base station in MHz band and with bandwidth of 25 MHz is proposed. The power amplifiers are implemented using 0.35 µm CMOS technology. The maximum frequency that the 0.35 µm CMOS technology can support is given in terms of unity-gain frequency 4 (f T ). Unity-gain frequency of N-channel MOSFET (NMOS) used for the design of PA using 0.35 µm CMOS technology is the frequency at which the current gain of the MOSFET is unity. The unitygain frequency for this NMOS is found using AC simulation. In the AC simulation the operating point of NMOS device was selected to be 2.5 V for both VGS and VDS, saturated with a significant overdrive voltage in order to minimize the non-quasi static (NQS) effects. The operating point is selected to allow for sizeable signal without any clipping. The dc operating point has a direct effect upon a transistor's cutoff frequency. A larger dc drain current will directly increase the device transconductance, thereby directly increasing the cutoff frequency as given in Eq. (6). f T Fig. 1 Circuit of Class-E power amplifier Fig. 2 Circuit for finding f T of NMOS transistor Iout 1 gm = = Iin 2π C + C + C + C g gb gso gdo (6) Where g m is the fundamental device transconductance; C g, C gb, C gso, and C gdo are the intrinsic input capacitance, the gate-to-bulk capacitance, the gateto source overlap capacitance, and the gate-to-drain overlap capacitances, respectively. Figure 2 shows the

3 146 INDIAN J ENG. MATER. SCI., APRIL 2012 circuit for finding f T of NMOS and the f T obtained is shown in Fig. 3. Input current of 1 ma is given at the gate of the NMOS transistor which is biased with dc voltage of 2.5 V. The voltage at the drain is 3.3 V. AC simulation is performed to find the variation of current gain with respect to frequency. The f T obtained from ac simulation is shown in Fig. 3. In Fig. 3, i gain denotes the current gain which is the ratio of output (drain) current to input (gate) current of common source NMOS device. The marker m 1 shows that at unity current gain the frequency is 18.3 GHz. For the NMOS with length (L) of 0.4 µm and width 221 µm the unity gain frequency of the NMOS is 18.3 GHz. If this NMOS is used for implementing power amplifier at center frequency of MHz, there will not be any NQS effects as there will not be any phase deviation till 20% of 18.3 GHz, i.e., 3.66 GHz and no amplitude variations till f T. Hence, this NMOS can be used to implement power amplifier at center frequency of MHz. The drain current measured for the NMOS is 18 ma at MHz. The operating point (V DS, I D ) for NMOS device at MHz is (2.5 V, 18 ma). The design specifications for power amplifier include center frequency (frequency of operation), bandwidth, power added efficiency (PAE), noise figure (NF), signal to noise ratio (SNR), spurious free dynamic range (SFDR) and power consumption. The design specification of the power amplifier operating in the specified band of frequency is given in Table 2. Based on the design equations, for the specifications mentioned in Table 2 the values of the components used in the circuit of power amplifier is given in Table 3. Simulation of the Power Amplifier The various simulations performed are transient simulation, S-parameter simulation, ac simulation, load pull simulation and harmonic balance simulation. Transient simulation is performed to find whether the product of voltage and current is low during the RF period. The result of transient simulation for the power amplifier operating at center frequency of MHz is shown in Fig. 4. From Fig. 4 it is inferred that the product of voltage and current is minimum during the RF period for the power amplifier. S-parameter simulation is performed to find the S-parameters like forward voltage gain S 21, return loss S 11. Forward voltage gain is found to ensure that the amplifier is working at the designed frequency and bandwidth with maximum gain and Fig. 3 f T from ac simulation Table 2 Design specification of the power amplifier Parameters Power amplifier Center frequency MHz Bandwidth 25 MHz Power added efficiency(pae) >50% NF 6 db maximum SNR >60 SFDR >40 Power consumption <50 nw Table 3 Values of components in Class-E power amplifier Components R L C 1 C 2 L Values used in the circuit Ω 3.4 pf pf nh Fig. 4 Transient simulation of power amplifier (a) transient current from NMOS and (b)transient voltage from NMOS

4 SAMPATH & GUNAVATHI: CLASS-E POWER AMPLIFIER 147 low return loss. The forward voltage gain will be lower since the power amplifiers are not voltage amplifiers. The S-parameter results of Class-E power amplifier for center frequency for MHz are shown in Fig. 5. The S-parameters S 21 and S 11 are measured in db as db(s(2,1)) and db(s(1,1)).the S-parameter results in Fig. 5 show that the power amplifier has maximum gain (S 21 ) given by marker m 1 and minimum return loss (S 11 ) given by marker m 4 at MHz. Power amplifier provides a bandwidth of 25 MHz given by the difference between the -3 db frequencies specified by markers m 2 and m 3 in Fig. 5a at the designed center frequency. AC simulation is performed to find the noise figure and signal to noise ratio (SNR). The noise must be low at the designed frequency of operation for the power amplifier. Noise is measured in terms of noise figure (NF) as a function of frequency. Noise figure (NF) is a measure of degradation of the signal-tonoise ratio (SNR), caused by components in a radio frequency (RF) signal chain. Noise figure is calculated using Eq. (7) as: SNRi NF( db) = (7) SNR o Where, SNRi is SNR in db at input of the power amplifier and SNR o is SNR in db at the output of the power amplifier. SNR at the output will always be smaller than the SNR at the input, due to the fact that any circuit will only add to the noise, but never reduces the noise present in the system. The NF must be close to unity for any amplifier since the minimum value of NF is unity (theoretically) and a maximum of 6 db NF is acceptable in wireless systems. The NF and SNR for the power amplifier are shown in Fig. 6. Minimum NF of db as shown by marker m 5 in Fig. 6a and the maximum SNR of db as shown by marker m 6 in Fig. 6b for the power amplifier is obtained. Harmonic balance simulation is performed to find the power added efficiency (PAE), 1-dB compression values, spurious free dynamic range (SFDR) and third order intercept point (IP3), for the power amplifier. PAE, impedance and output power delivered by power amplifier are found using one tone load pull simulation for the fundamental frequency at load impedance. Power amplifier design requires device characterization for power, efficiency, and reflection coefficients as a function of input power level. Bias Fig. 5 S-parameters of Class-E PA at MHz Fig. 6 Figure and SNR of power amplifier

5 148 INDIAN J ENG. MATER. SCI., APRIL 2012 conditions, output circuit loss, load impedance, and gain are the major design considerations to achieve the required amplifier performance. The wireless systems are matched at input and output with characteristic impedance of 50 ohms. The goal of the output-matching network is to transform 50 ohms into this ideal impedance. There are two methods to find the ideal output impedance presented to the MOSFET of the amplifier. One is to perform a load-pull analysis and the other method is to design a matching network based on the physical model of the output device, load-line analysis. In this work Load-pull analysis is performed for the power amplifier designed at MHz. Load-pull analysis is performed by having various load impedances at the output of power amplifier and measuring the output power simultaneously. The input match is adjusted to ensure matched condition at the input of the amplifier. For each specific impedance value, output power is measured. The minimum available source power (P avs ) of 23 dbm in wireless systems for which the PA has to deliver maximum power to the load is given as input for the load-pull simulation and the bias voltages are given as V high =3.3 V and V low =2.75 V based on the 0.35 µm CMOS technology used. The characteristic impedance Z o is 50 ohms for the power amplifier operating at MHz. The load-pull simulation gives the power added efficiency (PAE) of an amplifier. The PAE 5 is calculated using Eq. (8) Out put power - Drive power PAE = (8) DC supply power The results for power amplifier designed at MHz provide a PAE of % and the power delivered to the load is dbm. 1-dB compression point is found using harmonic balance simulation to find the variation of the output with input as a function of RF power. 1-dB compression point is the point where the circuit gives an output power of 1 db less than the actual output power required. At the power level greater than 1 db gain compression point, the amplifier will generate very high harmonic distortion components. 1 db compression point is determined from the curve plotted for gain with respect to input RF power. The 1 db compression response of Class-E power amplifier for center frequency for MHz is shown in Fig dB compression is obtained at input RF power of 7 db for power amplifier operating at MHz from Fig. 7. SFDR is defined as the SNR when the power in each 3 rd order intermodulation product equals noise power at the output 4. The power amplifier performance is better if SFDR is high. For the power amplifier proposed SFDR is obtained as db as against the design specification of 40 db or more. IP3 is defined as the cross point of the power for the first order tones ω 1 and ω2, and the power for the third order tones, 2ω 1 - ω 2 and 2ω 2 - ω 1 on the load. IP3 is a measure to estimate the nonlinear products. The nonlinear products are called as intermodulation products (IP) or intermodulation distortion (IMD). IP should be low in the communication circuits, as it creates spurious emissions, which can create severe interference to other operations of the signal. IP will lead to cross modulation. Third order intercept point (IP3) at the input and output (IIP3 and OIP3 respectively) are found for the power amplifier at MHz. The IIP3 is dbm for the power amplifiers at MHz. The OIP3 on the lower and upper side of the center frequency represented as OIP_lower and OIP_upper are found. OIP_lower is dbm and OIP_upper is dbm for the Power amplifier at MHz. Linearization of Power Amplifiers To improve the linearity of the power amplifiers linearization techniques are used. The predistortion method of linearization is a low-cost solution that provides moderate performance improvement, and it has the additional advantages of low-power consumption and simple circuit configuration over other linearization methods. Fig. 7 1-dB compression characteristic of PA at MHz

6 SAMPATH & GUNAVATHI: CLASS-E POWER AMPLIFIER 149 Predistortion linearization involves constructing a predistorter which has the inverse non-linear characteristics of the power amplifier. Therefore, when the output of predistorter is passed through the power amplifier, the distortion components cancel and only the linear components remain. Analog predistorters can be constructed using square law or cubic law devices or any combination of these two. Typically, diodes arranged in various configurations are used to generate the second and third order distorters 5-7. An advantage of using diodes is that the ability of predistorter to operate over a wide bandwidth increases. Some of the disadvantages of using diode are the power and temperature dependence as well as the inaccuracy in controlling the constructed nonlinearity. This ultimately leads to a limitation on the amount of inter modulation distortion (IMD) reduction achievable. An analog predistorter generally has two paths 8. One carries the fundamental components of the desired signal with harmonics and the other path carries only the harmonics generated by the distortion generator. The objective of analog predistorter is the elimination of the fundamental component in the distortion generator path, thereby providing independent control of the distortion relative to the fundamental component. The two paths are timealigned and then subsequently combined before being presented to the power amplifier. The circuit of analog predistortion linearization is shown in Fig. 8. The analog predistortion using cubic law and square law is a three step process. Both the predistorters are based on usage of diodes in various configurations to generate the distortion. The diodes can be biased to better approximate the type of nonlinear behavior that is required. The predistorter consist of two paths; one to generate the nonlinearity and the other to pass the fundamental components. A 180 hybrid is used in the distortion generation path for eliminating the fundamental component. A complex gain adjuster is then used to control the amplitude and phase of the distortion relative to the fundamental component. The complex gain adjuster acts as a vector modulator. The input signal is split into two branches in the complex gain adjuster, each branch being individually controlled by in-phase (I) and quadrature (Q) inputs. The output is the sum of the two branches. The two branches of the vector modulator are in phase quadrature and the mixer elements are implemented using ideal multipliers. The voltage applied to the complex gain adjuster through alpha_i and alpha_q is varied between -2 V to +2 V for varying the magnitude. The steps in square law method of analog predistortion for linearization of PA are: (i) finding the square law predistorter dependence on power and bias voltage; (ii) optimization of square law predistorter and (iii) square law predistortion of the PA. In square law method, two diodes are arranged so that the even terms of an equivalent series expansion add together and the odd terms cancel so that the 2 nd order distortions can be reduced. The square law device can be realized with a couple of diodes in push-push configuration, fed with two 180- degree shifted inputs. To have a large operational frequency range a differential amplifier has been used to realize the input 180 degrees phase-shift. The square law device optimizes the bias voltage to reduce any third order nonlinearity. The impedance in the fourth port of the 180 hybrid is adjusted in order to eliminate the fundamental component at the output of the 180 hybrid. The circuit for square law predistortion is shown in Fig. 9. The steps in cubic law method of analog predistortion for linearization of PA are: (i) optimization of cubic law predistorter; (ii) find the power and frequency dependence of cubic law predistorter and (iii) cubic law predistortion of the PA. In Cubic law method two diodes 7 are arranged so that the odd terms of an equivalent series expansion Fig. 8 Circuit of analog predistortion linearization Fig. 9 Circuit for square law predistortion

7 150 INDIAN J ENG. MATER. SCI., APRIL 2012 add together and even terms cancel so that 3 rd order distortions can be reduced. The cubic law device can be also realized with a couple of diodes, but in a pushpull configuration and with no input phase-shift. The cubic law device consists of two anti-parallel diodes to create the cubic behavior is shown in Fig. 10. A hybrid is also used in this distorter to eliminate the fundamental component. Simulation Results of Linearization Linearization is performed for the power amplifier working at center frequency of MHz using square law and cubic law methods. In square law method the first step is to find the power in the harmonics at the output of the predistorter circuit and dependence on power and bias voltage. In the predistorter circuit 180 hybrid coupler is used to phase shift the signal by 180. The hybrid coupler has reference impedance of 50 ohms and loss 0 db. The dependence of power is measured in terms of carrier to inter modulation distortion (IMD) ratio in dbc. For the voltage of 0.7 V in forward bias for the diodes and available source power the C/IMD ratio is dbc for the power amplifier. In the second step of square law predistortion, gradient optimization is performed to suppress the fundamental frequency components and the 2 nd order intermodulation power in the upper and lower sidebands at the designed center frequency. The value of resistor and capacitor are R=2315 ohms C=1 µf. In the third step the power amplifier is connected with the predistorter as shown in Fig. 8. The linearization using square law method of analog predistortion suppresses the harmonics and thereby the linearity of the amplifier is improved. The C/IMD ratio is improved to dbc for the power amplifier after linearization. In cubic law optimization, there are three steps similar to square law method. First step is Fig. 10 Circuit for cubic law predistortion optimization of cubic law predistorter using linearizer. The circuit is optimized for resistance and capacitance values of R=106 ohms and C= µf Second step is finding the power and frequency dependence of cubic law predistorter and the third step is performing cubic law predistortion of the power amplifier. The predistorter is optimized using linearizer with gradient optimization for available source power of 23 dbm. In the predistorter circuit 180 hybrid coupler is used to phase shift the signal by 180. The hybrid coupler has reference impedance of 50 ohms and loss 0 db. There is no need for transformer as in square law predistorter. This linearizer uses anti-parallel diodes to generate third order IMD products. The resistor and capacitor are used to reduce the fundamental output component relative to the third order IMD products. The fundamental component is suppressed at the output of the predistorter and the carrier to inter modulation distortion (IMD) ratio C/IMD in dbc reduces with number of iterations of the optimization. C/IMD is measured as the power with respect to carrier power of the input signal in dbc. In the second step of predistortion, the variation of the signal C/IMD with respect to power and frequency are observed and the spectrum is 180 phase shifted. The C/IMD ratio variation observed with respect to frequency and power is very close with the expected variation of C/IMD ratio and the output spectrum from the predistorter is maximum at the desired center frequencies for the power amplifier. For the voltage of 0.7 V in forward bias for the diodes and available source power the C/IMD ratio is dbc for the power amplifier. The third step in analog predistortion using cubic law the predistorter is connected with the power amplifier along with complex gain adjuster circuit. The complex gain adjuster circuit behaves like a vector modulator and controls the amplitude and phase the signal. The signal is split into inphase and quadrature components by 90 hybrid and the components are multiplied by the control voltage and finally combined by splitter/combiner. The power splitter/combiner has an isolation of 100 db between the port 2 and port 3 of the combiner. The impedance at all the ports is 50 ohms. The combiner is selected such that the S-parameters are as follows: S 21 =1, S 31 =1, S 11 =0 and S 22 =0.

8 SAMPATH & GUNAVATHI: CLASS-E POWER AMPLIFIER 151 Table 4 Optimization coefficients and optimum time delay for MHz No. of iterations Inphase coefficients Quadrature coeficients Time delay (ns) Table 5 Output of analog predistortion for power amplifier Frequency Frequency (MHz) Square law Power (dbm) Cubic law Power (dbm) Output from step1(before optimization) Pass band Center frequency Stop band Output from step2(after optimization) Pass band Center frequency Stop band Output from step3 (after linearization) Pass band Center frequency Stop band Table 6 IP3 values and power consumption of power amplifier Parameters Before linearizati on After linearization using square law method After linearization using cubic law method IIP3 (dbm) OIP3 lower (dbm) OIP3 upper (dbm) Total power consumed by the circuit for simulation (nw) The optimum value of the coefficients for optimization for different iterations are given in Table 4 for power amplifier with MHz. The power in the harmonics at output of each stage in the square law predistortion linearization for the power amplifier is given in Table 5. The improvement in linearity of the power amplifier is given in terms of the reduction in power of the harmonics and increase in the value of IP3. The power in harmonics has been reduced by dbm at the center frequency, dbm at the pass band frequency and dbm at the stop band frequency for the power amplifier. The improvement in IP3 and power consumption after linearization using square law analog predistortion is given in Table 6. The simulation results of the cubic law predistrotion step 3 shows that the harmonics has been decreased when compared to the signal before predistortion. Also the third order C/IMD ratio in dbc (in db with respect to carrier) has increased to dbc for Power amplifier after linearization. The power in harmonics has been reduced by dbm at the center frequency, dbm at the pass band frequency and dbm at the stop band frequency for the power amplifier. Hence the linearity of the power amplifier is improved with analog predistortion methods. Conclusions Class-E power amplifier for center frequency of MHz is designed and its performance is studied. The Class-E amplifier designed gives a PAE of % at MHz. The power amplifier gives a PAE of above 70% when compared to the power amplifiers in the literature with PAE 64%. The PAE of class-ab power amplifier 9 with on-chip linearization is 20% only. A reconfigurable CMOS power amplifier 10 operating from 0.9 to 2.4 GHz for Wireless application provides a PAE of 42 to 57%. The noise figure of for MHz is obtained which is less than desirable value of noise figure of 3 for power amplifiers in wireless systems. The SNR is and SFDR is db for power amplifier at MHz. The power amplifier provides a very good SNR and SFDR. The linearity of the power amplifier designed for MHz is improved by square law and cubic law analog predistortion methods by suppressing the power in the harmonics and increasing the IP3 and C/IMD ratio. In the square law method the second order harmonics are suppressed and thereby the linearity of the amplifiers is improved. In the cubic law predistortion the third order and fifth order harmonics are reduced to increase the signal strength at the desired frequencies and the linearity is improved. The power consumption of the power amplifier circuit is reduced after improving for linearity.

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