Power Management for Cellular Devices overview and opportunities

Transcription

1 Management for Cellular Devices overview and opportunities Thomas Olsson Ericsson Research Lund Mobile data evolution Functionality & capabilities GSM (2G) Speech 2.5G GPRS up to 115 kbps Packet Switched 3G EDGE up to 384 kbps 3.5G UMTS W-CDMA up to 2 Mbps HSPA HSUPA up to 14 Mbps 4G HSPA+ up to 42 Mbps LTE > 1 Mbps GPRS = Generic Packet Service EDGE = Enhanced Datarates for GSM Evolution UMTS = Universal Mobile Telecommunication System HSPA = High-Speed Packet Access LTE = Long-Term Evolution Page 3 Challenges - multiple standards makes design more complex management basics management design approach using dataflow management system perspective partitioning interfaces DVFS/GALS analog part regulator (DC/DC) Towards 5 billion connected Increasing number of standards to support in mobile Need efficient computation platform that can be reconfigured by software (Software Defined ) ZigBee NFC / RFID Bluetooth GPS GSM, GPRS, EDGE, 3G, HSPA, LTE, LTE-A DVB-H WLAN Page 2 Page SDR Digital baseband LTE-challenge and opportunity SDR for digital baseband? Highly reconfigurable/programmable modem. Can support standars not yet fully defined by standardization. Increase lifetime of product and architecture due to high degree of reconfigurability Performance scalability Must scale efficiently from to full bitrate Data rates for LTE / LTE advanced increases faster than the technology evolution A trend towards higher power consumption! WCDMA HSDPA 22 HSPA HSPA evolution LTE LTE-Advanced Multicore architecture Architectures of today are already multicore, but with more or less specialized cores. In the long run too costly to support specialized subsystems. However, higher data rata rates gives possibility for energy efficient scheduling Energy per bit transmitted can be reduced significantly! [%] TX+PA (Analog BB+ DAC+PA) 1 RX (Analog BB+ADC) 67 BB Page 5 33 Baseline BB Sleep (DRX) period (ms) Page 7 Some challenges ahead Significant peak rate increase Cell bandwidths up to ~1MHz needed 2 MHz 1 MHz Fragmented spectrum situation Carrier aggregation 2MHz 2MHz 2MHz 2MHz 2MHz 2MHz 2MHz 2MHz 2MHz Aggregated bandwidth of 1 MHz Aggregated bandwidth of 8 MHz How to handle these data-rates in portable Battery, heat, cost etc Graceful scaling Efficiency must be kept for lower bit-rates The system should be just good enough at any given time management basics management design approach using dataflow management system perspective partitioning interfaces DVFS/GALS analog part regulator (DC/DC) Towards 5 billion connected Page 6 Page 8 3 4

2 Acheiving energy balance management for portable - objectives One of the most difficult tasks today for design of hand-held Camera, big screen MP3, Video, Gaming, 3D graphics Blutooth, WiFi, DVB-H GSM, 3G, HSPA, LTE Extend battery life Not acceptable to recharge more than once/day for normal use Limit size Cope with smaller battery No cooling fan or heat sink Control heat Keep the device from shutting down due to overheat rapit aging due to electromigration feel unconfortable to have in hand or pocket Page 9 Page 11 Acheiving energy balance Fundamentals and commonly used techniques for power management at circuit level One of the most difficult tasks for design of hand-held Finding this balance at the right time to a competitive price Camera, big screen MP3, Video, Gaming, 3D graphics Blutooth, WiFi, DVB-H GSM, 3G, HSPA, LTE Better batteries Improved technology management Energy scavanging in digital domain: P = αc f V 2 + I stat V α switch probability C switched capacitance f clock frequency V voltage I stat leakage current Clock gating Only clock digital part when processing data gating switches to disconnect unused parts from power rails Scaling clock frequency/ voltage For entire chip or for each subsystem Design choices Parallel computing, memory architecture,... in analog domain: P ~ DR BW T DR dynamic range BW signal bandwidth T duty cycle Scaling voltage, bias current Reconfigure filters, matching,... Page 1 Page Design approach - management using Dataflow design management basics management design approach using dataflow management system perspective partitioning interfaces DVFS/GALS analog part regulator (DC/DC) Towards 5 billion connected Exploit parallelism to increase performance with minor area increase Performance may be traded for power Simplified GALS approach with data driven power control GALS = Globally Asynchronous Locally Synchronous Page 13 Page 15 Design approach - management using Dataflow design Master thesis at ericsson research (Hemanth Prabhu, Sherine Thomas) OFDM Channel estimator for LTE, WLAN and DVB-H Original RTL developed as Master s Thesis at ULUND Use high-level dataflow representation in CAL to optimize and the generate RTL management basics management design approach using dataflow management system perspective partitioning interfaces DVFS/GALS analog part regulator (DC/DC) Towards 5 billion connected Page 14 CAL dataflow Page

3 management, system perspective Interface circuits regulator Memories, subchips consuming switching large capacitance at high datarates clock recovery and synchronization Encoder Parallel to serial Serial to parallel Decoder Interface DBB regulator Example of typical relative power PA power depends on transmitted power (from small to dominating) Digital PA Regulator Interface DBB Page 17 Page 19 System partitioning and architecture Partition into analog/digital or modem/application or? Number of subchips, if more than 1, why? Complexity Interference Technology Flexibility Memory often 5-6% of design possibly up to 9% of digital part Reducing memory access Enabling memory retention switches to reduce static power Design/Runtime DVFS (Dynamic Voltage and Frequency Scaling) Grouping the components for DVFS Voltage islands with similar requirements on Larger number of voltage islands give higher flexibility but also higher overhead Also applied on analog and interface components Supply, bias regulator regulator Interface DBB Interface DBB Page 18 Page Dual a good DVFS compromise Signal level converter Dual with local power switches at each subsystem Supply voltage levels are optimized for lowest possible power at system level Each subsystem select low if possible, otherwise high 2 voltages near optimum for many usecases Relative power consumption Block(1) Select(1) Test(1) Controller Select(n) Test(n) DC/DC Block(n) DC/DC In In Vhigh Vlow Out Vlow Vhigh Feed-back to restore voltage. Needed when going from low to high voltage domain Out Page 21 Number of voltages Page 23 Ex: design using GALS with local oscillators and dual GALS = Globally Asynchronous Locally Synchronous E. Beigne, F. Clermidy, S. Miermont, P. Vivet, Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC, in Proceedings of the 2nd IEEE International Symposium on Networks-on-Chip (NOCS 8), pp , april 28. Implemented in ST 65nm Use local ring oscillators with digital frequency control Pausable clocks Level converters for multiple voltage domains Need to convert signal levels between voltage domains Ex: ~1 subsystems ~2 bus bits to each subsystem Problem: too many level converters area, delay, power Possible solution: use scheduling to transfer data without level shifters How should this be managed without damaging system performance? Use 2 voltage levels for each GALS block Switch between high and low voltage to get enough performance A B Data burst from A to D Data burst from D to A C D Bus activity Supply A Supply D t t 1 time Page 22 Page

4 Control analog components to trade perfomance for power Efficiency ~5-9% Buck converter consumption in the radio can be decreased by adaptation of RX/TX based on knowledge of current radio conditions ADC c Digital Capacitive switching converters LNA Hard to control Vout No inductor ADC PA LDO (Low DropOut) regulator Linear voltage regulator to stabilize Not used for power saving based on parameters detected in baseband Regulator PWM + filter Easy to control Vout using duty factor Need external inductor Adjusting bias bandwidth matching Filters... regulator - DC/DC converters Adaptive standard interference level signal quality... regulator DBB Interface Buck converter Capacitive switching converter Page 25 Page 27 Scheduler - Sensing mechanisms Runtime - Scheduling for low power in DC/DC converters Sensing Decrease max current DC/DC Reduce size Increase efficiency voltage/current, clock frequency, bias currents, bandwidth, #bits, #iterations,... System level simulations for evaluation 9 Current consumption at regulator 1 Efficiency η (%) modulation, temperature, bitrate, error rate,... Controlling/scheduling DC/DC (2) Load Current(mA) Imax DBB Interface DC/DC (1) 8 Time Page 26 Page Runtime - Scheduling for low power in DC/DC converters Current consumption at Towards 5 Billion Connected Fixed broadband Mobile Today Decrease max current 1 9 Efficiency η (%) DC/DC Reduce size Increase efficiency 14 DC/DC (1) DC/DC (2) 8 4 Billion Subscribers 7 5 Million Households 6 5 Tomorrow Full Service Broadband 3 Load Current(mA) Rescheduling to reduce variations 5 Billion Devices Imax Source: Ericsson Time Page 29 Page 31 What will be connected? management basics management design approach using dataflow management system perspective THINGS 5 B PEOPLE 5. B Digital Society Sustainable World partitioning interfaces DVFS/GALS analog part regulator (DC/DC) Personal Mobile Towards 5 billion connected Global Connectivity PLACES ~.5 B Source: Ericsson Page 3 Page

5 Machine to Machine type connections Large variation in performance requirements Many will be sensor-like with very limited power Idle for long times (hours/days/weeks..?) Able to transmit/receive very short burst of data, possibly at high peak rate A huge opportunity for energy scavanging techniqes together with advanced power management Ultra low voltage (sub Vt?) management basics management design approach using dataflow management system perspective partitioning interfaces DVFS/GALS analog part regulator (DC/DC) Towards 5 billion connected Page 33 Page 35 Energy scavanging Conclusions managemant has interesting topics for research Photoelectric Co-design of power domains and SW scheduling Light to power e.g. Solar cells The ability to re-schedule jobs heavily affects choise of optimum power architecture Thermelectric/Peltier elements Heat to power May also be used for cooling Piezoelectric Sound to power Electrodynamic Movement to power System level simulations including DVFS strategies Dataflow design Digital control of analog components Ensure that no analog components overperform (to the cost of eccess power) Combine with scheduling for global power management Algorithms for sensing and control Interfaces Chip-to chip and internal Emerging market for mobile phones High maximum bitrate at acceptable power level should scale with bitrate down to. Disruptive technologies Energy scavanging? Ultra low voltage design? source Idtechex Page 34 Page