HARDWARE VLSI CHIP DESIGN IMPLEMENTATION FOR SOFT-OUTPUT MINIMUM WEIGHT DECODER

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1 HARDWARE VLSI CHIP DESIGN IMPLEMENTATION FOR SOFT-OUTPUT MINIMUM WEIGHT DECODER ; ' W. M. El-Medany*, C. G. Harrison*, P. G. Farrello, and C. J. Hardy* *Manchester School of Engineering Manchester University Oxford Road, Manchester M13 9PL, U.K. Tel: Fax: mbgedwme@afs.mcc.ac.uk OCommunication Research Centre Lancaster University, Lancaster LA1 4YR, U.K. ABSTRACT A decoder for soft-decision decoding is much more complex than the corresponding hard-decision decoder, however it has a significant performance advantage over a hard-decision decoder. Minimum Weight Decoding (MWD) is a modified error trapping technique for cyclic block codes. In this paper a hardware VLSI chip design implementation is described which implements a soft-output minimum weight decoder for cyclic linear block codes. The design implemented and presented here is for the Hamming(7,4,3) code. 1. INTRODUCTION The output of the demodulator in digital communication systems has to be quantized into one of a finite number, Q, of discrete output symbols. When binary coding is used the modulator has binary input (M = 2) and the demodulator has binary output (Q = 2). In this case the decoder has only binary inputs, and the demodulator is said to make hard decisions. Since the decoder operates on the hard decisions made by the demodulator the decoding in that case is called hard-decision decoding [8, 21. If the demodulator output is quantized to more than two levels (Q > 2), then the demodulator feeds the decoder with more information than is provided in the hard-decision case, and the demodulator is said to make soft-decision decoding [I, 51. The decoder in this case must accept a multilevel input signal. Although this makes the decoder more difficult to implement soft-decision decoding offers much improved performance compared with hard-decision decoding. 2. SOFT-DECISION Minimum Weight Decoding Algorithm Minimum Weight Decoding (MWD) is a simple decoding algorithm for cyclic linear block codes, which gives a performance similar to that of Maximum Likelihood Decoding (MLD) and low complexity compared with other known soft-decision decoding techniques. In this paper a VLSI chip design is described for a soft-decision minimum weight decoder [3, 41, which gives a soft output decoding. The decoder has been designed for the Harnming(7,4,3) code. The decoder can detect and correct any soft error pattern with soft Hamming weight less than or equal to the the soft error correcting capability of the code. To use the extra information given by the quantization of the channel output a soft distance is defined. The soft distance [6], d,(v, U), between two vectors, Vand U, is given by:

2 The minimum soft distance of a code, d,, is calculated in terms of the hard distance and quantization levels as: d, = d(q - 1) (2) Similarly the soft-decision error correcting capability t, [l] is defined as: The soft weight of a word U is: As an example consider the soft-decision Hamming (7,4) code, with generator polynomial G, (x) = 7077 and transmitted codeword T,(x) = , where n = 7 is the code length, k = 4 is the number of information bits, and Q = 8 is the quantization levels. In this case the soft minimum Hamming distance of the code is d, = d(q - 1) = 3(8-1) = 21, and the soft error correcting capability of the code is t, = 1 1- = = 10. If there are two errors introduced in the second and fourth digits with the error pattern P,(x) = , this gives a received word R,(x) = Then: (Transmitted Codeword T,(x)) (Error Pattern P,(x)) (Received Word R,(x)) (Generator Polynomial Gs (x)) I (Error Pattern P,(x)) (W,=9) The Corrected Codeword = Error Pattern + Soft Decision Received Word = = Notice that the minimum soft distance W,(,i,) (t, = 10). = 9 which is less than the error correcting capability 3. VLSI HARDWARE DESIGN The hardware of the design mainly consists of three units as shown in figure 1. The first unit is called the SSTOP (Soft Serial TO Parallel) converter, which converts the serial stream of bits input into Parallel data soft codewords. The second unit is the SMWCEPD (Soft Minimum Weight Calculator and Error Pattern Detector). This unit receives the soft codeword and the soft generator polynomial, and divides the codeword by the generator polynomial by doing a series of additions (Modulo-2 addition) and shifting until the soft minimum weight W, becomes less than or equal to the soft error correcting capability t,.

3 t,. The resultant pattern from this process is the soft error-pattern. The third unit is the EC (Error Corrector), which has two inputs, the soft error-pattern detected from the second unit and the received soft codeword. The function of this unit is the to add them together using (XOR) to get the introduced error corrected. B D -- SMWCED EC STOP rart ~x-o-oy~o~~ gx-in (ZEO) reset - dk data-out (n.0) ewjn (2E0) - dk cormi-w(2'1~). ex-in d-ready en ready emme dsta-in em>rnp~o) e~r>rn(zro) Clk d-emblc cw~d(27:o) e-w-ready----ll> 0 Figure 1: Block Diagram of The Hardware Design Aeset Figure 2: Simulation Result of Serial To Parallel Converter Figures 2, 3 and 4 show the simulation results of the three units for the previous example.

4 Figure 3: Simulation Result of Soft Minimum Weight Calculator and Error Detector keset ' lclk t t Figure 4: Simulation Result of Error Corrector

5 4. CONCLUSIONS An implementation of a soft output minimum weight decoder has been presented for the Hamming(7,4) code in VLSI. A VHDL [9] source code program has been written to implement the design in hardware. The design has been tested, simulated, and synthesized using Mentor Graphics design tools [7] and targets an FPGA(Fie1d Programmable Gate Array). The simulation result shows that the decoder can detect and correct any soft-error, if the soft weight W, is less than or equal to the soft error correcting capability t, of the code. The decoder achieved a bit rate of 7Mbitlsec using a Xilinx XC4000 series FPGA. i ' References [l] J. Eiguren. Soft-Decision Decoding Algorithms for Linear Block Codes. PhD thesis, Manchester University, School of Engineering, Division of Electrical Engineering, [2] W. M. El-Medany, C. G. Harrison, and P. G. Farrell. VLSI Chip Design Implementation for Minimum Weight Decoder. CSDSP'98, 2: , April [3] W. M. El-Medany, C. G. Harrison, and P. G. Farrell. VLSI Hardware Implementation for Soft-Decision Minimum Weight Decoder. AISCON'98, pages , October [4] W. M. El-Medany, C. G. Harrison, P. G. Farrell, and C. J. Hardy. Modified Soft-Decision Minimum Weight Decoder: A VLSI Chip Design Implementation. DSPCS'99, pages 44-48, February [5] P. G. Farrell, V. C. Dunwoody, N. Doganis, and F. Taleb. Soft-Decision Decoding: A Review of Basic Algorithms and Novel Techniques. 3rd Bangor Communications Symposium, [6] P. G. Farrell, M. Rice, and F. Taldb. Division Algorithms For Hard And Soft Decision Decoders. International Conference on Digital Signal Procissing, September [7] Mentor Graphics. AutoLogic VHDL Synthesis Guide MentorGraphics Co., New York, [8] I. Martin, B. Honary, and P. G. Farrell. Modified Minimum Weight Decoding for Reed Solomon Codes. Electronics Letters, 31: , [9] D. L. Perry and L. J. Douglas. VHDL. McGraw-Hill, New York, 1994.