ORTHOGONALLY MODULATED CMOS READOUT INTEGRATED CIRCUIT FOR IMAGING APPLICATIONS

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1 ORTHOGONALLY MODULATED CMOS READOUT INTEGRATED CIRCUIT FOR IMAGING APPLICATIONS Jorge A. García Visiting Assistant Professor Electrical and Computer Engineering Department University of Delaware December 13, 2004 Research work supported by the Army Research Laboratory

2 Report Documentation Page Form Approved OMB No Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. 1. REPORT DATE 13 DEC REPORT TYPE 3. DATES COVERED to TITLE AND SUBTITLE Orthogonally Modulated CMOS Readout Integrated Circuit for Imaging Applications 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S) 5d. PROJECT NUMBER 5e. TASK NUMBER 5f. WORK UNIT NUMBER 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) University of Delaware,Department of Electrical and Computer Engineering,Newark,DE, PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR S ACRONYM(S) 12. DISTRIBUTION/AVAILABILITY STATEMENT Approved for public release; distribution unlimited 13. SUPPLEMENTARY NOTES 14. ABSTRACT 11. SPONSOR/MONITOR S REPORT NUMBER(S) 15. SUBJECT TERMS 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT a. REPORT unclassified b. ABSTRACT unclassified c. THIS PAGE unclassified Same as Report (SAR) 18. NUMBER OF PAGES 48 19a. NAME OF RESPONSIBLE PERSON Standard Form 298 (Rev. 8-98) Prescribed by ANSI Std Z39-18

3 ORTHOGONALLY MODULATED CMOS READOUT INTEGRATED CIRCUIT FOR IMAGING APPLICATIONS Introduction and motivation Contribution Phase I: Proof of principle Orthogonal encoding readout system description Prototype system design and verification Conclusions Contribution Phase II: Improving the system performance Readout cell improvements Transimpedance amplifier integration Conclusion and brainstorm on further improvements

4 Read Out Integrated Circuit ROIC ROIC may include: Amplifier electronics Control signal generators Analog-Digital Conversion On-chip Digital Signal Processing

5 Distance information: a time of flight measurement

6 FM/CW LADAR system LASER FM chirp generator Trigger Circuit Self-mixing detector array ROIC N samples 4-D data set ( x, y, n, intensity ) FFT along n N/2 range cells 4-D image ( x, y, z, reflectance ) Motivation: Readout Integrated Circuit ROIC for active/passive imaging systems

7 ORTHOGONALLY MODULATED CMOS READOUT INTEGRATED CIRCUIT FOR IMAGING APPLICATIONS Introduction and motivation Contribution Phase I: Proof of principle Orthogonal encoding readout system description Prototype system design and verification Conclusions Contribution Phase II: Improving the system performance Readout cell improvements Transimpedance amplifier integration Conclusion and brainstorm on further improvements

ROIC conventional architecture Time Domain Multiple Access Control signals access every readout cell in a time scheduled manner, sampling the voltage signals and transferring them to the

8 ROIC conventional architecture Time Domain Multiple Access Control signals access every readout cell in a time scheduled manner, sampling the voltage signals and transferring them to the readout bus. It requires faster electronics for bigger photodetector arrays. Each readout cell must be capable of storing the required charge, which becomes a problem for big array sizes (1024x1024).

9 Read Out Cell Architectures V B _ + V out From Direct Injection to Capacitive TransImpedance Amplifier

10 ROIC proposed architecture Orthogonal encoding ROIC Each column is multiplied by a unique code, and the multiplied signals are summed in the row common bus Codes are chosen to minimize cross talk Current-to-voltage amplifier per row Multiplexer scheme to generate single data stream

11 Orthogonal Encoding ROIC First Phase Design Tasks Test system with four readout cells and a discrete component I-V amplifier Design of the Active Readout Cell To design and fabricate a test chip for a proof of principle of the active 2D readout technique.

12 Active Readout Cell: Design Requirements Readout cell for orthogonal encoding Multiplies the input current by the code Provides detector virtual ground Couples the detector impedance to the bus Reduces charge injection noise

13 Active Readout Cell: Implementation Differential code multiplier Readout cell for orthogonal encoding Differential output current + + i () t = i () t c() t + n + i () t c() t + n, o in c in c + i () t = i () t c() t + n + i () t c() t + n, o in c in c + + i () t = i () t i () t = [ i () t i ()][() t c t c()], t od o o in in

14 Active Readout Cell Current Locked Loop ILL Characteristics Detector virtual ground v gg γ gg = =, with γ = v g g g g 1 γ g g g s1 low freq Low input impedance Z in low freq. 1 = (1 γ ) g 1

15 Active Readout Cell ILL Replica Current Locked Loop (ILL) Detector virtual ground Low input impedance Differential code multiplier Signal-code modulation Balanced charge injection Current amplifier Current gain High output impedance Charge cancellation

16 Test chip implementation 4 instances of active readout cell 4 instances of cell with input modulator only Test chip with cell prototypes

Prototype system testing Test chip with cell prototypes ROIC electrical verification set up Power Conditioning Amps Code inputs Amps Electrical inputs DUT Custom printed circuit board for

17 Prototype system testing Test chip with cell prototypes ROIC electrical verification set up Power Conditioning Amps Code inputs Amps Electrical inputs DUT Custom printed circuit board for electro-optical testing Code signals generated and conditioned externally Voltage sources + Resistors emulate electrical current inputs High-gain off-chip transimpedance amplifiers on the pcb Data is acquired and processed in the computer

Verification Results i in1 i in2 c1 c2 ---- ---- c1 c2 Common Bus To

18 Verification Results i in1 i in2 c1 c c1 c2 Common Bus To i-v amplifier Proof of principle system with 2 encoding cells Test results

19 Prototyping phase conclusion Satisfactory results with the 2 encoding cells experiment confirm validity of the orthogonal encoding scheme for readout circuits Applicability extends to passive imaging systems Depending on the system conditions, the orthogonal encoding architecture is advantageous with respect to the conventional time-multiplexed scheme Integrating the transimpedance amplifiers with improved versions of readout cells should enhance noise performance of the overall system

20 ORTHOGONALLY MODULATED CMOS READOUT INTEGRATED CIRCUIT FOR IMAGING APPLICATIONS Introduction and motivation Contribution Phase I: Proof of principle Orthogonal encoding readout system description Prototype system design and verification Conclusions Contribution Phase II: Improving the system performance Readout cell improvements Transimpedance amplifier integration Conclusion and brainstorm on further improvements

21 Active Readout Cell Improvements ILL current gain and noise performance VDD Q3 1:1 Q4 1:m Q5 i = 4kTγ g 2 Q3 3 2 g 5 iout = 4kTγg5 1+ = 4kTγg3m 1+ m g3 ( ) Q1 Q2 Q6 Input referred noise IBIAS i 2 ieq 2 iout = = 2 m ( 1+ m) 4 ktγ g3. m VSS Iout Minimize g 3 Iin Maximize current gain m

22 Active Readout Cell Improvements Fully differential architecture vdd Q3 Q4 1:m Q5 Q24 Q18 Q21 1:m Q11 Q17 Q1 Q2 Q6 Q23 Q19 Q20 Q12 Q22 Additional current mirror for complementary output IBIASp VSS Q7 Ioutp IBIASn VSS Ioutn Q10 Improved charge injection cancellation and offset Q8 Q13 Q14 Q9 Q16 Q15 Noise from cascode mirrors is minimized vss Iinp Iinn

23 Active Readout Cell Improvements Input impedance engineering From small-signal model, solve for Z in Z in ( )( ( )) Vs () s 1 g + sc g + s C + C g g = = Is() s scin g scgs g scp g scn 3 P 2 gs1 N 1 4 // ( 1+ 1)( 3+ )( 2 + ) Input impedance without C in Small-signal model 100k 40k First pole p1 Third pole p3 20k ILL input impedance / Ohm 10k 4k 2k Second zero z2 Second pole p2 1k 400 First zero z k 10k 100k 1M 10M 100M 1G 10G 50G Frequency / Hertz

24 Active Readout Cell Improvements Input impedance engineering (cont d) Input impedance with C in Impedance / Ohm 4M 2M 1M 400k 200k 100k 40k Input pad capacitance ILL input impedance Total input impedance 20k 10k 4k 2k 1k k 10k 100k 1M 10M 100M 1G 10G 50G ILL pole-zero analysis z z 1 2 p p p K C g C g C g = 2 C ( C + C ) g = C z gs1 3 N 3 P 2 P gs1 N K C g C g C g = 2 C ( C + C ) z gs1 3 N 3 P 2 3 P g = C 2 N g = C 1 gs1 P gs1 N Frequency / Hertz K z = C g + 2 C ( C g + C (2 gg gg)) + C g + 2 C C (2 gg gg) + C g gs1 3 gs1 N 3 P N 3 N P P 2 C P controls p 1 and z 1, but also moves z 2 to the left C N moves p 2 close to z 2, canceling its effect p 3 determines overall gain-bandwidth

25 Active Readout Cell Improvements Input impedance engineering (cont d) VDD Compensated input impedance with C in Q3 1:1 Q4 400k Compensated ILL input impedance 270f Ccompp 200k 100k Input pad capacitance Cin=500fF The z2/p2 doublet has vanished Q1 Q2 70f Ccompn 40k Ohm 20k 10k 500f Cin 4k 2k Total input impedance 1k 1k 2k 4k 10k 20k 40k 100k200k400k 1M 2M 4M 10M 20M 40M 100M 400M 1G 2G 4G 10G Iin Frequency / Hertz C P = 270fF and C N = 70fF compensate the input impedance for C in = 500fF

26 Improved Active Readout Cell Performance Frequency response Transient response Ioutp, 3.8nA peak I-diff-out / A Ioutp / na Ioutn / na Time/µSecs Ioutn, 3.8nA peak 5µSecs/div Designed for 500kHz code bandwidth (16 cells) Current gain of 3.8A/A

27 Improved Active Readout Cell Performance Virtual ground regulation Noise performance 3p Total output noise density 2p p Noise from Q3 and Q8 V/rtHz f / mv Y1 1p Noise from Q25 and Q30-3 Input Noise / A/rtHz 500f Input referred noise density Time/µSecs Virtual ground regulation@-2.82mv 5µSecs/div 400 1k 2k 4k 10k 20k 40k 100k 200k 400k 1M Frequency / Hertz Between -3.1mV and -2.6mV Input referred noise 400fA/rtHz

28 Transimpedance amplifier implementation Capacitive TIA (CTIA) CTIA with correlated double sampling (cds) RST switch injects charge and produces sampling (kt/c) noise CDS structure removes sampling noise SH capacitor produces voltage divider

29 CTIA system-level implementation Dynamics of CTIA system with cds Control signals OTA output cds output System output

30 CTIA system-level implementation Advantages of fully differential CTIA system single-ended outputs still exhibit pedestal error Vop, Von / mv differential output effectively cancels the pedestal error Vout / mv Time/µSecs 200nSecs/div Fully differential CTIA system Transient response of Single-ended vs. Differential output

31 CTIA system-level implementation External OTA compensation and sizing of switches and capacitors OTA External OTA compensation Input stabilization switches C CDS = 5pF, C SH = 1pF, C comp =3pF, C int = 50fF Switches designed for worst-case scenario R SW ~1kΩ

32 OTA circuit-level implementation 2-stage Miller compensated OTA, design requirements VDD Design requirements Q10 Q3 Q4 Q8 Votan VBIASn Q9 Ccn Vin Q2 vd2 VBIASp vx Q6 VSS vd1 Q1 Vip Ccp Q7 Votap Gm > 250mSie a vo (2% settling accuracy) > 40k Input referred noise < 5nV/rtHz Dominant pole and non-dominant pole more than three decades apart Output common-mode < 10mV CMRR > 60dB Input differential capacitance not to exceed 15pF Output swing of 2.4Vpk-pk Dual power supplies of ±2.5V Best effort on power consumption and layout area

33 OTA design methodology

34 OTA design methodology First and second stage design strategy VDD VBIAS Q4 W=w p L=lp M=mp Q5 W=w p L=lp M=mp 20u I1 1u C1 Q3 W=w p L=lp M=mp vout vout Transistor models from vendor are used to optimize the design of a single stage of amplification with active loading Q2 W=w n L=ln M=mn 1u C2 vin AC 1 0 V3 1 E1 VBIAS Q1 W=w n L=ln M=mn 100f C3 Bias conditions are replicated, and noise from biasing strategy is properly filtered out VSS Circuit for design of amplification stage Design results are back-annotated in work sheet

35 OTA design methodology Common-Mode amplifier design vdd ibias Q7 W=10.15u L=0.7u Q6 W=10.15u L=2.1u M=2 Q14 W=10.15u L=1.925u M=8 Q22 W=10.15u L=2.1u Q20 W=11.55u L=1.05u ina Q21 W=10.15u L=2.1u Q10 W=10.15u L=1.925u M=8 Q19 W=10.15u L=0.7u M=8 Q13 W=5u L=5u M=4 outc Q16 W=10.15u L=2.1u M=2 cura taila Q2 W=5u L=5u M=4 GND Q5 W=10.15u L=1.925u M=8 Q18 W=10.15u L=0.7u M=8 Q4 W=5u L=5u M=4 outg Q1 W=10.15u L=2.1u M=2 curb tailb Q3 W=5u L=5u M=4 CSn CSp cascp inb Q12 W=5u L=5u Q8 W=10.15u L=0.7u vdd Q11 W=5u L=5u imir Q9 W=10.15u L=0.7u iout Q13 and Q3 compute common-mode voltage from the OTA output and compare it to the desired value (GND) The amplifier produces a current output that regulates the common-mode voltage in the differential amplifier vss Common-mode amplifier circuit

36 OTA design methodology Final schematic for differential OTA W=6.3u L=4.025u Q10 M=16 100u I1 W=6.3u L=4.025u Q4 M=16 W=6.3u L=4.025u Q3 M=16 VG3 VDD W=6.3u L=4.025u Q11 M=16 vd2 von vop W=5.075u L=5.075u Q9 M=16 W=5.075u L=5.075u Q5 M=16 VDD vin W=12.43u L=2.975u Q1 M=16 W=12.43u L=2.975u Q2 M=16 vip VSS W=5.075u L=5.075u Q6 M=16 W=5.075u L=5.075u Q7 M=16 vd1 VG3 VG7 140f Ccp 140f Ccn W=5.075u L=5.075u Q6A M=16 W=5.075u L=5.075u Q12 M=16 W=6.3u L=4.025u Q8 M=16

37 OTA Performance Open-loop gain Frequency response Output voltage swing k k 100k 40k Total voltage gain Dominant k 10k 4k 30 2k 1k First stage gain Non-dominant 8.25MHz k Large-signal gain Avo Vod, Vd1 / V Small-signal gain avo m 200m k 2k 4k 10k 20k 40k 100k200k400k 1M 2M 4M 10M 20M 40M 100M 400M 1G 2G 4G 10G :vod/v 1V/div Frequency / Hertz Open-loop gain exceeds 40,000 for the operation range (2.4Vpk-pk) Dominant and non-dominant pole about three decade apart

38 OTA Performance 100k Frequency response with external compensation Dominant 1.66kHz Input differential capacitance G G 40k 20k p 10k 10p 4k 2k 1k Miller effect on the input Cgs decreases as the gain lowers p vod / V with switch equivalent resistor of 100 Ohm Cid / F p m 200m 100m 40m 20m k 2k 4k 10k 20k 40k 100k 400k 1M 2M 4M 10M20M40M 100M 400M 1G 2G 4G 10G20G40G 100G Frequency / Hertz for unitary feedback, the phase margin is close to 80 degrees with switch equivalent resistor of 500 Ohm External compensation of 3pF yields phase margin of about 80 degrees Compensation switch optimally sized for zero-nulling 2p 1p k 10k 100k 1M 10M 100M 1G 10G 100G 1T 5T Frequency / Hertz Cin ~ 12pF at low frequencies Decays for high frequencies because of absence of Miller effect p

39 OTA Performance Transient response with external compensation Input referred noise density 30 single-ended outputs still exhibit pedestal error 10n 20 Vop, Von / mv n differential output effectively cancels the pedestal error Input Noise / V/rtHz 2n Low frequency input referred noise power density Input referred noise at this requencies is irrelevant 40 1n Vout / mv p 0 Time/µSecs nSecs/div External compensation of 3pF effectively reduces differential transient ringing CMFB amplifier is also compensated (1pF) to reduce common-mode voltage transient ringing 1k 2k 4k 10k 20k 40k 100k 200k 400k 1M 2M 4M 10M 20M 40M 100M200M400M 1G 2G 4G 10G Frequency / Hertz Low frequency input referred noise around 5nV/rtHz High frequency noise density is not relevant in this case

40 Second generation ROIC Four 1x16 arrays + Fully differential CTIA

Readout cell physical design Ioutp IBIAS wn=2.975u, ln=2.1u wp=1.4u, lp=4.025u wn1=3.3u, ln1=4.025u wn2=4.9u, ln2=4u wp1=3.3u, lp1=4.025u ws=1.8u, ls=1.05u, ms=1 70f C4 70f C3 W=1.575u L=1.

41 Readout cell physical design Ioutp IBIAS wn=2.975u, ln=2.1u wp=1.4u, lp=4.025u wn1=3.3u, ln1=4.025u wn2=4.9u, ln2=4u wp1=3.3u, lp1=4.025u ws=1.8u, ls=1.05u, ms=1 70f C4 70f C3 W=1.575u L=1.05u Q10 W=1.575u L=1.05u M=5 Q12 W=1.225u L=2.1u M=5 Q14 W=1.225u L=2.1u Q15 wn1 ln1 Q16 wn1 ln1 Q13 wn1 ln1 Q11 wn1 ln1 Q9 wp1 lp1 Q34 wp1 lp1 Q26 wp lp Q25 M=4 500f C2 270f C1 wp lp Q4 VDD wn ln Q2 wn Ln Q1 wp lp Q3 VSS wp lp Q8 wn ln Q7 wn ln Q6 VDD wp lp Q5 270f C6 wp lp Q24 M=4 wp lp Q30 M=4 wn2 ln2 Q17 wn2 ln2 Q18 wn2 ln2 Q19 wn2 ln2 Q20 wp1 lp1 Q21 wp1 lp1 Q23 ws ls Ms Q31 ws ls Ms Q29 ws ls Ms Q28 ws ls Ms Q27 code codeb code VSS 500f C5 W=1.225u L=2.1u Q33 W=1.575u L=1.05u Q32 wp lp Q22 M=4 VDD Transistor parameters Ioutn Iinn Iinp

differential OTA is divided into differential pair sections Four-capacitor

42 CTIA physical design Matching transistors and capacitors All differential pairs are designed with multi-finger, common-centroid structure The differential OTA is divided into differential pair sections Four-capacitor layout using common-centroid techniques Dummy cap in the middle shorted to ground

43 ROIC physical design Fully differential CTIA amplifier

44 ROIC physical design

45 ORTHOGONALLY MODULATED CMOS READOUT INTEGRATED CIRCUIT FOR IMAGING APPLICATIONS Introduction and motivation Contribution Phase I: Proof of principle Orthogonal encoding readout system description Prototype system design and verification Conclusions Contribution Phase II: Improving the system performance Readout cell improvements Transimpedance amplifier integration Conclusion and brainstorm on further improvements

46 Conclusion Satisfactory results with the prototype experiment confirm validity of the orthogonal encoding scheme for readout circuits Expect system performance improvement with the design optimization of the readout cell and the integration of the fully differential CTIA + + i () t = i () t c() t + n + i () t c() t + n, o in c in c + i () t = i () t c() t + n + i () t c() t + n, o in c in c + + i () t = i () t i () t = [ i () t i ()][() t c t c()], t od o o in in The readout cell with the codemodulator only is an outstanding candidate for highly-scalable imaging systems. Its characteristics: only four transistors, zero noise, no power consumption, no band width limitations. Further improvement is accomplished if differential photodetector devices are used

47 Conclusion (cont d) Take advantage of switched nature of the system to cancel charge injection peaks from readout cells. With code-modulator-only cells the system becomes highlyscalable but the noise performance of the OTA amplifier needs to be improved by one order of magnitude Code-modulator-only readout cell array Capacitive Transimpedance amplifier per row

48 Conclusion (cont d) Integrating an amplifier to perform differential to singleended conversion inside the chip would improve the system performance (pedestal voltages and vestigial voltage spikes would be cancelled inside the integrated circuit) Single-ended output Capacitive Transimpedance amplifier per row Differential amplifier per row

49 Acknowledgements Thanks to everybody who has been involved in the dissertation process in one way or another Fouad, Bill, Mayra LADAR group, thanks so much for the support

0.18 μm CMOS Fully Differential CTIA for a 32x16 ROIC for 3D Ladar Imaging Systems

0.18 μm CMOS Fully Differential CTIA for a 32x16 ROIC for 3D Ladar Imaging Systems Jirar Helou Jorge Garcia Fouad Kiamilev University of Delaware Newark, DE William Lawler Army Research Laboratory Adelphi,