3.1-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER

Transcription

1 SLOS367B AUGUST 3 REVISED AUGUST 4 3.-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER TPA6A FEATURES APPLICATIONS Designed for Wireless or Cellular Handsets Ideal for Wireless Handsets, PDAs, and and PDAs Notebook Computers 3. W Into 3Ω From a -V Supply at THD = % (Typ) DESCRIPTION Low Supply Current: 4 ma Typ at V The TPA6A is a 3.-W mono fully-differential amplifier designed to drive a speaker with at least Shutdown Current:. µa Typ 3-Ω impedance while consuming only mm total Fast Startup With Minimal Pop printed-circuit board (PCB) area in most applications. Only Three External Components The device operates from. V to. V, drawing Improved PSRR (-8 db) and Wide Supply only 4 ma of quiescent supply current. The TPA6A is available in the space-saving Voltage (. V to. V) for Direct Battery 3-mm 3-mm QFN (DRB) and the 8-pin MSOP Operation (DGN) PowerPAD packages. Fully Differential Design Reduces RF Rectification Features like -8 db supply voltage rejection from Hz to khz, improved RF rectification immunity, -63 db CMRR Eliminates Two Input small PCB area, and a fast startup with minimal pop Coupling Capacitors makes the TPA6A ideal for PDA/smart phone applications. APPLICATION CIRCUIT 8-PIN QFN (DRB) PACKAGE (TOP VIEW) V DD 6 To Battery SHUTDOWN 8 V O- In From DAC - + R I R I kω IN- IN+ _ + V O+ V O- 8 C s BYPASS IN+ IN GND V DD V O+ 4 kω GND 7 DGN PACKAGE (TOP VIEW) SHUTDOWN C () (BYPASS) kω Bias Circuitry SHUTDOWN BYPASS IN+ IN V O- GND V DD V O+ () C (BYPASS) is optional. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 3 4, Texas Instruments Incorporated

2 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. NAME T A SMALL OUTLINE (DRB) ORDERING INFORMATION PACKAGED DEVICES () MSOP PowerPAD (DGN) EVALUATION MODULES -4 C to 8 C TPA6ADRB TPA6ADGN TPA6AEVM () The DGN and DRB are available taped and reeled. To order taped and reeled parts, add the suffix R to the part number (TPA6ADGNR or TPA6ADRBR). TERMINAL DRB, DGN IN- 4 I Negative differential input IN+ 3 I Positive differential input I/O V DD 6 I Power supply V O+ O Positive BTL output GND 7 I High-current ground V O- 8 O Negative BTL output Terminal Functions SHUTDOWN I Shutdown terminal (active low logic) DESCRIPTION BYPASS Mid-supply voltage, adding a bypass capacitor improves PSRR Thermal Pad - - Connect to ground. Thermal pad must be soldered down in all applications to properly secure device on the PCB. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted () V DD Supply voltage -.3 V to 6 V V I Input voltage -.3 V to V DD +.3 V Continuous total power dissipation UNIT See Dissipation Rating Table T A Operating free-air temperature -4 C to 8 C T J Junction temperature -4 C to C T stg Storage temperature -6 C to 8 C Lead temperature,6 mm (/6 Inch) from case for seconds DRB 6 C DGN 3 C () Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PACKAGE DISSIPATION RATINGS PACKAGE T A C DERATING T A = 7 C T A = 8 C POWER RATING FACTOR () POWER RATING POWER RATING DGN.3 W 7. mw/ C.36 W. W DRB.7 W.8 mw/ C.7 W.4 W () Derating factor based on high-k board layout.

3 SLOS367B AUGUST 3 REVISED AUGUST 4 RECOMMENDED OPERATION CONDITIONS TPA6A MIN TYP MAX UNIT V DD Supply voltage.. V V IH High-level input voltage SHUTDOWN. V V IL Low-level input voltage SHUTDOWN. V T A Operating free-air temperature -4 8 C ELECTRICAL CHARACTERISTICS T A = C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output offset voltage (measured V OS V I = V differential, Gain = V/V, V DD =. V mv differentially) PSRR Power supply rejection ratio V DD =. V to. V -8-6 db V IC Common mode input range V DD =. V to. V. V DD -.8 V V DD =. V, V IC =. V to 4.7 V CMRR Common mode rejection ratio db V DD =. V, V IC =. V to.7 V R L = 4 Ω, Gain = V/V, V DD =. V.4 Low-output swing V IN+ = V DD, V IN- = V or V DD = 3.6 V.37 V V IN+ = V, V IN- = V DD VDD =. V.6.4 R L = 4 Ω, Gain = V/V, V DD =. V 4.9 High-output swing V IN+ = V DD, V IN- = V or V DD = 3.6 V 3.8 V V IN- = V DD V IN+ = V V DD =. V.3 I IH High-level input current, shutdown V DD =. V, V I =.8 V 8 µa I IL Low-level input current, shutdown V DD =. V, V I = -.3 V 3 µa I Q Quiescent current V DD =. V to. V, no load 4 ma V(SHUTDOWN). V, V DD =. V to. V, I (SD) Supply current. µa R L = 4Ω 38 k 4 k 4 k Gain R L = 4Ω R I R I R V/V I Resistance from shutdown to GND kω 3

4 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 OPERATING CHARACTERISTICS T A = C, Gain = V/V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V DD = V.4 THD + N= %, f = khz, R L = 3 Ω V DD = 3.6 V. V DD =. V.49 V DD = V. P O Output power THD + N= %, f = khz, R L = 4 Ω V DD = 3.6 V. W V DD =. V.47 V DD = V.36 THD + N= %, f = khz, R L = 8 Ω V DD = 3.6 V.7 V DD =. V.33 P O = W V DD = V.4% f = khz, R L = 3 Ω P O = W V DD = 3.6 V.% P O = 3 mw V DD =. V.6% P O =.8 W V DD = V.3% THD+N Total harmonic distortion plus noise f = khz, R L = 4 Ω P O =.7 W V DD = 3.6 V.3% P O = 3 mw V DD =. V.4% P O = W V DD = V.% f = khz, R L = 8 Ω P O =. W V DD = 3.6 V.% P O = mw V DD =. V.3% V f = 7 Hz -8 DD = 3.6 V, Inputs ac-grounded with k SVR Supply ripple rejection ratio db C i = µf, V (RIPPLE) = mv pp f = Hz to khz -7 SNR Signal-to-noise ratio V DD = V, P O = W, R L = 4 Ω db V No weighting DD = 3.6 V, f = Hz to khz, V n Output voltage noise µv Inputs ac-grounded with Ci = µf RMS A weighting CMRR Common mode rejection ratio V DD = 3.6 V, V IC = V pp f = 7 Hz -6 db Z I Input impedance kω Start-up time from shutdown V DD = 3.6 V, No C BYPASS 4 µs V DD = 3.6 V, C BYPASS =. µf 7 ms 4

5 TPA6A TYPICAL CHARACTERISTICS SLOS367B AUGUST 3 REVISED AUGUST 4 Table of Graphs P O Output power FIGURE Supply voltage Load resistance P D Power dissipation Output power 3, 4 Output power, 6, 7 THD+N Total harmonic distortion + noise Frequency 8- Common-mode input voltage 3 K SVR Supply voltage rejection ratio Frequency 4,, 6, 7 K SVR Supply voltage rejection ratio Common-mode input voltage 8 GSM Power supply rejection Time 9 GSM Power supply rejection Frequency CMRR Common-mode rejection ratio Frequency Common-mode input voltage Closed loop gain/phase Frequency 3 Open loop gain/phase Frequency 4 I DD Supply current Supply voltage Shutdown voltage 6 Start-up time Bypass capacitor OUTPUT POWER SUPPLY VOLTAGE f = khz Gain = V/V P O = 3 Ω, THD % P O = 4 Ω, THD % 3. 3 OUTPUT POWER LOAD RESISTANCE V DD = V, THD % V DD = V, THD % f = khz Gain = V/V P O - Output Power - W.. P O = 8 Ω, THD % P O = 3 Ω, THD % P O = 4 Ω, THD % P O = 8 Ω, THD % P O - Output Power - W.. V DD = 3.6 V, THD % V DD = 3.6 V, THD % V DD =. V, THD % V DD =. V, THD % V DD - Supply Voltage - V R L - Load Resistance - Ω Figure. Figure.

6 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 - Power Dissiaption - W P D POWER DISSIPATION OUTPUT POWER V DD = 3.6 V 4 Ω 8 Ω - Power Dissiaption - W P D POWER DISSIPATION OUTPUT POWER 4 Ω V DD = V 8 Ω P O - Output Power - W P O - Output Power - W Figure 3. Figure 4. TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER THD+N - Total Harmonic Distortion + Noise - % R L = 3 Ω, C (BYPASS) = to µf, Gain = V/V. V m m m m m 3 P O - Output Power - W 3.6 V V THD+N - Total Harmonic Distortion + Noise - %..... R L = 4 Ω, C (BYPASS) = to µf, Gain = V/V. V 3.6 V V. m m m m m m 3 P O - Output Power - W Figure. Figure 6. 6

7 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 THD+N - Total Harmonic Distortion + Noise - %..... TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER R L = 8 Ω, C (BYPASS) = to µf, Gain = V/V. V 3.6 V V. m m m m m m 3 P O - Output Power - W THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE V DD = V, R L = 3 Ω,, C (BYPASS) = to µf, Gain = V/V, C I = µf W W k k k k k f - Frequency - Hz Figure 7. Figure 8. THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE V DD = V, R L = 4 Ω,, C (BYPASS) = to µf, Gain = V/V, C I = µf.8 W W W k k k k k f - Frequency - Hz THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE V DD = 3.6 V, R L = 4 Ω,, C (BYPASS) = to µf, Gain = V/V, C I = µf. W. W W k k k k k f - Frequency - Hz Figure 9. Figure. 7

8 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE V DD =. V, R L = 4 Ω,, C (BYPASS) = to µf, Gain = V/V, C I = µf.8 W.4 W. k k k k k f - Frequency - Hz THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE V DD = 3.6 V, R L = 8 Ω,, C (BYPASS) = to µf, Gain = V/V, C I = µf. W.6 W. W k k k k k f - Frequency - Hz Figure. Figure. THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE COMMON MODE INPUT VOLTAGE f = khz P O = mw, R L = khz V DD =. V V DD = 3.6 V V DD = V V IC - Common Mode Input Voltage - V k SVR - Supply Voltage Rejection Ratio - db SUPPLY VOLTAGE REJECTION RATIO R L = 4 Ω,, C (BYPASS) =.47 µf, Gain = V/V, C I = µf, Inputs ac Grounded V DD =. V V DD = V - k k k k k f - Frequency - Hz V DD = 3.6 V Figure 3. Figure 4. 8

9 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 k SVR - Supply Voltage Rejection Ratio - db SUPPLY VOLTAGE REJECTION RATIO R L = 4 Ω,, C (BYPASS) =.47 µf, Gain = V/V, C I = µf, Inputs ac Grounded V DD =. V V DD = V V DD = 3.6 V k SVR - Supply Voltage Rejection Ratio - db SUPPLY RIPPLE REJECTION RATIO R L = 4 Ω,, C (BYPASS) =.47 µf, C I = µf, V DD =. V to V Inputs Floating - k k k k k f - Frequency - Hz - k k k k k f - Frequency - Hz Figure. Figure 6. k SVR Supply Voltage Rejection Ratio db SUPPLY VOLTAGE REJECTION RATIO R L = 4 Ω,, C I = µf, Gain = V/V, V DD = 3.6 V C (BYPASS) =. µf No C (BYPASS) C 9 (BYPASS) = µf C (BYPASS) =.47 µf k k k k k f Frequency Hz k SVR Supply Voltage Rejection Ratio db SUPPLY VOLTAGE REJECTION RATIO DC COMMON MODE INPUT V DD =. V V DD = 3.6 V R L = 4 Ω,, C I = µf, Gain = V/V, C (BYPASS) =.47 µf V DD = 3.6 V, f = 7 Hz, Inputs ac Grounded V DD = V DC Common Mode Input V Figure 7. Figure 8. 9

10 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 GSM POWER SUPPLY REJECTION TIME Voltage V V DD C Frequency 7 Hz C Duty % C Pk Pk mv V OUT R L = 8 Ω C I =. µf C (BYPASS) =.47 µf Ch mv/div Ch4 mv/div t Time ms Figure 9. ms/div Output Voltage dbv V O 4 GSM POWER SUPPLY REJECTION V DD Shown in Figure 9, R L = 8 Ω, C I =. µf, Inputs Grounded 6 C (BYPASS) =.47 µf f Frequency Hz Figure. Supply Voltage dbv VDD

11 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 CMRR - Common-Mode Rejection Ratio - db COMMON MODE REJECTION RATIO R L = 4 Ω,, V IC = mv V p-p, Gain = V/V, V DD =. V V DD = V CMRR - Common Mode Rejection Ratio - db COMMON-MODE REJECTION RATIO COMMON-MODE INPUT VOLTAGE R L = 4 Ω,, Gain = V/V, dc Change in V IC V DD = 3. V V DD =. V V DD = V - k k k k k f - Frequency - Hz V IC - Common Mode Input Voltage - V Figure. Figure. Gain - db V DD = V R L = 8 Ω A V = CLOSED LOOP GAIN/PHASE Phase Gain -8 k k k M M f - Frequency - Hz Phase - Degrees Gain db V DD = V, R L = 8 Ω OPEN LOOP GAIN/PHASE Phase Gain k k k M f Frequency Hz Phase Degrees Figure 3. Figure 4.

12 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 I DD - Supply Current - ma V DD = V SUPPLY CURRENT SUPPLY VOLTAGE T A = C T A = C T A = -4 C I DD - Supply Current - ma... SUPPLY CURRENT SHUTDOWN VOLTAGE V DD = V V DD = 3.6 V V DD =. V V DD - Supply Voltage - V. 3 4 Voltage on SHUTDOWN Terminal - V Figure. Figure 6. 3 START-UP TIME BYPASS CAPACITOR Start-Up Time - ms C (Bypass) - Bypass Capacitor - µf Figure 7.

13 APPLICATION INFORMATION APPLICATION SCHEMATICS TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 Mid-supply bypass capacitor, C (BYPASS), not FULLY DIFFERENTIAL AMPLIFIER required: The fully differential amplifier does not require a bypass capacitor. Any shift in the The TPA6A is a fully differential amplifier with mid-supply voltage affects both positive and differential inputs and outputs. The fully differential negative channels equally, thus canceling at the amplifier consists of a differential amplifier and a differential output. Removing the bypass capacicommon- mode amplifier. The differential amplifier tor slightly worsens power supply rejection ratio ensures that the amplifier outputs a differential volt- (k SVR ), but a slight decrease of k SVR may be age that is equal to the differential input times the acceptable when an additional component can be gain. The common-mode feedback ensures that the eliminated (See Figure 7). common-mode voltage at the output is biased around V Better RF-immunity: GSM handsets save power DD / regardless of the common- mode voltage at the input. by turning on and shutting off the RF transmitter at a rate of 7 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal much Advantages of Fully Differential Amplifiers Input coupling capacitors not required: A fully better than the typical audio amplifier. differential amplifier with good CMRR, like the TPA6A, allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC has a lower mid-supply voltage than that of Figure 8 through Figure 3 show application schethe TPA6A, the common-mode feedback matics for differential and single-ended inputs. Typical circuit compensates, and the outputs are still values are shown in Table. biased at the mid-supply point of the TPA6A. The inputs of the TPA6A can be biased from. V to V DD -.8 V. If the inputs are biased outside of that range, input coupling capacitors are required. Table. Typical Component Values COMPONENT VALUE R I 4 kω C () (BYPASS). µf () C (BYPASS) is optional. C S µf C I. µf V DD 6 To Battery 4 kω C s In From DAC + R I R I 4 3 IN IN+ _ + V O+ V O 8 4 kω GND 7 SHUTDOWN C () (BYPASS) kω Bias Circuitry () C (BYPASS) is optional Figure 8. Typical Differential Input Application Schematic 3

14 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 V DD 6 To Battery C I R I 4 4 kω IN _ V O+ C s + R I 3 IN+ + V O 8 C I 4 kω GND 7 SHUTDOWN C () (BYPASS) kω Bias Circuitry () C (BYPASS) is optional Figure 9. Differential Input Application Schematic Optimized With Input Capacitors V DD 6 To Battery IN C I R I 4 4 kω IN _ V O+ C s R I 3 IN+ + V O 8 C I 4 kω GND 7 SHUTDOWN C () (BYPASS) kω Bias Circuitry () C (BYPASS) is optional Figure 3. Single-Ended Input Application Schematic 4

15 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 C F C F V DD 6 To Battery R a C a C I R I 4 4 kω IN _ V O+ C s + R a C I R I 3 IN+ 4 kω + V O GND 8 7 C a SHUTDOWN C () (BYPASS) kω Bias Circuitry () C (BYPASS) is optional Figure 3. Differential Input Application Schematic With Input Bandpass Filter Selecting Components Input Capacitor (C I ) The TPA6A does not require input coupling Resistors (R I ) capacitors when driven by a differential input source The input resistor (R I ) can be selected to set the gain biased from. V to V DD -.8 V. Use % tolerance of the amplifier according to equation. or better gain-setting resistors if not using input Gain = R F /R coupling capacitors. I () In the single-ended input application, an input capaci- The internal feedback resistors (R F ) are trimmed to tor, C I, is required to allow the amplifier to bias the 4 kω. input signal to the proper dc level. In this case, C I and Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and the cancellation of the second harmonic distortion diminishes if resistor mismatch occurs. Therefore, %-tolerance resistors or better are recommended to optimize performance. Bypass Capacitor (C BYPASS ) and Start-Up Time The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references and sets the output common mode voltage to V DD /. Adding a capacitor filters any noise into this pin, increasing k SVR. C (BYPASS) also determines the rise time of V O+ and V O- when the device exits shutdown. The larger the capacitor, the slower the rise time. R I form a high-pass filter with the corner frequency defined in Equation. f c R C I I () -3 db f c

16 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 The value of C I is an important consideration. It Substituting R I into equation 6. directly affects the bass (low frequency) performance f of the circuit. Consider the example where R I is c(hpf) k C kω and the specification calls for a flat bass response I (8) down to Hz. Equation is reconfigured as Therefore, Equation 3. C I R I f c (3) Band-Pass Filter (R a, C a, and C a ) It may be desirable to have signal filtering beyond the one-pole high-pass filter formed by the combination of C I and R I. A low-pass filter may be added by placing a capacitor (C F ) between the inputs and outputs, forming a band-pass filter. An example of when this technique might be used would be in an application where the desirable pass-band range is between Hz and khz, with a gain of 4 V/V. The following equations illustrate how the proper values of C F and C I can be determined. Step : Low-Pass Filter f c(lpf) R C F F where R is the internal 4 k resistor F (4) f c(lpf) 4 k C F () Therefore, C F C I C a 4 k f c(lpf) (6) db 9 db AV k f c(hpf) (9) Substituting Hz for f c(hpf) and solving for C I : C I =.6 µf In this example, C I is.6 µf, so the likely choice ranges from. µf to.47 µf. Ceramic capacitors are preferred because they are the best choice in preventing leakage current. When polarized capaci- tors are used, the positive side of the capacitor faces the amplifier input in most applications. The input dc level is held at V DD /, typically higher than the source dc level. It is important to confirm the capacitor polarity in the application. At this point, a first-order band-pass filter has been created with the low-frequency cutoff set to Hz and the high-frequency cutoff set to khz. The process can be taken a step further by creating a second-order high-pass filter. This is accomplished by placing a resistor (R a ) and capacitor (C a ) in the input path. It is important to note that R a must be at least times smaller than R I ; otherwise its value has a noticeable effect on the gain, as R a and R I are in series. Step 3: Additional Low-Pass Filter R a must be at least x smaller than R I, Set R a = kω f c(lpf) R a C a () Therefore, kω f c(lpf) () Substituting khz for f c(lpf) and solving for C a : C a = 6 pf Figure 3 is a bode plot for the band-pass filter in the previous example. Figure 3 shows how to configure the TPA6A as a band-pass filter. Substituting khz for f c(lpf) and solving for C F : C F = 398 pf Step : High-Pass Filter f c(hpf) R C I I where R is the input resistor I Since the application in this case requires a gain of 4 V/V, R I must be set to kω. (7) + db/dec db/dec 4 db/dec f c(hpf) = Hz f c(lpf) = khz f Figure 3. Bode Plot 6

17 Decoupling Capacitor (C S ) The TPA6A is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically. µf to µf, placed as close as possible to the device V DD lead works best. For filtering lower frequency noise signals, a -µf or greater capacitor placed near the audio power amplifier also helps, but is not required in most applications because of the high PSRR of this device. USING LOW-ESR CAPACITORS Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor. DIFFERENTIAL OUTPUT VERSUS SINGLE-ENDED OUTPUT V (rms) Power V O(PP) V (rms) R L () V DD R L V DD V O(PP) x V O(PP) -V O(PP) TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 Figure 33. Differential Output Configuration In a typical wireless handset operating at 3.6 V, bridging raises the power into an 8-Ω speaker from a singled-ended (SE, ground reference) limit of mw to 8 mw. This is a 6-dB improvement in sound Figure 33 shows a Class-AB audio power amplifier power loudness that can be heard. In addition to (APA) in a fully differential configuration. The increased power, there are frequency-response con- TPA6A amplifier has differential outputs driving cerns. Consider the single-supply SE configuration both ends of the load. One of several potential shown in Figure 34. A coupling capacitor (C C ) is benefits to this configuration is power to the load. The required to block the dc-offset voltage from the load. differential drive to the speaker means that as one This capacitor can be quite large (approximately 33 side is slewing up, the other side is slewing down, µf to µf) so it tends to be expensive, heavy, and vice versa. This in effect doubles the voltage occupy valuable PCB area, and have the additional swing on the load as compared to a drawback of limiting low-frequency performance. This ground-referenced load. Plugging V O(PP) into the frequency-limiting effect is due to the high-pass filter power equation, where voltage is squared, yields 4 network created with the speaker impedance and the the output power from the same supply rail and load coupling capacitance. This is calculated with impedance Equation. Equation 3. f c R C L C (3) For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 93 Hz. The BTL configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency performance is then limited only by the input network and speaker response. Cost and PCB space are also minimized by eliminating the bulky coupling capacitor. 7

18 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 V DD C C R L V O(PP) V O(PP) An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 3). V O -3 db V (LRMS) I DD f c Figure 34. Single-Ended Output and Frequency Response Increasing power to the load does carry a penalty of increased internal power dissipation. The increased dissipation is understandable considering that the BTL configuration produces 4 the output power of the SE configuration. FULLY DIFFERENTIAL AMPLIFIER EFFICIENCY AND THERMAL INFORMATION Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different. Keep in mind that for most of the waveform both the push and pull transis- tors are not on at the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform. The following equations are the basis for calculating amplifier efficiency. Class-AB amplifiers are inefficient, primarily because of voltage drop across the output-stage transistors. The two components of this internal voltage drop are the headroom or dc voltage drop that varies inversely to output power, and the sinewave nature of the output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from V DD. The internal voltage drop multiplied by the average value of the supply current, I DD (avg), determines the internal power dissipation of the amplifier. I DD(avg) Figure 3. Voltage and Current Waveforms for BTL Amplifiers 8

19 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 Efficiency of a BTL amplifier P L P SUP Where: P L V L rms R L, and V V P LRMS, therefore, P L V P R L and P SUP V DD I DD avg and I DD avg V P R L sin(t) dt V P R L [cos(t)] V P R L Therefore, P V DD V P SUP R L substituting P L and P SUP into equation 6, V P Efficiency of a BTL amplifier Where: V P Therefore, BTL P R L L P R L L 4 V DD R L V DD V P R L V P 4 V DD P L = Power delivered to load P SUP = Power drawn from power supply V LRMS = RMS voltage on BTL load R L = Load resistance V P = Peak voltage on BTL load I DD avg = Average current drawn from the power supply V DD = Power supply voltage η BTL = Efficiency of a BTL amplifier (4) () Table. Efficiency and Maximum Ambient Temperature Output Power Output Power Efficiency Internal Dissipation Power From Supply Max Ambient Temperature () (W) (%) (W) (W) ( C) -V, 3-Ω Systems () V, 4-Ω BTL Systems () () () () -V, 8-Ω Systems () () () () () DRB package () Package limited to 8 C ambient 9

20 TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 Table employs Equation to calculate efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a.8-w audio system with 4-Ω loads and a -V supply, the maximum draw on the power supply is almost 3.8 W. A final point to remember about Class-AB amplifiers is how to manipulate the terms in the efficiency equation to the utmost advantage when possible. Note that in Equation, V DD is in the denominator. This indicates that as V DD goes down, efficiency goes up. Table shows that for most applications no airflow is required to keep junction temperatures in the speci- fied range. The TPA6A is designed with thermal protection that turns the device off when the junction temperature surpasses C to prevent damage to the IC. In addition, using speakers with an impedance higher than 4-Ω dramatically increases the thermal performance by reducing the output current. A simple formula for calculating the maximum power dissipated, P Dmax, may be used for a differential output application: P Dmax V DD R L (6) P Dmax for a -V, 4-Ω system is.7 W. The maximum ambient temperature depends on the heat sinking ability of the PCB system. The derating factor for the 3 mm x 3 mm DRB package is shown in the dissipation rating table. Converting this to θ JA : θ JA Derating Factor C W (7) Given θ JA, the maximum allowable junction tempera- ture, and the maximum internal dissipation, the maxi- mum ambient temperature can be calculated with Equation 8. The maximum recommended junction temperature for the TPA6A is C. T A Max T J Max θ JA P Dmax 4.9(.7) 9.7 C (8) Equation 8 shows that the maximum ambient temperature is 9.7 C (package limited to 8 C ambient) at maximum power dissipation with a -V supply.

21 PCB LAYOUT TPA6A SLOS367B AUGUST 3 REVISED AUGUST 4 Use the following land pattern for board layout with the 8-pin QFN (DRB) package. Note that the solder paste should use a hatch pattern to fill solder paste at % to ensure that there is not too much solder paste under the package..7 mm.33 mm plugged vias ( places).4 mm.38 mm.6 mm.9 mm Solder Mask:.4 mm x.8 mm centered in package Make solder paste a hatch pattern to fill % 3.3 mm Figure 36. TPA6A 8-Pin QFN (DRB) Board Layout (Top View)

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