Research Paper FPGA BASED SIGMA DELTA MODULATION FOR DC-DC FLYBACK CONVERTER

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1 Research Paper FPGA BASED SIGMA DELTA MODULATION FOR DC-DC FLYBACK CONVERTER 1 Dr.K.R.Aravind Britto, 2 Dr.R.Vimala Address for Correspondence 1 Assistant Professor, ECE, PSNA College of Engineering and Technology, Dindigul, India. 2 Assistant Professor, EEE, PSNA College of Engineering and Technology, Dindigul, India. ABSTRACT This paper proposes the FPGA-Based pipelined sigma delta modulation for conducted-noise reduction in dc-dc fly back converters. Traditionally, the implementation of the switching-mode power supply (SMPS) has been accomplished using analog control circuits. However, the field-programmable gate array (FPGA) is much flexible than analog control circuits, becoming lower cost, and applicable for power supply applications. The implementation of the SMPS has been accomplished using FPGA-based digital controller. This paper proposes a digital control system that adopts a new Adaptive DPWM topology to achieve high resolution without clock spurs. Effective prototype DPWM along with a digital neural network control algorithm is verified by using a Xilinx Spartan-3E FPGA on a Fly-Back converter. Adaptive resolution of ADC is introduced as a digital source to increase the flexible effective DPWM resolution, thus enhancing limit cycling, and enabling low-power, small-area DPWM implementations. The proposed DPWM takes advantage of Digital Clock Manager (DCM) phase-shift characteristics which is available in high speed digital circuit and combines a counter-comparator with a Multistage-noise-Shaping (MASH) pipelined Delta-Sigma modulator. Utilizing the selectable frequency regulator to optimization of ADC resolution, we can switch to the high-resolution ADC speed up the feedback time when system tends to be unstable, or the medium resolution ADC to eliminate the power consumption when the system is stable. INDEX TERMS: Electromagnetic Compatibility (EMC), FPGA, Adaptive DPWM, Fly-back Converter, SMPS, EMI. 1. INTRODUCTION Digital controllers will increasingly replace currently predominant analogue controllers in high frequency switch- mode power supply applications. The advantages of digital controller implementation include much improved flexibility, reduced design time, programmability, and improved system reliability, easier system integration, and possibility to include various performance enhancements[1]-[6]. One of the disadvantages of digital controller perhaps is the limited discrete resolution of DPWM, which ultimately determines the discrete output voltage of power converter. If the DPWM resolution is not sufficiently high, an undesirable limit-cycle oscillation can occur [6]-[9]. A possible approach to get out of the difficulty is to design and implement high resolution DPWM device, in which the clock frequency is of hundreds MHz based on high technology and expenditure [10]-[12]. Switching power converter devices are often composed of several sub circuits, and each sub circuit requires a unique voltage level that is different from that supplied by the source. Switching power converters have been reported to generate commonand differential-mode conducted noises, in addition to radiated noise. They may cause serious problems by generating such switching noise. Although switching converters produce significant amounts of switching noise, they are also required to operate inside Electro- Magnetic Interference (EMI) sensitive applications. Thus, it is necessary to find a mitigation technique to overcome this problem [16], [17]. This paper aims to reduce the switching noise produced by Fly-back converters. Common methods for EMI suppression are related to the use of filters and shielding techniques. However, these tools are bulky and require expensive passive components, which makes them unsuitable for spacelimited and price-sensitive portable devices [18], [19]. However, this switching noise rises among the high speed switching period and manifests itself in the form of ripple at the output in the time domain and as spurs at discrete multiples of the clock frequency f clk in the frequency domain. In this paper, we design and implement an adaptive DPWM based digital controller for a low-power converter. It is required to maintain tight voltage regulation and high efficiency over wide ranges of input voltage and loads. To avoid limit cycling oscillation, a MASH pipelined sigma delta modulator and neural network controller is introduced which is in parallel connected to digital controller. The Adaptive DPWM based digital controller constructs continuous duty ratios with which a very high resolution of the output voltage can be obtained. The noise directly couples into the components that draw current from the converter. The conventional schematic diagram of a digital controller for Fly-Back converter is shown in Figure 1, where the digital controller consists of three blocks: Analog-to-Digital Converter (ADC), control circuits and adaptive DPWM. Different from analog controller, all the signals are processed in discrete data from inside the digital controller. Fig.1. Schematic diagram of digital controller for Fly-back converter In order to improve the discrete accuracy of output voltage and eliminate undesirable limit-cycle oscillation, the DPWM resolution is required as high as possible [20]. Here high resolution means high power consumption. The energy consumption of DPWM has a proportional relationship with the switching frequency and the PWM resolution. This constraint limits not only the switching frequency but also DPWM resolution. Different DPWM resolutions for different switching frequencies and different practical applications are used to adaptive for the system stability [21], [22]. Based on the effective - noise-shaping approach and the functionally DLL phase-shift module, this paper explains an Adaptive DPWM, which consists

2 of Digital Clock Manager (DCM), phase-shift characteristics available in FPGA with a selectable frequency Fly-back converter, and combines a counter-comparator block with Multi-stAge-noise- SHaping (MASH) - modulator. This Adaptive approach can not only obtain a high-resolution DPWM while reducing system clock frequency, but also enhance the efficiency to the system by tuning ADC resolution to against the incoming noise. The converter output voltage is converted into a digital 8-bit signal by means of analog to digital converter (ADC). This signal is processed by the digital compensator to calculate the duty-ratio (d). The ADC s driver is designed and imbedded in the FPGA-based digital controller. This completes the conversion and enables the output buffers that contain the conversion result. The driver commands the digital compensator to read the conversion result. The conversion cycle is started with the switching cycle and completed within the same switching cycle. 2. NEURAL NETWORK CONTROLLER In the past decade, the controller for the PWM switching control is restraining to Proportional- Integral-Differential (PID) controller. This controller often applied to the converters because of their simplicity. However, implementations of this control method to the nonlinear plants such as the power converters will undergo from dynamic response of the converter output voltage regulation. In general, PID controller produces long rise time when the overshoot in output voltage decreases. In order to tackle this problem and improve the dynamic response of DC-DC converters, several intelligence controllers such as fuzzy logic control, neural network control and hybrid neuro-fuzzy control methods for DC-DC converter have been reported. The purpose and utilization of the fuzzy controller for dc-dc converter has been developed. Implementations of the fuzzy logic control to dc-dc converter using micro controller have been verified. Inherently, the relatively simple fuzzy controller has a good performance for those systems where linear control technique fail and can apply to any dc-dc converter topologies. Neural network controls [NNC] for the DC-DC converter has been tested in both laboratory and computer simulation model both turned out to be successful. NNCs illustrate the result in minimizing the difference between the output voltage and the reference voltage. In addition, the dynamic characteristics of dc-dc converter are improved and can realize excellent dynamic characteristics with the used of neural network as compare with the conventional PID method. In order to improve performance of the NNC some researchers have been done to develop online learning scheme of the NNC. 2.1 THE BACK-PROPAGATION LEARNING A back propagation neural network uses a feedforward topology, supervised learning, and back propagation learning algorithm. This algorithm was responsible in large part for the re-emergence of neural networks in the mid-1980s. Back propagation is a general purpose learning algorithm. A back propagation network with a single hidden layer of processing elements can model any continuous function to any degree of accuracy (given enough processing elements in the hidden layer). The input pattern is presented to the input layer of the network. These inputs are propagated through the network until they reach the output units. This forward pass produces the actual or predicted output pattern. Because back propagation is a supervised learning algorithm, the desired outputs are given as part of the training vector. The actual network outputs are subtracted from the desired outputs and an error signal is produced. This error signal is then the basis for the back propagation step, whereby the errors are passed back through the neural network by computing the contribution of each hidden processing unit and deriving the corresponding adjustment needed to produce the correct output. The connection weights are then adjusted and the neural network has just learned from an experience. Fig.2.Back propagation network 2.2. IMPLEMENTATION OF BACK PROPAGATIONALGORITHM The back-propagation algorithm consists of the following steps: Each Input is then multiplied by a weight that would either inhibit the input or excite the input. The weighted sum of then inputs in then calculated first, it computes the total weighted input, using the formula = (1) Where is the activity level of the jth unit in the previous layer and is the weight of the connection between the ith and the jth unit.then the weighed is passed through a sigmoid function that would scale the output in between a 0 and 1.Next, the unit calculates the activity using some function of the total weightedinput. Typically we use the sigmoid function: = (2) Once the output is calculated, it is compared with the required output and the total Error E is computed. Once the activities of all output units have been determined, the network computes the error E, which is defined by the expression: E = ( ) (3) where y j is the activity level of the i th unit in the top layer and d j is the desired output of the i th unit. Now the error is propagated backwards. (i) Compute how fast the error changes as the activity of an output unit is changed. This error derivative (EA) is the difference between the actual and the desired activity. = = (4) (ii) Compute how fast the error changes as the total input received by an output unit is changed. This quantity (EI) is the answer from step 1 multiplied by the rate at which the output of a unit changes as its total input is changed. = = = 1 (5)

3 (iii) Compute how fast the error changes as a weight on the connection into an output unit is changed. This quantity (EW) is the answer from step 2 multiplied by the activity level of the unit from which the connection emanates. = = = (6) (iv) Compute how fast the error changes as the activity of a unit in the previous layer is changed. This crucial step allows back propagation to be applied to multi-layer networks. When the activity of a unit in the previous layer changes, it affects the activities of all the output units to which it is connected. So to compute the overall effect on the error, we add together all these separate effects on output units. But each effect is simple to calculate. It is the answer in step 2 multiplied by the weight on the connection to that output unit. = = = (7) By using steps 2 and 4, we can convert the EA s of one layer of units into EA s for the previous layer. This procedure can be repeated to get the EA s for as many previous layers as desired. Once we know the EA of a unit, we can use steps 2 and 3 to compute the EW s on its incoming connections. 3. ADAPTIVE DPWM ARCHITECTURE Based on the Multi-stage-noise-Shaping pipelined Delta-Sigma modulator architecture, Adaptive DPWM includes three blocks: the 5-bit pipelined MASH - block, the 4-bit Adaptive DCM block and the K-bit counter comparator where K is the adaptive index inherent from PWM resolution. In order to realize the adaptive function of MASH - modulator, the resolution of MASH - and DCM block is fixed but with different frequency adaptive to the switch corresponding to the resolution of ADC. Figure 3 shows the three function blocks of the Adaptive DPWM Multi-Bit Mashpipelined - DPWM Delta-Sigma - is mostly used in digital-to analog and analog-to-digital conversion. It is based on the noise-shaping approach which can be fabricated in low-cost CMOS technologies [23]-[24]. Based on the useful single-stage - noise-shaping modulator, the cascade modulator, also called Multistage-noise- SHaping (MASH) modulator is used to improve the noise-shaping of the system. The transfer function in linear model is given by v( u( He (. y( He (. v( E( v( u ( z ) [1 H e ( ]. E ( (8) Where u(is the input duty value, E( is the truncation error, H e is a delay or an integrator, and Y(is the output duty value. In Eq. (9), the STF ( is the Signal Transfer Function and NTF(is the Noise Transfer Function. Setting the filter H e as a digital delay z -1 then the STF=1 and NTF ( =1-z -1 in Eq. (9). k8bit Truncation z -1 Truncation Z -1 E 1 H 1 E 2 e 2 e 1 k2msb 2MSB 5MSB H 2 Z -1 1 & - - k4bit C(t) Core ADPWM Fig.4. Single stage - modulator for DPWM with an error feedback filter In steady-state, - the loop has an infinite gain at zero frequency (z 1) and the noise can be decreased significantly ( NTF( <<1)such that it can eliminate the input signal quantization error which is show in the following Eq. (10). STF(=1 NTF( <<1=v( u( (10) The first order - transfer form can easily associate to high-order form. The second order - transfer form is demonstrated as the following Eq.(11). 1 2 v( u( (1 z ). E2 ( (11) Pipelined MASH - modulator has its inherent noise-shaping performance of a second-order loop but only exist first-order loop stability issue. The theoretic scheme is shown in Figures 4. The K8 bit Adaptive DPWM duty value from controller is sent to the firststage loop, and then it distributes K2 MSB for output and 7-LSB for error-feedback. After the second stage loop, it delivers the 2-MSB for output and 5-LSB for error feedback e2. Finally the K4 bit combination of PWM signals (K2 MSB and 2 LSB) are sent to the Adaptive DCM and counter comparator blocks. Fig.3. Proposed adaptive DPWM block diagram Thus Eq. (8) can be revised to the digital form: v( STF (. u( NTF (. E( (9) Fig.5. Proposed reconfigurable sigma delta modulator Bit Adaptive DCM Block The Digital Clock Manager (DCM) functionality block is available in most FPGA devices, and it consists of the general Delay-Locked Loop (DLL) and/or Phase-Locked Loop (PLL) modules.

4 The FPGA based DCM module can not only generate four version phase-shift clocks (clk_0, clk_π/2,clk_π and clk_3π/2) respectively, but also produce four times of the incoming clock simultaneously. The four phase shifted clocks can act as an equivalent2 2 f s clock with a 4:1 multiplexer. Thus the switching frequency for the DCM architecture can be reduced by 2 2 times for a fixed-resolution ADPWM, or the resolution can be increased by 2 2 bits for a fixed-frequency ADPWM. To optimize the requirement of system clock frequency, and minimize the power consumption, which is dependent on the requirement of resolution and also the stability of control system. The segmented DCM phase-shift architecture including two DCM phase-shift modules in series is explained [11]. The similar DCM architecture is improved which called 4-bit Adapted-DCM block is described in this paper. The block diagram of the 4-bit Adapted-DCM architecture which consists of a DCM multiple and phase shift and a multiplexer. While the incoming clock f ADAPT go through the DCM multiple and phaseshift can be adjusted to the ADC resolution, the phase-shift block and adapted-multiplexer can generate only two different period s four version phase-shift signals s x and s y. Then those signal do the logic and, more precise 1/16 duty signal is produced K-Bit Couter-Comparator Block The Adaptive DPWM consists of a countercomparator which can adjust the incoming system clock frequency to adapt the change of ADC resolution. Linking to the MASH - and Adaptive DCM phase-shift blocks, the adaptive counter comparator block is used in the Adaptive DPWM. It includes a K-bit counter, a K-bit comparator and a D Flip- Flop with Asynchronous Clear and Preset (FDCP), where K is PWM resolution. 4. SIMULATION RESULTS AND ANALYSIS The comparison between conventional PI controller and the proposed NNC is done in this simulation. It is found that the output voltage start up transient response of the Flyback converter with reference voltage is higher than the input voltage source as in the case of the boost converter (the output voltage at 24 volt) and lower than the input voltage source as in the case of the buck converter (output voltage 12V) as shown in Figure 6 and Figure 7 respectively. Table.1. Parameters of fly back converter variable parameter value L1 Primary inductance 0.6(mH) n Turns ratio 1/4 C capacitance 100(µF) V1 Input voltage 12(volt) The proposed NNC produce a better performance than PI-Controller such as removing overshoot and oscillation to achieve desired output voltage. Furthermore, the settling time of the NNC is faster than PI-Controller. Fig.7.The output voltage transient response of the converter during starting-up at 24V The next step is to simulate the digital control system with different resolution to verify its performances. From the s, system behavior is analyzed more precisely. In order to produce the high resolution PWM signal, the system clock frequency must be enhanced to make sure its period is match with switching frequency. But the raised up frequency may increase power consumption, this cannot be changed arbitrary. Fig.8.PSD of the proposed modulator Fig.9. SNR vs OSR When the digital control system tends to be stable, the ADC s resolution is voluntarily enhanced by ADPWM to make our system more efficiency. The PWM accuracy can be enhanced by increasing the system clock frequency. The trade-off met between the accuracy and power consumption, this approach aid to improve this defect by Adapted DCM which can do the phase-shift and multiplier simultaneously. The s for the Adaptive DPWM are illustrated in Figures 10 to 12.When the digital control system operates in different ADC resolution, the ADPWM performance is changed. Fig.6.The output voltage transient response of the converter during starting-up at 12V Fig 10. Adaptive DPWM adapted to 12-bit ADC

5 Fig 11. daptive DPWM adapted to 24-bit ADC Fig 12. Adaptive DPWM adapted to 16-bit ADC In Figure 12, the system is operated in 24-bit ADC, where the duty of PWM is signal divided to 1024 parts, but the delay time merely is 0.24 ns. Due to this result, the characteristic between different cases accompany with ADC resolution, can be optimized by Adaptive DPWM to improve the optimum system efficiency. Table.2. ADC Resolution S.No Resolution Frequency Delay time 1 12 bit 5 MHz 38.5 ns 2 16 bit 10 MHz 7.8 ns 3 24 bit 12 MHz 0.24 ns 5. CONCLUSION In this paper a neural network control for Flyback DC-DC converter is discussed. To enhance performance of the voltage tracking of a Flyback converter, a back propagation learning algorithm is developed. The implementation of the back propagation learning technique is feasible for the Flyback converter based on the results in the simulation. It is observable that the NNC is effective in decreasing overshoot, reducing settling time and also has a fast response to track desired output voltage. A digital controller for high-frequency lowpower Fly back converter with high efficiency and high performance approach is achieved. This paper presents Adaptive DPWM architecture with the advantage of FPGA-based DCM phase-shift with selectable frequency converter, and the combination of a counter-comparator block with pipelined MASH - modulator. It effectively achieves an equivalent K 8 bit DPWM resolution only using the a 2-bit adaptive counter comparator and 4-bit Adaptive DCM block, which significantly eliminates the high clock frequency requirement. REFERENCES [1] D. Maksimovic, R. Zane, and R. Erickson, Impact of digital control in power electronics, in Proc. IEEE Int. Symp. Power Semicond.Devices ICs, May 2004, pp [2] G. Wei and M. Horowitz, "A fully digital, energy-efficient, adaptive power-supply regulator." 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