CIT 1 AND CIT 2, ADVANCED NON EPITAXIAL BIPOLAR/CMOS PROCESSES FOR ANALOG-DIGITAL VLSI

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1 CIT 1 AND CIT 2, ADANCED NON EPITAXIAL BIPOLAR/C PROCESSES FOR ANALOG-DIGITAL LSI C. olz, L. Blossfeld To cite this version: C. olz, L. Blossfeld. CIT 1 AND CIT 2, ADANCED NON EPITAXIAL BIPOLAR/C PRO- CESSES FOR ANALOG-DIGITAL LSI. Journal de Physique Colloques, 1988, 49 (C4), pp.c4-85- C4-88. < /jphyscol: >. <jpa > HAL Id: jpa Submitted on 1 Jan 1988 HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

2 JOURNAL DE PHYSIQUE Colloque C4, supplkment au n09, Tome 49, septembre 1988 CIT 1 AND CIT 2, ADANCED NON EPITAXIAL BIPOLAR/C PROCESSES FOR ANALOG-DIGITAL LSI C. OLZ and L. BLOSSFELD ITT Intermetall, Hans-Bunte-Str. 19, 'Freiburg, F.R.G. ABSTRACT Deux processus Bipolaire/C de haute performance ont dt: developp:s; les processus CIT 1 (2.0 pm) et CIT 2 ( pm). La technologie CIT nfutilise ni llepitaxie nl le buried layer. Des transistors bipolaires (npn, pnp) et des transistors (canal n, canal p) sont implantes avec succes sur un meme chip sans diminuer les performances des deux technologies en pr&sence. Two N-well high performance Bipolar/C processes have been developed; a 2.0 pm CIT 1 process and CIT 2, a pm process. CIT technology uses neither epitaxie nor buried layer. Bipolar txansistors (npn and pnp) and NOS transistors (n-channel and p-channel) have been sucessfully fabricated on the same chip without a decrease of the performance. I 1 INTRODUCTION For expanding markets like the consumer market, the automotive, or the telecommunication sectors, signal processors with working frequencies of 1 GHz and more are required. The integration of various kinds of functions on the same chip is advantegous. Today's system designs demand processes which allow integration on one chip [l For a high integration level the power consumption is also a very important issue. In the past bipolar devices have been used for these analog-digital applications. In this paper two new high performance nonepitaxial Bipolar/C processes are proposed; the 2.0 pm CIT 1 process and CIT 2 [4, 51, a pm process. Bipolar transistors (npn and pnp) and NOS transistors (both n-channel and p-channel) have been succesfully fabricated on the same chip, 2 DEICE STRUCTURE AND PROCESS SEQUENCE In the present CIT processes p-type <Ill> substrates with a resistivity of 2 cm are used as a starting material. The n-wells for the C transistors and the collectors of the bipolar transistors are formed by a phosphorous implantation. The n-layer has a sheet resistance of 1 k per square and is 2.5 pm deep. Base and drain/source for the p-channel transistors as well as the emitter and n+ drain/source are made simultaneously. The base is doped by a double boron implantation. The collector contact and the emitter area are defined by a nitride layer, which is used as a mask for the ion implantation of the extrinsic base. The intrinsic base is implanted through this nitride layer where the collector is protected by photoresist. The following oxidation creates a bird's beak. It allows a self aligned separation of the highly doped extrinsic base from the collector contact and the emitter area. Article published online by EDP Sciences and available at

3 After an arsenic ion implantation for emitter and n+ drain/source a dielectric layer of PECD oxide is deposited. In the channel region this oxide is removed. The threshold voltage is adjusted by ion implantation through an 80 nm thick gate'oxide. CIT 1 uses a metal gate. This process is very simple and needs only 6 photolithographic steps. Figure 1 shows the cross section of the 2.0 m Bipolar/C device structures. r After removing the nitride layer and gate oxidation, buried contacts for emitter, collector and drain/source are opened in the gate oxide, which has a thickness of 20 nm. Polysilicon is deposited and patterned. The polysilicon is used as an etch mask to remove the oxide on the external base. This step forms a vertical spacer. The 200 nm thick emitter polysilicon is doped by an arsenic ion in~plantation. To reduce the sheet resistance of the polysilicon (200 s per square) and of the extrinsic base a 50 nm thick layer of platinum silicide with a resistivity of 8 s per square is selectively deposited. The bipolar transistor surface is completely covered by this silicide. Both collector-base and base-emitter are electrically isolated by a vertical oxide spacer. After gate patterning, the lightly doped drain region is defined by a shallow ion implantation. The threshold voltage is adjusted by a deep ion implantation through the polysilicon layer. The n-channel drain/source contacts are completely covered by polysilicon. The p-channel drain/source diffusion and the n-doped polysilicon are linked by platinum silicide. The silicided polysilicon can be used as a first metal level. It can interconnect all kind of contacts, n- and p-channel. The second metal is 1.2 pm thick aluminium with 2 % silicon. Between platinum silicide and aluminium a 170 nm thick barrier layer of titanium is inserted. A third metal level is available. Figure 2 shows the cross section of the pm Bipolar/C device structures. 3 DEICE PERFORMANCE Table 1 gives a summary of the performance. 3.1 NPN DEICE PERFORMANCE Bipolar transistors with a performance comparable to those produced by conventional collector implanted bipolar processes were fabricated. The current gain was 80 and independent of the collector current up to 10 na. The breakdown voltages were BEBO =, BCBO = and BCEO =. The transition frequency ft was GHz for CIT 1 and 5.0 GHz for CIT C DEICE PERFORMANCE The threshold voltages and the transistor conductance (W/L = 1) of the CIT 1 devices are th = 1.75, Beta = 8 pa/2 for the n-channel transistor and th = -1.75, beta = 8 /2 for the p-channel transistor. Using 1 additional mask the thresholp voltages can be adjusted independently for the n- and

4 p-channel transistors. BY using the n-well as a lighty doped drain for the n-channel transistor a drain/source breakdown voltage of typically 40 was measured. The CIT 2 devices threshold voltages and conductances (W / L = 1) are th = 0.8 v, Beta = 50 lua/2 for the n-channel transistor and th = I Beta = 30 pa/2 for the p-channel transistor. 3.3 CIT 2 BASIC GATES To evaluate the basic gate delay, ringoscillators with 51 stages were fabricated. The minimum bipolar propagation delay time at 1.25 W is 0 ps for a fan out of 2. The C oscillator is interconnected only by polysilicon lines. Its minimum propagation delay is 280 ps for a fan out of 1. 4 CONCLUSION 2.0 um and um nonepitaxial Bipolar/C processes with high performance ECL circuits have been developed. The very simple metal gate process CIT 1 with arsenic implanted emitter needs only 6 photolithographic steps. The high speed process CIT 2 uses a polysilicon emitter and silicided polysilicon lines as a first metal level, The process is optimized for ECL within the Bipolar/C process. The minimum bipolar propagation delay is 0 ps. Both processes have the potential for monolithic multifunctional analog- digital LSI. 5 ACKNOWLEDGEMENT The authors thank the engineers of INTERMETALL Development Department for very helpful discussions and support. This work has been partly supported by the Federal Department of Research and Technology of the Federal Republic of Germany. 6 REFERENCES [I] Hiroshi Momose, Hideki Shibata, Shinji Saitoh, Junlichi Miyamoto, Kohichi Kanzaki, Susumu Kohyama: 1.0 pm n-well C/Bipolar Technology, IEEE Journal of Solid-State Circuits, ol.sc-20, No.1, February 1985 [2] Yutaka Okada, Kenji Kaneko, Satoshi Kudo, Kouichi Yamazaki, Takahiro Okabe: An Advanced Bipolar--I2L Technology with a Thin Epitaxial Layer for Analog-Digital LSI, IEEE Journal of Solid-State Circuits, ol.sc-20, No.1, February 1985 [31 Katsumi Ogiue, Masanori Okada, Shuuichi Miyaoka, Ikuro Masuda, Takahide Ikeda, Kenichi Tonomura: 13-ns, 500-mW, 64-kbit ECL RAM Using HI-BIC Technology, IEEE Journal of Solid-State Circuits, ol.sc-21, No.5, October C.olz, ~.~lossfeld: Collector Implanted Technology for Si Bipolar Devices, ESSDERC, paper, September 1986 [5] L.Blossfeld, C.olz: CIT 2 - eine vollsilizierte neue bipolare LSI-Technologie, IGT-Fachtagung Grossintegration, paper, March 1987

5 C4-88 Table 1: summary of the BIC device performance NPN N P parameter CIT 1 CIT 2 unit j emitter I size RE RB ex RC Cje Cjc hfe BEB BCE BCB ft Lg th BDS 1 Lg th BDS 2.5 * (40) * 5.0 pm ff ff GHz /urn /am v npn bipolar p-channel n- channel PECO Source Gate Drain Source Gate Drain Fig.l: cross section of the CIT 1 BIC device structures PECD PtSi npn Bipolar Poly Si Spacer PtSi Source n-channel Gate Drain Poly Si PtSi p-channel Source Gate Drain Fig.2: cross section of the CIT 2 BIC device structure