LATCH-UP FREE VLSI CMOS CIRCUITS CONSIDERING POWER-ON TRANSIENTS

Transcription

1 LATCH-UP FREE VLSI CMOS CIRCUITS CONSIDERING POWER-ON TRANSIENTS W. Reczek, J. Winnerl, W. Pribyl To cite this version: W. Reczek, J. Winnerl, W. Pribyl. LATCH-UP FREE VLSI CMOS CIRCUITS CONSIDER- ING POWER-ON TRANSIENTS. Journal de Physique Colloques, 1988, 49 (C4), pp.c4-49-c4-52. < /jphyscol: >. <jpa > HAL Id: jpa Submitted on 1 Jan 1988 HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

2 JOURNAL DE PHYSIQUE Colloque C4, supplement au n09, Tome 49, septembre 1988 LATCH-UP FREE VLSI CMOS CIRCUITS CONSIDERING POWER-ON TRANSIENTS W. RECZEK, J. WINNERL" and W. PRIBYL Siemens AG, Components Group, Otto-Hahn-Ring 6, Miinchen 83, F.R.G. "siemens AG, Corporate Research and Development, Otto-Hahn-Ring 6, Miinchen, F.R.G. R6sumB - I;e p&sent article se propose de fonmler les conditions d'apparition du latch-up a condition de ---On et d'en 6tablir les origines physiques, d'indiquer les tendances actuelles mttant de r&iw lracuit6 du prob1za-1~ au niveau de la concept+on des circuits et de faire un bilan des mesures penrnettant une meilleure protectlon des syst&nes a lr6gard de ce ph&e. Abstract - Pomr-on latch-up is depending on circuit design and technology. The use of an epilayer increases the latch-up hardness of conventional CMOS (LOGIC) while for n-well CMOS with VBB generator (DRAM) the latch-up suszeptibility is increased because of the capacitive voltage divider in the periphery and the high effective substrate shunt resistance. Therefore protection circuits provide latch-up free operation. 1 - INTRODUCTION The success of a CMUS technology in the micron and sdmicron range is strongly related to latch-up hardness. So far, mst latch-up investigation was done on simple four layer test struchxes, which gives an insight in the physics of the latch-up effect. For latch-up predictions the circuit environment is essential, especially for --on latch-up. The usefullness of technology and circuit measures for latch-up prevention considering power-on are discussed. 2 - LATCH-UP TEST STRUCTURE AND EQUIVATiENT CIRCUIT AT POWER-ON %he latch-up test structure Fig.la is identical to a CMOS inverter provided with an additional field oxide plysilicon gate. The total n+p+ spacing is 6p.m (X=Zp.m and Y=4p.m). Each diffusion of the test structure can be connected separately. Samples have been fatzricated in a 1p.m n-well CMOS technology. Besides the 'functional unitt,latch-u path, the enviromt of the latch-up path also has to VDD a) b) P T I - Fig.1: Latch-up test structure and equivalent circuit at --on. a.) Cross section of the test structure. b.) Fquivalent circuit of an n-we11 CNOS structure (DRAM) with the latch-up sensitive CMOS path, the cell area with cell plate generator and VBB generator /I/. Article published online by EDP Sciences and available at

3 C4-50 JOURNAL DE PHYSIQUE be considered. The conventional two transistor equivalent circuit is extended by elmts describing the envimnnmt. As an example, Fig.& shcws the equivalent circuit of an n-well CMOS structure (DRAM, /I/) with the latch-up sensitive CMOS path, the cell area with the cell plate generator and the on chip WE3 generator. 3 - LATCH-UP DURING POWER-ON Fig.3 shows the ptier-on behaviour of an n-11 CMOS structure with VBB generator. At the m- mat of per-on the substrate is floating because substrate bias can only be generated after a certain time delay. With floating substrate the effective substrate shunt resistance is nearly infinite. 'Iheefore, the substrate potential VBB is determined through a capacitive voltage divider by the supply voltage VDD (see Fig.&). VDD changes, especially the rise at --on, are coupld into the substrate by C (VBB-VDD) and buffered by C- (VBB-VSS). The rising VM) leads to a positive peak on VBB. The level of this peak determines whether latch-up is triggered (Fig.2~) or not (Fig.%). Fig. 2: --on of an n-well CMCXj circuit. a) msurenwt setup, b) VBB and WD without latch-up, c) VBB and VDD with latch-up CRITICAL CAPACITANCE RATIO FOR POWER-ON LATCH-UP The necessary ramp rate to trigger --on latch-up depends on the capacitances C and C-. Fig.& shows the critical ramp rate (CRR) dv/dt vs. C with VDD and C-as parameters. For high C. (Cc>lnF) the CRR is independent of C- (dv/dt*c = const. ). Decreasing C, a L value is found, *ere the structure is latch-up free even for infinite ramp rate RR. Ckn, decreases for increasing VDD, because for a given RR the charge built up by the displacement current increases with increasing final VDD level. Critical ramp rate CRR (%Us) A\~DD = 5 v vss X =2pm Y =4pm C-=l nf h Coupling capacitance C+ (nf) X =2pm Y =4um I I I 5 10 Capacitance ratio C-/C+ (-) - Fig. 3: ParnRr-on latch.-up. a. ) Critical ramp rate RR vs. C with parmter VDD b. ) minirmrm supply voltage VDD with infinite RR vs. ratio C-/&.

4 Fig.3b shows the mininnrm WD with infinite RR, which triggers-latch-up, vs. the ratio C-/L. Using the ratio C-/L as a variable, one single linear function describes the overall --on latch-up behaviow COMPARISON OF LOGIC AETD DRAM The rraxirrnrm allowable RR and final VDD level for latch-up fyes pmr-on of circuits with VBB generator is determined by the ratio of C-/C+. In the case of IGIC circuits a capacitance ratio L/C- of 1/3 results at pow~-on. Tkis ratio of 1/3 shows to be near the safe area. Additionally it has to be mentioned that in LOGIC circuits nomlly no VBB generator is used. The substrate is grounded to VSS. In the case or D m with cell plate bias (VDD or VDD/2) a typical capacitance ratio L/C-of 20 is fourad. L is mainly detennjned by the cell plate capacitance (also called L*). 4 - HOW TO AVOID POWER-ON LATCH-UP %e latch-up hardness of circuits can be inpromd by technology and circuit design (protection ci3xuits) TECHNOLOGY The use of an epilayer over highly doped substrate is well known to inprwe the static latchup hanhess. With gnnded substrate the critical current to initiate latch-up is increased by orders of magnitude /3/. But for circuits with VBB generator (especially DNaMs) the pmr-on latch-up hanlness is a main problan because of the incnxised effective substrate shunt resistance. The latch-up free regime for infinite RR in Fig.3b can not be knpd. For finite RR and a given C- the critical RR is even reduced by a factor of 2 with epi /3/. This is due to the higher current gain of the lateral parasitic bipolar transistor in the epi case. A ccanparison of the lateral bipolar transistor current gain for epi and nm epi is shown in Fig.4. Current gain Plat (-) Collector current lc (ma) -+ Fig. 4: Current gain of the lateral bipolar transistor vs. the collector current I, for epi and nonepi PROTECTION CIRCUIT In DFCMs the main part of C. is represented by C&=. A protection circuit reduces the effective C+ by disconnecting C&Z frran VDD or the plate voltage generator during --on (Fig.5). Fig.5b shows that the latch-up free regims is increased for a certain ratio C-/L so that no latch-up occurs.

5 JOURNAL DE PHYSIQUE Critical ramp rate C:RR (V/S) =)I 7- with switch h I Coupling capacitance C+ (nf) + Capacitance ratio C-/(C+ + C+) (-) + Fig.5: Paer-on latch-up with and without protection circuit. a.) Critical RR vs. C and b. ) minimum supply voltage VDD with infinite RR vs. ratio C-/C. 5 - CONCLUSION Besides the 'functional unit' latch-up path, wkich is represented by the latch-up test structure, the environment of this path also has to be considered. Tkis is of special importance when the pwsr-on latch-up hardness is investigated. Latch-up savety during per-on can be achieved by increasing C-/C+ or reducing VDD. For the case of a DRAM with VBB generator, the capacitance ratio C/C-of 20 is leading to a high risk of latch-up during pmr-on. Epi, a unique measure for static latch-up suppression can even lead to a reduction of --on latchup hardness in circuits with on-chip generated substrate bias. In this case it is necessary to use protection cirmi1~ to achieve p.er-on latch-up free circuits. ACKNOWLEDGEMENT This work is based on a project which has been supported by the Minister of Research and Wdmo1cqy of the Fecieral Republic of Gemmy under the support-no. NT For the contents the authors alone are responsible. REFERENCES /1/ RECZEK W., PhD.thesis, Munich, FRG (1988). /2/ MAZURE C., EZEK W., TAKACS D., WINNEIiL J.,to be published in IEEE ED (1988). /3/ TAKACS D., WINNER1; J., RECZEK W., IEDM Tech. Dig., Washington, M3, Decfmber(l985) 504.