MODELLING AND DIGITAL CONTROL DESIGN OF AN INTERLEAVED BOOST PFC CONVERTER

Transcription

1 MODELLING AND DIGITAL CONTROL DESIGN OF AN INTERLEAVED BOOST PFC CONVERTER ABSTRACT Carmen Cheng, Jiatai Zheng, Ying Feng School of Automation Science and Engineering, South China University of Technology 381 Wushan Road, Tianhe District, Guangzhou, P.R. China, The interleaving technique is a key player in the field of Power Factor Correction (PFC) converters in switchedmode power supplies (SMPS). As an effective improvement on the traditional topologies, it aids engineers in tackling the increasingly stringent power regulations concerning power factor and input harmonics. In this work, the interleaving structure is applied to the boost topology for the purpose of PFC. In order to improve the efficiency and stability of the converter, a digital PID controller is designed to show the greater robustness of the closed-loop system. Compared with the analogue controller, the digital controller has numerous advantages, such as higher level of integration, higher efficiency, smaller size, faster dynamic response, lower sensitivity to external influences and greater control flexibility. In order to obtain the regulation law of the digital controller, the small signal model for a two-channel interleaved boost PFC converter is discussed in this paper. The controller design is deduced for converter operation in continuous current mode (CCM), using the average current mode control (ACMC) scheme. By using a digital control chip (UCD 3138), a modified PI controller is embedded in the digital platform and the system performance is evaluated. The closed-loop system using the digital controller satisfy requirements of 99% Power Factor and less than 1% Total Harmonic Distortion (THD). The results of the experiment given in this paper for the entire power and control stages show the effectiveness of the proposed method. KEYWORDS: Interleaved Boost Converter, Power Factor Correction, Digital PI Controller.

2 1. INTRODUCTION Poor power quality, characterised by low power factor and high harmonic pollution, leads to inefficiencies and harmonics being fed back into the grid, ultimately giving rise to potential risks in the stability of the entire grid [1] [2] [3]. This growing urgency is reflected in the release of increasingly stringent regulations governing power quality, such as the international recommendations set out by IEEE519 and the national standard GB/T in China [4] [5] [6], which place particular emphasis on power factor and total harmonic distortion levels (THD). In order to keep up with these requirements, the power factor correction (PFC) technique plays an important role in improving power quality and meeting the current harmonic standards, which has become a primary topic in the power electronics industry. Compared with conventional PFC methods [7] [8] [9], use of the interleaving structure can decrease the ripple current effectively under both CCM (continuous conduction mode) and DCM (discontinuous conduction mode) for active power factor correction [1]. The input current can follow the sinusoidal line voltage automatically and the control loop can be simplified which aids in the controller design. As the conventional control method, analogue controllers may be affected by errors which cause them to fall short of the high precision control circuitry required in interleaved PFC applications. In more recent times, in order to further the study of interleaved PFC control, it is necessary to explore the implementation of digital control. The digital controller can achieve higher levels of integration, higher efficiency, smaller size, faster dynamic response, lower sensitivity to external influences and greater control flexibility, and as such, it has become a popular method in power electronics. With the development of high performance and low-cost digital ICs, they have attracted more attention for the various digital control strategies in multiphase topologies. For example, Sun shows the various algorithms that can be utilised for adequate current sharing between the current loops [11]. Digital sliding mode control was implemented for the converter in [12] however, the dynamic response was limited by high switching frequencies. DSP control utilising the 32-bit TMS32F2812 module with additional current sharing circuitry was demonstrated in [13] and exhibited higher frequency operation and greater flexibility. With newer ICs, further performance improvements can be realised and more complex algorithms can be explored. As an illustration, a two-channel interleaved boost PFC converter is utilized in this paper to demonstrate the application of digital controllers. In order to model the converter, the small signal state space model is analysed under CCM. Based on this model, a PI controller is designed which is implemented using a digital controller chip (UCD 3138) in a series of experiments. The efficiency and dynamic response of the closed-loop are given to show the effectiveness of the proposed method. 2. INTERLEAVED BOOST CONVERTER OPERATION PRINCIPLE The technique of interleaving the boost converter parallels two or more complete boost sections in lieu of one, effectively sharing input current which subsequently divides component stresses among more, and possibly smaller, components. Additionally, by feeding out of phase PWM signals to each of the switches, inductor current ripple can be drastically reduced and therefore allow the converter to accommodate much higher power densities. The most basic interleaved boost converter (and the converter under study) consists of two channels with the switches operating 18 out of phase. The states are shown in Figure 1 and the inductor waveforms (i L ), the switch states (S) of each channel and the combined input inductor current waveform (i in ) at high duty cycle (>5%) are shown in Figure 2.

3 a) Entire power stage circuit schematic b) State 1 (identical to state 3) c) State 2 d) State 4 Figure 1. Topological states of the basic interleaved boost converter. Figure 2. Timing diagrams for the basic interleaved boost converter at high duty cycle. 3. SMALL SIGNAL STATE SPACE MODELLING The control goal is to ensure that the input current follows the input voltage. At the same time, the output voltage should be stable in a certain amplitude range. In order to achieve this purpose, the modelling method for the interleaved PFC main circuit needs to first be discussed. The state equations of a continuous time-variant system can be written in compact matrix form as follows [7] [14] Kx (t) = Ax(t) + Bu(t) (1) y(t) = Cx(t) + Eu(t) (2)

4 where K, x(t), u(t) and y(t) are the quantity, state, independent input and dependent output vectors respectively, following the definitions shown in Figure 3. Figure 3. Simplified schematic of the interleaved boosts converter defining state variables. Circuit analysis techniques are used to obtain the differential equations for each state and are represented in matrix form. The weighted averages can then be combined to obtain the state matrices, A, B, C, and E over an entire switching cycle as follows A = A 1 d 1 + A 2 d 2 + A 3 d 3 + A 4 d 4 = A 1 (2D 1) + D(A 2 + A 4 ) B = B 1 d 1 + B 2 d 2 + B 3 d 3 + B 4 d 4 = B 1 (2D 1) + D(B 2 + B 4 ) C = C 1 d 1 + C 2 d 2 + C 3 d 3 + C 4 d 4 = C 1 (3) E = E 1 d 1 + E 2 d 2 + E 3 d 3 + E 4 d 4 = E 1 For the ideal case at high duty cycle, the matrices of (3) can be evaluated as (D 1) A = (D 1) [ (1 D) (1 D) 1 R ] 1 B = [ 1 ] (4) 1 C = [ 1 ] E = [ 1 ] (5) Combining (1), (2) and (3), the full large signal representation is formulated as (D 1) L i 1 (t) i L1 (t) 1 [ L ] [ i 2 (t)] = (D 1) [ i L2 (t)] + [ 1 C v c (t) [ (1 D) (1 D) 1 v c (t) R ] ] [ v in(t) ] (6) i g1 (t) 1 i L1 (t) [ i g2 (t)] = [ 1 ] [ i L2 (t)] + [ v o (t) 1 v c (t) ] [ v i L1 (t) in(t) ] = [ i L2 (t)] (7) v c (t) Small signal dynamics can be modelled by approximating the system about a quiescent operating point such that the small signal representation consists of both a steady state DC signal and small signal (AC) perturbations. Thus the DC state variables, including the duty cycle, are replaced as follows where the upper case letters represent the DC component and the hat notation represents AC variations

5 x = X + x y = Y + y u = U + u d = D + d (8) Using this approach, the product of the second order AC terms can be eliminated by adopting the assumption that these are small enough to be negligible in comparison to the remaining terms [7]. Thus, the small signal AC model of the basic interleaved converter is evaluated as (1 D) i L1(t) i L1 (t) K d 1 dt [ i L2 (t)] = (1 D) [ i L2 (t)] + [ 1 v c(t) [ (1 D) (1 D) 1 v c(t) R ] V C ] [ v g(t) ] + [ V C ] d (t) (I L1 + I L2 ) (9) 4. DIGITAL PID CONTROLLER DESIGN The selected control scheme utilises average current mode control in continuous conduction mode. Figure 4 shows a simplified dual loop block diagram for the digital controller under average current mode control (ACMC). Figure 4. Simplified block diagram of the digital control scheme. Only one current loop is shown for simplicity. The two current loops are identical and use the same input current reference, i ref. Further details are given in [15]. To design the two PI controllers PI v and PI i, the mathematical representations of both the current and voltage power stages (T i and T v ) are required, that is, the control duty to output transfer function y (s) from the small signal model. Since the bandwidth of the inner loop d (s) is significantly higher than the outer loop, inner current dynamics can be ignored when considering the voltage loop. Then the voltage power stage can be simplified significantly by reducing the order of the system from 2 to 1. This is one of the advantages of implementing current mode control [16]. Both power stage representations are obtained from the state-space model derived earlier as follows i L(s) d (s) = CV V o + 2I L (1 D) + or CLs 2 + L = T (1) i R s + 2(1 D)2 V o (s) 2(1 D) = I L (s) Cs + 1 = T v (11) R

6 Using the open loop representation of the entire system, a typical PI controller is designed to satisfy the control goals of power factor and THD. For the voltage loop, the non-linear PI gains are used based on the voltage error threshold. The control output of the voltage loop, u v, is used to generate the input current reference, given by 1 i ref = K m u v v in K vin ( v 2 ) (12) in,rms where K m is the multiplier gain determined by the minimum value of the input voltage and K vin is the input voltage divider gain required to scale the signal to accommodate the measurement range of the chip. The two current loops then process the reference signal through 3 major hardware function blocks including the digital PI controller and digital PWM (one for each channel). There are two kinds of digital control design methods. One follows continuous control system design and is then converted to a digital controller by the method of successive approximation. The other method designs the controller in the z-domain directly based on the analysis method of the discrete system. The bilinear transformation method is a kind of numerical approximation. It compresses the entire range on the frequency axis to between T and T, where T is the sampling period, in the s plane and z plane and 2 2 establishes a corresponding single value relationship, given by: { s = 2 T 1 z 1 1+z 1 z = 1+(T/2)s 1 (T/2)s (13) The transfer function of the analogue PI controller can be defined as G PI (s) = K p + T i s (14) then, by bilinear transformation, the digital transfer function is obtained as G PI (z) = (K Ti T p+ 2 )z+t i T 2 K p z 1 (15) where K p is the proportionality coefficient and T i is the integral coefficient. 5. EXPERIMENTAL STUDIES 5.1 Experimental Platform Set Up As shown in Figure 5, the digital control chip (UCD 3138) is integrated on a board consisting of the twochannel interleaved boost converter experimental platform. The board supplies four input signals to the chip: two current sense signals (i L ), one from each boost channel, output voltage (v o ), and input voltage (v in ) which form the current and voltage loop feedback signals and multiplier input respectively. The controller chip outputs consist of the two out of phase PWM signals fed to each switch. The design target for the interleaved converter with digital PI control is shown in Table 1. In order to show the performance of the converter under different load conditions, the efficiency of the converter is also tested.

7 Table 1. Performance indicators used for the interleaved boost converter. Input Voltage Range (V in ) Input Frequency (f s ) Output Bus Voltage (V o ) 9 ~ 264 VAC 45 ~ 65 Hz 39 VDC Power Factor (PF) >.99 Total Harmonic Distortion (THD) <1% Efficiency (η) >96% Sampling frequency (S) 16MHz Four configurations are analysed to produce a range of results from 9V, 11V, 22V and 264V RMS value and the experiment results are presented in the following section. K m 1/V in.rms 2 Digital controller V ref i ref d v o G v (s) - G i (s) G vd (s) K vin H i (s) H v (s) Input Output Interleaved Boost PFC main circuit Figure 5. Experimental platform and simplified block diagram of the digital control scheme.

8 5.2 Input Waveform and PF/THD Analysis Figures 6(a)-(b) show the input current and voltage waveforms for the basic interleaved boost converter. The results of the experiment show that the rectified current waveform is sinusoidal in shape, accurately follows the reference voltage and that there is no phase delay between the two signals. The exact THD and PF values under different input voltages are given in Table 2. a) Input voltage at 11V b) Input voltage at 22V Figure 6. Input current and voltage waveforms. Evidently, Table 2 shows that the experimental converter achieves the goals stated in Table 1 of PF levels greater than 99% and THD values lower than 1% under different load conditions. Specifically, harmonic distortion levels increase with increasing voltage proportionally. Table 2. Power Factor and THD values for the 4 tested configurations. Input Voltage (V) True Power Factor Total Harmonic Distortion % % % %

9 5.3 Input Voltage Boost Start-up Waveform and Dynamic Test Analysis Figure 7 shows the results of the soft start control algorithm where the voltage boost feature of the topology is achieved in the absence of overshoot over the entire tested range. The rise is linear at larger duty cycle. However, the settling time for the 9V configuration is longer than for 22V in this example. a) Input voltage at 9V b) Input voltage at 22V Figure 7. Converter output voltage at start-up. Figure 8 shows the input current and output voltage waveforms in response to changes in load. For Figure 8(a) the load was varied between 6% to maximum load and in (b) it was varied between 8% to maximum load. Under digital control, the signals quickly stabilize. a) Input voltage at 11V

10 b) Input voltage at 22V Figure 8. Dynamic load response of the converter. 5.4 Efficiency versus Load Analysis As shown in Figure 9, the efficiency of the converter at various loads is given. Efficiency is affected at lower load levels below 3 4%, since the higher input current accumulates in greater switch conduction and inductor resistance losses. For the 22V stage, the efficiency is 96.7% under full load, therefore 49.5W is lost due to conduction and heat losses. Figure 9. Converter efficiency with various loads at 11V and 22V. 5. CONCLUSION In this paper model analysis and digital control for an interleaved PFC converter based on the traditional boost topology are discussed. The two channel interleaved boost converter is modelled using the small-signal state space method and the digital control design based on the digital controller chip are introduced briefly. Experiments carried out with the digital controller chip show that the power factor and THD under different input voltages and load conditions can satisfy the design target and that the good start-up and dynamic performance shows the effectiveness of the proposed method.

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