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1 c 2012 IEEE. eronal ue of th materal permtted. ermon from IEEE mut be obtaned for all other ue, n any current or future meda, ncludn reprntn/republhn th materal for advertn or promotonal purpoe, creatn new collectve work, for reale or redtrbuton to erver or lt, or reue of any copyrhted component of th work n other work. do:

2 A Succeve Cancellaton Decoder ASIC for a 1024-bt olar Code n 180nm CMOS A. Mhra, A. J. Raymond, L. G. Amaru, G. Sark, C. Leroux,. Menerzhaen, A. Bur, and W. J. Gro elecommuncaton Crcut boratory, EFL, uanne, Swtzerland Department of Electrcal and Computer Enneern, McGll Unverty, Montréal, uébec, Canada IMS boratory, Inttut olytechnque de Bordeaux, Bordeaux, France Abtract h paper preent the frt ASIC mplementaton of a ucceve cancellaton (SC) decoder for polar code. he mplemented ASIC rele on a em-parallel archtecture where procen reource are reued to acheve ood hardware effcency. A peculatve decodn technque employed to ncreae the throuhput by 25% at the cot of very lmted added complexty. he reultn archtecture mplemented n a 180nm technoloy. he fabrcated chp can be clocked at 150 MHz and ue 183k ate. It wa verfed un an FGA tetn etup and provde reference for the true lcon complexty of SC decoder for polar code. I. INRODUCION olar code, ntroduced by Arıkan n [1], are a new cla of error-correctn code that provably acheve the capacty of ymmetrc bnary-nput dcrete memoryle channel. Recently, polar code have alo been extended to the addtve whte Gauan noe channel [2] and to other relevant channel [3]. An mportant property of polar code that the complexty of the encoder and of a ucceve cancellaton (SC) decoder cale only a O(N lo N) [1], where N = 2 n the code lenth. However, the caln behavor uually provde only lttle nformaton on the true lcon complexty of a correpondn crcut and the avalablty of hardware effcent VLSI archtecture for a new type of code key to demontrate the practcal relevance of thee new code. A frt tep toward th objectve ha been made n a number of recent publcaton that propoe dfferent mplementaton tratee for the decoder. he frt hh-level conderaton of a potental SC decoder mplementaton were already decrbed n [1]. ter, more hardware effcent equental archtecture were decrbed n [4], [5] and [6]. A comparon that how the uperorty of SC decodn over the alternatve belef propaaton alorthm at comparable complexty wa provded n [7], toether wth a em-parallel archtecture that further reduce complexty compared to [4]. Unfortunately, all of the above publcaton conder only the reter-tranfer level and provde no ASIC mplementaton. Outlne and Contrbuton: In th paper, we decrbe the frt ASIC mplementaton of a decoder for polar code. o th end, we frt ummarze the ucceve cancellaton decodn alorthm and hhlht the cheduln of computaton n the decodn proce. We alo decrbe the em-parallel decoder archtecture n Secton II. In Secton III, we propoe an archtectural modfcaton of the em-parallel decoder that mprove throuhput by 25% wthout notceable overhead and decrbe the crcut-level detal of the procen element. Fnally, ASIC mplementaton and meaurement reult are ummarzed n Secton IV. II. DECODING ALGORIHM AND ARCHIECURE In th ecton, we frt revew the SC decodn alorthm, then the em-parallel SC decoder archtecture of [7]. A. Alorthm Let the polar code under conderaton have lenth N and code rate k/n. Denote the bnary nput vector (u 0, u 1,.., u N 1 ) by u0 N 1. Only k element of u N 1 0 carry nformaton: the remann N k bt are fxed to 0 and are called the frozen bt. he frozen bt ndce are determned by the communcaton channel type and condton [8]. Both nformaton and frozen bt are encoded nto the codeword x0 N 1 = u0 N 1 G, where G the polar code enerator matrx. he codeword x0 N 1 ent over the communcaton channel. At the output of the channel, y0 N 1 receved and the correpondn lo-lkelhood rato (LLR) L N 1 0 are calculated. An SC decodn alorthm produce an etmate û of a bt u ven L N 1 0, the prevouly decoded bt û 1 0, and the frozen bt et. If u n the frozen bt et, then û = 0; otherwe, û decoded baed on the LLR of û (Lû ). A hown n (1), Lû a functon of L0 N 1 and û 1 0. he dependency of Lû on û 1 0 mpoe the equental decodn order û 0, û 1,..., û N 1. { û (L0 N 1, û 1 0, f Lû (L N 1 0 ) = 0, û0 1 ) 0 1, otherwe. B. Alorthm to Archtecture Mappn he SC decodn alorthm lead to a reular data dependency raph (DDG) [1]. In F. 1, the DDG for N = 8 depcted. Each computatonal node n the raph can operate ether on lkelhood rato, a propoed n [1], or drectly on LLR, a propoed n [4]. he latter yeld a conderable reducton n complexty at the cot of only a mnor deradaton n error-rate performance. here are two dfferent type of node: f and. he f-type node receve a nput two LLR (L a, L b ) and calculate an output LLR a L f (L a, L b ) = n(l a ) n(l b ) mn( L a, L b ). (2) (1)

3 F. 1. DDG of a SC polar decoder for a code of lenth N = 8. he -type node alo receve a nput two LLR (L a, L b ), n addton to a partal modulo-2 um ( ) of prevouly etmated bt (û ). In th cae, the output LLR L (û, L a, L b ) = L a ( 1)û + L b. (3) he computaton of Lû equvalent to a topolocal-order traveral of the raph tartn from L N 1 0 on the rht-hand de. Note that the maxmum-lenth path n the topolocalorder traveral of the raph not lo N, but 2N 2 due the data dependency of the -node on prevouly decoded bt û. Drectly mappn the computatonal node n the DDG to N lo N hardware procen element (E) lead to an omorphc mplementaton wth a crtcal path that pan 2N 2 E whch mpractcal and hardware neffcent. he lne archtecture [4] [5] reduce the number of E to N/2 by mean of teratve decompoton at the cot of 2N memory element (ME) whle mantann approxmately the ame decodn latency. However, the reular tructure of the DDG permt further harn of E, ncrean the utlzaton rate of E wth mnor latency penalte. o explot th opportunty, the em-parallel SC decoder [7] provde a tunable number ( < N/2) of E. he tme cheduln for a em-parallel SC decoder wth N = 8 and = 4 denoted by CC or n F. 3. he decodn latency for the em-parallel SC decoder wa 2N + N lo( N 4 ) and the memory requrement remaned the ame a that of the lne archtecture. C. Archtecture he archtecture decrbed n [7] dvde the em-parallel SC decoder nto four major unt: an array of E, the LLR memory, the partal-um update loc and the aocated torae reter, and the controller, a hown n F. 2. tonally, a read-only memory (ROM), mplemented a a lookup-table (LU), ued to tore the ndce of the frozen bt for a ven channel nal-to-noe rato, choen a per [8]. rocen Element: Wthout reource harn (.e., = N/2 E), the employed SC decoder archtecture etmate the bt û N 1 0 equentally, n 2N 2 clock cycle. he correpondn decodn chedule dentfed by CC or n F. 3. However, nce t wa hown n [7] that a mall uffcent to acheve 90% of the throuhput of a decoder wth N/2 E we ntantate only = 64 E for the choen code block ze of N = 2 10 ). Each E mplement both the f and functon n the LLR doman (2) and (3), un the n-and-mantude repreentaton. LLR Memory: he LLR memory allow the reue of ntermedate reult from E calculaton durn the decodn proce. Unlke [7], our LLR memory mplemented un reter, whch are connected to the E un a multplexer network. Snce each E ue two -bt value to calculate one -bt value, the reter are of ze. artal Sum: hrouhout the decodn proce, the procen element need partal um û,z of the etmated bt û to compute L. hee partal um are calculated throuh contnuou update of the tored û,z durn the decodn proce to yeld û,z = N 1 j=0 β(j, ) = B(, j) û j (β(j, ) δ(j,, z)) (4) 1 δ(j,, z) = (B( v 1, z) + B(v, j)), v=0 where B(, j) = j 2 mod 2, and where β(j, ) and δ(j,, z) are mak that ndcate f û j contrbute to û,z or not. he operator denote the bnary product, and δ( ) = 1 when = 0. Note that th expreon already take nto account the tme multplexn ntroduced n [7], whch reduce the amount of memory needed for the partal um from O(N lo N) to O(N). he hardware for the update correpond to (N 1) reter and a mall amount of combnatonal loc n front of each partal um torae element, a llutrated n F. 2. h loc compute β( )δ( ), wth and z ben the hardwred ndce of û,z. If any of thoe block yeld true for a ven decoded bt, û added ( ) to the current content of the correpondn torae element. Controller: he controller coordnate the decodn proce wth three tate counter: the currently decoded bt ndex, the current tae ndex, and the porton of a tae p ben proceed, 0 p < 2. he bt ndex mplemented un a equental counter ncremented whenever reache 0. he tae number a functon of both and p : when p 2, and are updated. Becaue ome temporary computaton are tll avalable n the LLR memory, not all tae have to be evaluated when decodn a bt. Specfcally, et to the ndex of the frt bt equal to 1 n the bnary repreentaton of the updated, or to n 1 f ha wrapped around N 1. We notce that tae requre 2 E computaton. Due to the tme harn of only E th requre 2 clock cycle that are counted by p. In addton, the controller n chare of electn the approprate nput to the E, electn the rht functon to perform, and electn the proper memory locaton (LLR and

4 CN CN LOAD DEC p CN p Controller p p L U * L U Wrte Wrte LLRn Wrte LLR Mem W W DECODER artal Sum * 2* LLRout E 0 E0 f E1 f E 1 f E Array F or G LU p LU frz frz û F. 2. olar decoder hh-level archtecture partal um) to update. hee nal are calculated from,, and p un mall LU, a ndcated n F. 2. III. ARCHIECURAL IMROVEMS A. Concurrent Decodn n Stae 0 In order to mprove the throuhput of the decoder, the archtecture modfed to reduce the number of cycle requred to decode one codeword by N/2. he mprovement acheved by decodn two bt at a tme whenever the decoder n the lat tae ( = 0), whch poble by explotn the fact that two ubequent û are obtaned from f and node that take the ame nput LLR. Unfortunately, the -node need the output of the precedn f node a t û 0,z nput. herefore the -node output cannot be computed before the f node ouput avalable. he em-parallel archtecture n [7] compute the -node n the clock cycle after the f-node. In our archtecture, t poble to compute both node output n the ame cycle. o th end, the two poble -node output are calculated peculatvely whle the output of f calculated. he correct -node output then elected wth a nelble addtonal combnatonal delay. F. 3 how an example of the new, hortened chedule of f- and -node for concurrent decodn of two bt n cae of N = 8 and = 4, denoted CC conc. Overall the number of cycle for decodn reduced by N/2. In term of area, t hould be noted that only one of the procen element mut be able to perform th concurrent decodn. Hence, the ncreae n lcon area hardly notceable. However, nce two bt are decoded concurrently, both have to be condered alo n the û memory update loc. h extra loc render the correpondn hardware lhtly more complex: the ncreae n total area due to th chane wa only 1.62%. We note that th peculatve approach mlar to the one preented n [6]; however, t appled to a very dfferent baelne archtecture and much mpler nce t apple only to one tae n the decoder. Furthermore, t ental almot no addtonal hardware. B. Optmzed E Implementaton he propoed archtecture, ued by all E, mprove upon the E archtecture n [7], whch mere both functon f and n a nle E and thu hare a comparator and an XOR ate between the two functon. he LLR are tored n n-and-mantude form. he value of n(l f ) ven by n(l a ) n(l b ), wherea L f mn( L a, L b ), a hown n (2) and (3). he E archtecture n [7] calculate L by convertn mn( L a, L b ) to two complement repreentaton, and addn t to max( L a, L b ). he hardware for th operaton ha a lon carry path throuh the mantude comparator, the two complement converon block (an adder), and the adder. We note that L ha three poble mantude, namely ( L a L b ), ( L b L a ), and ( L a + L b ). he mprovement n the propoed archtecture come from calculatn all the poble value of L multaneouly n n-and-mantude form; electn the correct output baed on û, n(l a ), and n(l b ); and fnally aturatn a requred. he chane marked a E Mod n F. 4. he value of n(l ) ven by û n(l a ) when L a > L b, and n(l b ) otherwe. Compared to the propoal n [7], th optmzed archtecture reult n 50% reducton of the delay throuh the E wth an ncreae of 30% n t area. However, nce the E only make up 8.5% of the total core area (for = 64), the overall mpact mall and the area-delay product of the crcut mprove nfcantly. Furthermore, a pecal E named E 0 n F. 2 ntroduced, whch compute two decoded bt at a tme a decrbed n Secton III-A. E 0 ha an addtonal node output for concurrent decodn, whch ued n tae 0, a hown n F. 3. We note that E 0 doe not replcate a full node but hare the peculatve computaton of the normal E. he mplementaton ue 8 addtonal 2-nput MUX a compared to normal E. E 0 alo functon a a normal E when ued n tae 1 and 2. A a reult, E 0 44% larer than the

5 F. 3. Schedule for ornal and mproved em-parallel SC decoder. F. 5. Mcrophotoraph of the SC olar Decoder chp. n() n() n() n() û F functon COM Compab Shared n(f) Compab u Sat E Mod n() G functon f/ F Output G Crtcal ath ABLE I SUMMARY OF MEASURED RESULS FOR SC OLAR DECODER WIH N = 1024, k = 512, = 64, AND = 5 echnoloy 180 nm Core area 1.71 mm 2 Chp area 1.72 mm 2 Gate count 183,637 Frequency hrouhput Voltae ower Enery effcency 150 MHz 49 Mbp 1.3 V 67 mw 1.37 nj/bt F. 4. RL archtecture of a tandard E other E, but nce th chane only affect a nle E n the entre den, the mpact on total area very mall. he delay throuh E 0 vrtually the ame a that of the other E. IV. IMLEMAION RESULS AND MEASUREMS h ASIC, mplemented n the 180nm proce, wa bult wth N = 1024, = 64, and a code rate of 1/2. Each LLR value tored un = 5 bt n n-and-mantude form. Synopy Den Compler and Cadence SoC Encounter were ued for ynthe and layout, repectvely. he crtcal path of the den ornate from the controller, oe throuh the LLR memory, a E and back to the LLR and partal um memore. he layout mple, wth power ral on the perphery and four addtonal par of vertcal trpe to dtrbute the core power wthout much drop. Functonal tetn of the chp wa done by connectn the chp to an FGA board whch uppled the clock and the tmul for each cycle, and recorded the repone. he maxmum acheved frequency 150 MHz n th etup. he meaurement reult are hown n able I. A mcroraph of the chp hown n F. 5, n whch the E, controller and partal um memory are marked; whle the LLR memory account for the remann, unmarked area. V. CONCLUSION olar code are an nteretn canddate for error correcton n future telecommuncaton ytem. he lcon complexty of a ucceve cancellaton (SC) decoder chp for a code block ze of 1024 bt 183k ate, reultn n 1.72 mm 2 n a 180 nm technoloy. he correpondn throuhput 49 Mbp. he key concept for the hardware effcent mplementaton of a SC decoder for polar code are the emparallel archtecture propoed n [7], whch make the lcon complexty feable, and a concurrent decodn technque to ncreae the throuhput by 25% wth nelble addtonal complexty. On top of that, an optmzed mplementaton of the procen element (E) mportant to acheve a hh operatn frequency, a the crtcal path pa throuh the E. REFERCES [1] E. Arkan, Channel olarzaton: A Method for Contructn Capacty- Achevn Code for Symmetrc Bnary-Input Memoryle Channel, IEEE ran. Inf. heory, vol. 55, no. 7, pp , July [2] E. Abbe and A. Barron, olar codn cheme for the AWGN channel, n Informaton heory roceedn (ISI), 2011 IEEE Internatonal Sympoum on, au , pp [3] E. Saolu, E. elatar, and E. Arkan, olarzaton for arbtrary dcrete memoryle channel, n Informaton heory Workhop, IW IEEE, Oct. 2009, pp [4] C. Leroux, I. al, A. Vardy, and W. J. Gro, Hardware archtecture for ucceve cancellaton decodn of polar code, n roc. IEEE Int Acoutc, Speech and Snal rocen (ICASS) Conf, 2011, pp [5] C. Leroux, A. J. Raymond, G. Sark, I. al, A. Vardy, and W. J Gro, Hardware mplementaton of ucceve cancellaton decoder for polar code, Journal of Snal rocen Sytem, vol. 69, no. 3, pp , December [6] Chuan Zhan, Bo Yuan, and Kehab K. arh, Reduced-latency SC polar decoder archtecture, n Communcaton, ICC 12. IEEE Internatonal Conference on, 2012, pp [7] C. Leroux, A. J. Raymond, G. Sark, and W. J. Gro, A em-parallel ucceve-cancellaton decoder for polar code, o appear n IEEE ranacton on Snal rocen. [8] I. al and A. Vardy, How to contruct polar code, ubmtted to IEEE ran. Inf. heory, avalable onlne a arxv: v2, 2011.