Configurable K-best MIMO Detector Architecture

Transcription

1 ISCCSP 008, Malta, 114 March Confgurable Kbet MIMO Detector Archtecture Ramn SharatYazd, Tad Kwanewk Department of Electronc Carleton Unverty Ottawa, Canada Emal: {ryazd, Abtract In MIMO communcaton ytem, Kbet decodng algorthm acheve near optmal performance wth reduced complexty. Smulaton reult how that a confgurable MIMO detector can mprove ytem performance over a wde range of operatng condton. In th paper we preent a novel confgurable archtecture for mplementaton of Kbet algorthm. The propoed archtecture fully parallel and can upport QPSK, 16QAM and 64QAM modulaton cheme for a range of K value. I. INTRODUCTION Multplenput multpleoutput (MIMO) communcaton ytem beneft from multpath propagaton to mprove the overall bt error rato (BER) and data rate n the communcaton lnk [1]. In a typcal MIMO communcaton ytem comprng N t tranmtter and N r recever antenna, each of the N r recever receve both lneofght and reflected propagaton component from each of the N t tranmtter. The role of the MIMO detector to ue the receved gnal at each of the N r recever antenna and to recover the tranmtted ymbol []. Maxmumlkelhood () detector the optmum detecton algorthm n MIMO channel. Due to hgh level of computatonal complexty n detector, lattcebaed decodng algorthm, uch a the Kbet decodng algorthm have been propoed. The degn of low complexty MIMO detector that are flexble n term of number of upported antenna and modulaton type a challengng tak. There alo a need for MIMO detector that are able to dynamcally adapt to the requrement of channel and tranmon condton. In a Kbet MIMO detector throughput, latency and BER are related to K, whch a fxed detector parameter. In th paper, we wll dcu the need for Kbet MIMO detector that can adaptvely change K to mprove ytem performance. We wll later ntroduce a confgurable VLSI archtecture for mplementaton of Kbet decodng algorthm. The propoed archtecture upport QPSK, 16QAM and 64 QAM modulaton cheme wth the ablty to have dfferent modulaton cheme on dfferent tranmttng antenna. The ret of the paper organzed a follow: Secton II provde an ntroducton to the MIMO channel model and the Kbet detecton algorthm. The need for a confgurable Kbet archtecture wll be dcued n ecton III. In ecton IV, the propoed Kbet archtecture wll be preented and fnally n ecton V, the mplementaton reult for a CMOS 0.18 µm target technology are dcued. Fnally, the concluon are drawn n ecton V. II. DETECTION IN MIMO CHANNELS A. MIMO Channel Model In a MIMO ytem wth N t tranmtter and N r recever antenna (N t N r ), the channel model can be decrbed a: y c = Hcc n (1) c Where y c the N r x1 vector of receved ymbol, H c = [h j ] the N r x N t equvalent flatfadng channel matrx, c = [ 1,, Nt ] T an N t x1 vector of tranmtted ymbol. The N r x1 vector n c repreent the thermal noe a ndependent dentcal dtrbuted (..d) addtve complex Gauan noe at the recever wth zero mean and varance σ. The tranmt vector c correpond to complex contellaton Λ c contanng p c contellaton pont. The tak of MIMO detector to recover c from y c by olvng (1). It poble to tranform the N t dmenonal complex equaton (1) to an equvalent N t dmenonal realvalued repreentaton () [3]. The real operaton reduce the complexty of detecton nce the number of chldren node per parent node n a realvalued contellaton (log p c ) become maller than complexbaed contellaton (p c ). The entre of () are defned by realvalued ampltude modulated contellaton pont Λ r. { c} { y } { Hc} I{ Hc} { H } R{ H } { c} { } { nc} { } nc R y R R R () = I c I c c I c I Equaton () can be further mplfed n the form of the realvalued channel equaton (3). y = H n (3) B. Kbet Detecton The Maxmum Lkelhood () detector n hardoutput detector olve the followng equaton = arg mn y H (4) Followng tandard mplfcaton by applyng QR decompoton on channel matrx H [3], [4] we can further mplfy (1) and () to obtan (5): = arg mn y R q (5) /08/$5.00 c 008 IEEE Authorzed lcened ue lmted to: Carleton Unverty. Downloaded on June, 009 at 11:11 from IEEE plore. Retrcton apply.

2 1566 ISCCSP 008, Malta, 114 March 008 uch that and H = QR (6) H y q = Q y (7) expandng vector norm n (5) yeld N t N t = arg mn y q R j = 1 j = tartng from =N t, (8) can be olved recurvely a follow: where and T ( P ) = T 1( P 1) e ( P ) T ( P ) = 0 N t 1 N t 1 ( > 1 1 j (8) (9) T P ) T ( P ) (10) e (P ) = y q Nt j= R j j (11) In (9)(11), P = [, 1,, Nt ] T known a partal ymbol vector [4]. Ung the above mplfcaton, the orgnal optmzaton problem () can be recurvely olved by applyng an teratve tree earch methodology. The cot functon of the reultng optmzaton problem T (P ), whch known a Partal Eucldean Dtance (PED) [7]. In Kbet algorthm a breadthfrt tree earch conducted to earch for oluton of (8).e. the detector vt all blng of a node before t proceed to the next level. Intead of expandng every node at each layer of the tree, we only keep the bet K node that have the mallet accumulated PED. After completng tree earch, we wll have K leave wth the mallet PED. Each path n the tree correpond to a gnal vector. The path wth mallet PED the detecton reult. The Kbet can guarantee a fxed throughput and ha BER performance that cloe to detector. It alo poble that each of the tranmttng antenna ue dfferent modulaton cheme. III. MIMO CHANNEL VARIATION In a MIMO wrele ytem, a the wrele channel condton and the noe level change, the recever etmate the channel parameter and gnal to noe rato (SNR) n order to optmze detecton proce. In th ecton we conder two dfferent cenaro for channel varaton and wll analyze the effect of parameter K n each of thee cae. Fg. 1 how the mulated BER n a Kbet MIMO detector for two dfferent channel condton. The aumpton here that the SNR reman unchanged. We aume the detector ntally operatng at pont 1. Due to channel varaton, the operatng pont of detector move to pont and a a reult BER ncreaed. It poble to mprove BER by ncreang K and move operatng pont from pont to pont 3. The drawback of ncreang K n a Kbet detector that throughput wll be decreaed. In Fg., t aumed that the applcaton requre a fxed BER. Due to varaton n SNR, the operatng pont move from pont 1 to pont and a a reult the BER uffer, n order to mantan the requred level of BER, detector hould ncreae the K parameter at the expene of throughput. The econd cenaro depcted n th fgure related to the tuaton where channel condton and SNR level have not changed but due to a change n applcaton, recever could mprove the BER performance by ncreang K (pont 1 to 4). We can conclude that n a Kbet MIMO detector, t poble to adjut detecton parameter to mprove performance under dfferent operatng condton. In the next ecton, we propoe a VLSI archtecture that atfe th need. BER 10 1 ch1 K= 3 ch K= 3 ch K= SNR[dB] Fgure 1. Effect of K and channel varaton on BER performance BER 10 1 K = K = SNR[dB] Fgure. Effect of K and SNR on BER performance IV. CONFIGURABLE KBEST ARCHITECTURE The ppelned archtecture [5] for mplementaton of Kbet algorthm compoed of N t proceng element (PE) a hown n Fg.3. In th archtecture each PE aocated wth one level of a realvalued earch tree. The th PE receve K data vector from the precedng proceng element (PE (1)). The entre of the data vector contan the prevou vector ymbol of the admble node and the aocated PED. The tak of the PE to expand each of the K parent node to all ther chldren node, calculate the aocated PED for each chldren and to dentfy a et of K chldren whch have the Authorzed lcened ue lmted to: Carleton Unverty. Downloaded on June, 009 at 11:11 from IEEE plore. Retrcton apply.

3 ISCCSP 008, Malta, 114 March lowet accumulated PED and pa on the relevant nformaton to the next PE. Fg. 4 how the archtecture of the propoed PE block. All canddate vector ymbol and ther aocated PED (T ) are tored n the Data Buffer block. Each PED value from prevou level generate up to 8 new PED value dependng on the type of modulaton cheme (64QAM, 16QAM or QPSK). The PED Computaton block (Fg. 5) compute the PED of all aocated chldren of the parent node. Th block degned n a way that t alway calculate all the aocated PED conderng 64QAM modulaton. The contellaton et n 16 QAM (({3,1,1,3}) and QPSK ({1,1}) modulaton can be condered a a ubet of contellaton et n 64QAM ({7,5, 3,1,1,3,5,7}) modulaton. In cae of QPSK and 16QAM modulaton a et of multplexer mak the value of unued PED and replace them wth the maxmum poble value. The maxmum value depend on the number of data bt n the archtecture; for a 16bt fxed pont ytem th value would be (0xFFFF). Th force the ort8 block to place the aocated value for the maked PED at the end of the orted queue and eventually they wll be puhed down the ortng queue and have no effect n the fnal reult. The role of the ortng block n th archtecture to ort all the generated PED and elect the mallet K PED. The mot challengng apect of the degn of a ortng block to mnmze the number of vertcal logc level n the archtecture. In mplementng the PE block we are partcularly ntereted n ortng network that can be confgured to upport a varable number of nput entre (8 to 18). Sortng algorthm can be dvded n to two man clae: parallel and eral. In parallel ortng all the value to be orted are proceed multaneouly n an nterconnect network where n eral ortng the value arrve erally to the ortng crcut n uch a way that the new value to be orted nerted n an already orted lt. The drawback of the eral ortng crcut the extra clock cycle requred to proce each new value. Parallelbaed ortng archtecture are fater than eral ortng archtecture but requre more area. Table I compare the complexty of a number of parallel ortng algorthm for a 18 (16 8) nput ortng network. TABLE I. COMPLEITY OF SORTING ALGORITHMS Sortng algorthm Number of comparator Number of vertcal comparator layer Parallel Batcher oddeven Parallel Btonc Parallel Bubble Parallel Batcher oddeven wth feedback regter Ppelned Batcher oddeven wth feedback regter The Batcher oddeven mergeort algorthm [6] merge two orted equence nto one orted equence. The complexty and number of vertcal layer n th algorthm comparatvely lower than other parallel ortng algorthm. In PE block, every clock cycle eght new PED value are computed. We can ue th property to further mplfy the archtecture of the ortng network by ung a et of feedback regter to tore the K value of the prevou comparon and reduce the ze of ortng network to K. In order to further reduce the complexty, we propoed a ppelned mplementaton. Fgure 3. Ppelned archtecture for Kbet detector Authorzed lcened ue lmted to: Carleton Unverty. Downloaded on June, 009 at 11:11 from IEEE plore. Retrcton apply.

4 1568 ISCCSP 008, Malta, 114 March 008 Fgure 4. Archtecture of PE block 8 7 T1 R8 R7 R yq (7) (5) (5) (7) R x x x x Fgure 5. Archtecture of PED computaton block T(=7) T(=5) T(=5) T(=7) Fg. 4 how the archtecture of the propoed ppelned ortng block. The bac dea behnd the ppelned ortng archtecture that a the new PED value arrve, they are frt orted n ort8 block and then ether enter the ppelne regter or go drectly to the merge block and are merged wth the prevouly tored PED. The role of the merge block to merge two orted equence nto one orted output equence. A an example, merge16 block merge two equence each compred of eght element nto a xteen element equence [7]. In Fg.6, the archtecture of merge16 block depcted. The bac buldng block n th archtecture a mple compare/exchange (cmpx) cell. The two nput enterng the cmpx cell are compared, the mallet connected to l and the larget connected to h output.one of our man goal n th archtecture to be able to ort equence wth varable length. In a ppelned archtecture th can be accomplhed wth the help of multplexer a hown n Fg. 4. V. IMPLEMENTATION RESULTS Fgure 6. Archtecture of merge16 block Baed on the propoed archtecture, a 4 4 (QPSK/16 QAM/64QAM) MIMO detector ha been degned, ynthezed and mapped to a 0.18 µm CMOS tandard cell lbrary. After ynthe and mappng, a clock frequency of f clk = 47 MHz ha been acheved wth a logc complexty of 300K equvalent gate (equvalent gate number calculated by dvdng total area by the area of a twonput drve1 NAND gate). All the arthmetc computaton are baed on 16bt fxedpont number. Data buffer have been mplemented ung regter to ncreae the peed at the expene of lcon area. The latency of each PE cell K cycle and the overall latency of the archtecture 14K1 cycle. Throughput of the detector (f clk.n t.log p c )/K Mbp. Drect comparon of the propoed archtecture wth prevouly reported archtecture tend to be qute dffcult nce prevouly publhed archtecture focu on mplementaton and optmzaton of a detecton algorthm for a pecfc K value and modulaton cheme. Our oluton, on the other hand, ha been degned wth the am of upportng varable K a well a three dfferent modulaton cheme for each antenna and a a reult there an aocated hardware cot for lcon area and tmng. The ze of the data bu can gnfcantly affect the area. In majorty of the prevouly reported work, th parameter mng and t make Authorzed lcened ue lmted to: Carleton Unverty. Downloaded on June, 009 at 11:11 from IEEE plore. Retrcton apply.

5 ISCCSP 008, Malta, 114 March comparon between archtecture even more dffcult. In order to be able to compare core area mplemented n dfferent CMOS technologe, one oluton would be to convert all the reported core area to equvalent gate number. Table I. how performance fgure of the propoed archtecture and compare them wth ome of the reported archtecture for Kbet algorthm. ACKNOWLEDGMENT The author would lke to thank Altera Corporaton, Ontaro Centre of Excellence (OCE), and Natural Scence and Engneerng Reearch Councl (NSERC) for ther fnancal upport. Technology acce from Canadan Mcroelectronc Corporaton (CMC) alo apprecated. TABLE II. COMPRARISON OF ASIC IMPLEMENTATION RESULTS Reference [8] [9] [9] Th work K ~ 16 Number of Antenna Modulaton 16QAM 16QAM 16 QAM 64QAM, 16QAM, QPSK Tech [µm] 0.35 µm 0.5 µm 0.5 µm 0.18 µm Equvalent 91 K 68 K 110 K 300 K gate number Clock 100 MHz 13 MHz 5 MHz 47 MHz Frequency Latency K1 (15 ~ 5) (cycle) Throughput 53 Mbp 44 Mbp 83 Mbp 1 ~ 564 Mbp VI. CONCLUSION Degnng a multmode flexble MIMO detector repreent a challengng tak for next generaton wrele recever. In a K bet decoder we can acheve better performance under dfferent channel condton by changng K parameter. In th paper a confgurable VLSI archtecture for Kbet decodng algorthm ha been preented. The propoed archtecture ealy confgurable for dfferent modulaton cheme (QPSK, 16 QAM and 64QAM) and K value (1~16). REFERENCES [1] G. J. Fochn and M. J. Gan, On lmt of wrele communcaton n a fadng envronment when ung multple antenna, Wrele Peronal Communcaton, vol. 6, pp , March [] D. Gebert, M. Shaf, D. Shu, P. J. Smth, and A. Nagub, From theory to practce: An overvew of MIMO pacetme coded wrele ytem, IEEE Journal on Selected Area n Communcaton, vol. 1, pp , Aprl 003. [3] M. O. Damen, H. El Gamal, and G. Care, On maxmum lkelhood detecton and the earch for the cloet lattce pont, IEEE Tran. Informaton Theory, vol. 49, No. 10, pp , Oct [4] A. Burg, M. Borgmann, M. Wenk, M. Zellweger, W. Fchtner, and H. Bolcke, VLSI mplementaton of MIMO detector ung the phere decodng algorthm, IEEE Journal of SoldState Crcut, vol. 40. Iue 7, pp , July 005. [5] K. Wong, C. Tu, R. Cheng, and W. Mow, A VLSI archtecture of a K bet lattce decodng algorthm for MIMO channel, n Proc. IEEE Int. Symp. On Crcut and Sytem (ISCAS), vol. 3, May 00, pp [6] K. E. Batcher, Sortng network and ther applcaton, Proc. AFIPS Sprng Jont Comput. Conference, 1968, pp [7] K. Parh, VLSI dgtal gnal proceng ytem: degn and mplementaton, John wley & Son, 1999, pp [8] Z. Guo and P. Nlon, A VLSI archtecture for the SchnorrEuchner decoder for MIMO ytem, Proc. IEEE CAS Sympoum on Emergng Technologe, June 004, pp [9] M. Wenk, M. Zellweger, A. Burg, N. Felber, and W. Fchtner, KBet MIMO detecton VLSI archtecture achevng up to 44 Mbp, n Proc. IEEE Int. Symp. on Crcut and Sytem (ISCAS)006, 006 pp Authorzed lcened ue lmted to: Carleton Unverty. Downloaded on June, 009 at 11:11 from IEEE plore. Retrcton apply.