Improved single-phase PLL structure with DC-SOGI block on FPGA board implementation

Transcription

1 Orgnal reearch paper UDC :6.38 DOI 0.75/IJEEC70053R COBISS.RS-ID Improved ngle-phae PLL tructure wth DC-SOGI block on FPGA board mplementaton Mlca Rtovć Krtć, Slobodan Lubura, Tatjana Nkolć Faculty of Electrcal Engneerng, Unverty of Eat Sarajevo, Eat Sarajevo, Bona and Herzegovna Faculty of Electronc Engneerng, Unverty of Nš, Nš, Serba Abtract - Synchronzaton block whch ued a a part of photovoltac (PV) nverter control tructure ha a key mpact on connectng nverter wth grd. One of the mot mportant parameter n the pont of connecton PV nverter and grd phae angle between grd voltage and nverter current. Th angle determne the energy tranfer between nverter and grd. Synchronzaton algorthm have developed for very long tme. At frt, they were baed on zero crong grd voltage detecton, whle today complexed ynchronzaton algorthm mplemented on hgh performance dgtal board have been ued. One of thee ynchronzaton tructure Phae Locked Loop PLL. In th paper mplementaton of mproved PLL tructure preented. Th mproved tructure pecal whle t ha poblty of grd parameter etmaton even f grd voltage ha noe or DC offet. Th DC offet from the grd n PLL tructure uually entered va meaurement and A/D converon proceor or may be generated due to temporary ytem fault. Appearance of DC offet n meaured grd voltage on the one hand prevent any etmaton proce of grd parameter and on the other hand alo degrade reference ne gnal at the output of PLL tructure n PV nverter. Th mproved tructure degned n dgtal form and mplemented on FPGA dgtal board and expermental reult of th mplementaton are preented. Obtaned expermental reult how that the propoed PLL tructure uccefully olve mportant ue uch preence of DC offet n meaured grd voltage. Keyword - SRF-PLL; two-phae generator; DC-SOGI block; DC-offet; FPGA mplementaton. I. INTRODUCTION Synchronzaton block neceary part of a control tructure when PV nverter connect wth grd, and t ued to adjut phae angle between grd voltage and nverter current. One of the mot wdely ued ynchronzaton tructure Phae Locked Loop PLL. In th paper analyzed mplementaton of Synchronou Reference Frame Phae Locked Loop SRF-PLL tructure wth DC-SOGI (Second Order Generalzed Integrator wth DC offet elmnaton) ued for PV nverter ynchronzaton, on FPGA board. Th mproved PLL tructure preented n [], and pecfc whle DC-SOGI block whch phae detector ha poblty of DC offet and noe elmnaton, o the whole tructure can etmate grd parameter even f the grd voltage contamnated by noe or harmonc. Thank to t mple realzaton, robutne and effcency, SRF-PLL probably the mot popular tructure for obtanng nformaton on grd voltage parameter. In Fg. hown a block dagram of th ngle-phae PLL tructure. The SRF block work a a phae detector, whch tranform tatonary voltage component (αβ) nto DC component (dq) of the Th paper a reved and expanded veron of the paper preented at the XVI Internatonal Sympoum INFOTEH-JAHORINA 07 [9]. Corepondence to: M. Rtovć Krtć (mlca.rtovc@etf.una.r.ba) ynchronou reference ytem ung Park tranformaton. Th block adaptve by the etmated phae angle, therefore output of PLL tructure ha uch mpact on ampltude of the vector v d and v q, o that the gnal v q reduced to zero. At the ame tme, the value of v d converge to the ampltude of the grd voltage. The PI controller ued a a loop flter. In addton, n order to make the SRF-PLL tructure robut to grd ampltude change, the gnal v q dvded by the etmated ampltude of the grd gnal, whch can be obtaned by flterng the v d gnal ung the low pa flter. Fgure. SOGI-PLL tructure Th tructure very popular at three-phae ytem due to t effcency and mplcty. However, n the cae of nglephae ytem, due to the lack of ndependent nput gnal, uch a n three-phae ytem, t applcaton more complcated. 53

2 Mlca Rtovć Krtć et al. Therefore, ome method are propoed for generatng an orthogonal gnal ung nput gnal n the ngle phae ytem o the applcaton of the Phae Detector (PD) block poble. In the lterature, a large number of dfferent PD block are known, but actualy ther realzaton baed on SOGI and nvere Park OSG block, o thee tructure are alo called SOGI PLL and Park PLL tructure [-4]. They have acceptable performance even under condton of varyng frequency of grd voltage or n the preence of harmonc and noe, whch are the mot common nput gnal dturbance. However, f the nput gnal ha a DC offet or an aymmetry, the phae dfference at the output of the two-phae generator not exactly π/, o an error n the etmaton of grd parameter wll occur. In [] detaly decrbed a DC-SOGI block that ha the poblty to elmnate a DC offet or noe f they ext at the nput of SRF-PLL tructure. Modfyng a two-phae generator, addng a control loop to the generator telf, generaton of quadrature gnal and elmnaton of DC offet wthout the addton of any flter enabled. The propoed generator robut and ha a fat repone to change n grd parameter. It alo effectvely elmnate noe n the meaured grd voltage. Vgrd m () V () 3 Vg ( ) ( k) k Vα αβ DC-SOGI Vβ dq 0 Vq Vd PI ωet ωnom Fgure a. Block dagram of ngle-phae SRF-PLL tructure r(t) e(t) z(t) α () v α (t) v β (t) β () θet (4) II. DC-SOGI BLOCK A t already mentoned, DC-SOGI block a part of the SRF-PLL tructure. The phae detector n the SRF-PLL tructure [-4] the SRF block (αβ/dq block - Fg. a). At the nput of the SRF block, t neceary to have two gnal phae hfted by π/, v α(t) and v β(t), whch are the output gnal of the SOGI block. The SOGI block cont of two econd-order flter, α() whch bandpa flter and the low-pa flter β(), o that both can effectvely upre hghfrequency noe, but not a DC offet f t appear n the meaured grd gnal. The tranfer functon of thee flter n a contnou doman are gven by equaton () and (). () () For the operaton of a two-phae generator, t alo mportant, that etmated frequency ω et ame a frequency ω, whch mean t hould be frequency-adaptve. DC offet caue unwanted wave n the grd frequency and ampltude etmated value at the output of the PLL tructure. Therefore, t wa neceary to make ome change to the extng SOGI block. Th enhanced SOGI block called DC-SOGI. A block dagram of the SRF-PLL tructure wth a DC-SOGI block and a block dagram of the DC-SOGI block telf are hown n Fg. a) and Fg. b). Tranfer functon of DC-SOGI block gven by the followng equaton: m V () () V k k 3 g ( ) ( ) () () (3) k e DC (t) 0 Fgure b. Block dagram of DC-SOGI block Flter of the DC-SOGI block mα() and mβ() can elmnate the DC offet whle the SOGI block not able to. If t aumed that the meaured grd voltage r(t) contan DC offet, the value of th DC offet etmated at the control loop output and then ubtracted from the nput voltage upermpoed wth DC offet. The key parameter of propoed cloed loop the ntegral gan k. Both and mβ() flter are band-pa flter and have dentcal denomnator, but dfferent nomnator. Flter mα() n numerator ha ω, and the flter mβ() ha ω. Th dfference n numerator eental for generatng two gnal v α(t) and v β(t) phae-hfted for π/ at the output of DC-SOGI block. If replaced wth jω n (3) and (4), t can be concluded that the mα() flter ntroduce a zero phae delay, whle the mβ() flter ntroduce a phae delay of π/ regardng meaured grd voltage r(t). Frequency band-pa flter do not pa DC offet and hgh-frequency noe f the nput voltage contan them at all. III. DC-SOGI BLOCK RESPONSE If t aumed that the meaured grd voltage contan a DC offet t can be expreed a: v n(t) = V nco(ωt) + C, where v n0(t)= V nn(ωt) nuodal gnal wthout DC offet, whle C DC offet. Laplace tranformaton of v α and v β gnal at output of two-phae generator gven by: C (5) V ( ) m ( ) Vn 0( ) m ( ) 54

3 C (6) V ( ) m ( ) Vn 0( ) m ( ) After performng the nvere Laplace tranform, the equaton (5) and (6) how that the gnal v α and v β are: v ( t) V co( t) Ae A e co( t) A e n n( t) t/ 3 t/ 6 t/ t/ v ( t) V n( t) A e A e co( t) A e n n( t) t/ t/ 4 5 It obvou that the exponental component n equaton (7) and (8) dappear after (3-5) τ and τ, o the gnal v α(t) = V nco(ωt) and v β(t) = V nn(ωt) at output of two phae generator are phae hfted for π/. From (3) and (4) t clear that the value of the ntegral gan k determne the pole poton of the functon mα() and mβ() n -plane, o the parameter k determne the value of the tme contant τ and τ, ampltude A, =,,..., 6, and frequency ω n the tme doman, whch affect the repone of the two-phae generator durng the tranton proce. If the real and conjugated complex root of the charactertc polynomal D() are -a (a> 0) and j j, repectvely, where n n n ζ (0<ζ<) dampng factor, and ω n natural frequency, then: 3 ( k ) k ( a)( n n ) (9) ( a ) ( a) a 3 n n n n From (9): (7) (8) k a (0) n n () n n a k a () Term for a, ζ and ω n depend on parameter k are gven by equaton (0)-(). Therefore, tme contant τ = /a, τ =/ ζω n and frequency ω from (7) and (8) can be determned ung k parameter. Optmal value of k can be determned from condton of the equalty of real root (-a) and real part of conjugated-complex root (-ζω n). Ung a= ζω n n (0)-() obtaned: k 3a (3) ( a k ) a (4) 3 Ung ω=πf, f=50 Hz (grd frequency) and olvng (3) and (4) for a and k obtaned: a (5) IV. DC-SOGI BLOCK IN DISCRETE DOMAIN Dgtal devce uch a FPGA, Dgtal Sgnal Proceor (DSP), etc. are commonly ued for gnal proceng. In order to mplement a control tructure on a dgtal devce, uch a PLL, t neceary to dcretze the tructure frt, whch mple dcretzaton of each ndvdual block of the tructure. Durng the dcretzaton proce, t neceary to choe ample tme, whch gnfcantly nfluence the operaton of the DC-SOGI block. In [5] analyzed the tablty, the repone of the DC-SOGI block and the entre SRF-PLL tructure. A already mentoned, one of the key component of the ngle-phae SRF-PLL tructure a two-phae generator that generate two phae-hfted gnal v α(t) and v β(t) from the ngle-phae meaured grd voltage. The two-phae generator made of two econd order flter. Applyng blnear tranformaton on tranfer functon () and () tranfer functon of thee flter n z-doman are ganed: where: z z r z pz q z z z t z pz q a b b 4 b a 4 r, t, p, q, a b 4 a b 4 a b 4 a b 4 a T, b T (7) (8) The blnear tranformaton map the - plan left half to the nteror of the unt crcle n the z-doman, whch mean that f a tranfer functon table n the -doman, t mage n the z- doman alo table. Regardle of th, a rgorou proof of the flter tranfer functon n the z-doman tablty wa performed [5]. The β() flter a low pa flter and t can not elmnate the DC offet f t occur n the meaured grd voltage. Thu, n general, the two-phae generator telf can not elmnate the nduced DC offet unle the loop propoed n [5] appled. The block dagram of the DC-SOGI block n the z-doman hown n Fg 3. v n (z) e(z) m(z) r (z) e(z) α (z) β (z) v α (z) e DC (z) v DC (z)=0 v α (z) ω et v β (z) k k (6) The obtaned value of parameter k from (6) optmal. opt 55 Fgure 3. Block dagram of dcrete DC-SOGI block [5]

4 Mlca Rtovć Krtć et al. From block dagram at Fg. 3 t clear that dcrete block perform the ame functon a thoe n the contnou doman. Thu, f the dcrete nput grd voltage v n(z) contan a DCoffet, α(z) act a a frequency band-pa flter, o t doe not pa through a DC component, and the etmated value of the DC offet e DC(z) dfference between gnal at the nput and output of th flter: e DC(z) = e(z) v α(z). The DC offet further compared to t reference value v DC(z)=0 and the error paed through the mple regulator (ntegrator) r(z), and ubtracted from the nput gnal that contan DC offet. Th way, the DC offet that exted n the meaured nput gnal v n(z) wll be elmnated. A already mentoned, the key parameter of the DC-SOGI block control loop, for DC offet elmnaton, a parameter that determne the dynamc of the DC offet elmnaton. Tranfer functon of the modfed flter mα(z) and mβ(z), accordng to Fg. 3, are: m m z z V z z Vn z r z z V z z Vn z r z z (9) (0) Ued DC-SOGI control loop controller a mple ntegrator and n z-doman ung a blnear tranformaton t tranfer functon : T z * z * T r z k, Gr z k, k k z z () two-phae generator precely to th dorder. From the theory of dcrete ytem t known that the conjugate complex root of the charactertc polynomal D(z) cloet to the boundary of the unt crcle n z-doman, have a domnant nfluence on the character of the dcrete ytem tranent proce. In th cae, a par of conjugated complex root z,3=σ ±jω z have a key mact on the tranton proce. Conjugated complex root can be wrtten a: z z,3 r, r z, arctg (4) Domnant tme contant T d of tranton proce regardng T th conjugated complex root gven a: T. In th d ln r cae for 4 6T d the contant T d = That mean that tranton proce end n 4 6T d whch about DC offet etmaton tme at the output of control loop ( r(z) - Fg. 3) hown n Fg. 4 for three dfferent value od parameter k and for two lmt value of DC offet n meaured gnal: %@30 V and 50%@30 V. For mall value of parameter k (k =0), DC offet etmaton tme at control loop output about 0.5, whch very longme. In the other hand f the parametar value bg k (k =500) unwanted oclaton occure, and lat about 0.3, whch not good too. For optmal value of parameter k (k = k opt=85.64) tranton proce end n 0.05 whch accordant wth prevou analy. After arrangng and mplfyng mα(z) and mβ(z) can be wrtten a: where: m m z z r 3 r z z z z p z p z p t z z z z p z p z p 3 3 * * p k r p q p k r p q p * * p,, k r k r * k r q q 3 * p k, () (3) It clear that both modfed DC-SOGI block flter mα(z) and mβ(z) are band-pa flter and do not pa ether a DC component or a hgh-frequency noe f they occur n the meaured grd voltage. Propoed flter doe not pa DC component and t confrmed ung the lmt value theorem n z-doman. The next tep to determne the mpact of the ntegral gan k on the etmaton parameter and DC component elmnaton at the output of a two-phae generator. The appereance of a DC offet at the nput of a two-phae generator can be vewed a tep change, o t nteretng to oberve the repone of the 56 Fgure 4. DC offet etmaton tme at output of control loop for three dfferent value of parameter k and for two dfferent value of DC offet %@30 V and 50%@30 V V. RESULTS OF EXPERIMENT Structure and algorthm for gnal flterng are motly mplemented on dgtal hardware. A the dgtal hardware n th work, the FPGA board wa ued. FPGA belong to a type of programmable crcut where dfferent dgtal tructure

5 (control tructure/algorthm) can be realzed and whch can be programmed/reprogrammed outde the producton. Modern FPGA board can contan element uch a proceor core, PLL crcut, embedded RAM memory, etc. Programmng language that are ued for programmng FPGA are called Hardware decrpton language (HDL), mot common are the VHDL (VHSIC - Hardware Hgh Speed Integrated Crcut) and Verlog (tandardzed IEEE 364 programmng language). In addton to wrtng n the HDL edtor, the code n thee programmng language can be automatcally generated from other program, uch a MATLAB, Quartu, and o on. Generaton of HDL code n the MATLAB envronment poble from: Smulnk model, Stateflow dagram, Embedded MATLAB block and tool for creatng dgtal flter. The technque for HDL code generaton from the MATLAB envronment decrbed n detal n [6]. Already degned, mproved SRF-PLL tructure n Smulnk wa matched to the MATLAB HDL encoder, and then the obtaned HDL code were verfed n the ModelSm program, and then ued for programmng the FPGA crcut. The reult obtaned by the mulaton n MATLAB/Smulnk and ModelSm envronment are compared to thoe obtaned n experment. Ued FPGA located on the Altera DE board from the Cyclone II famly [7]. In order to oberve the gnal from the DE board on an ocllocope and record t, t wa neceary to perform a dgtal to analogue converon, whch wa ued by the Terac AD/DA board [8]. The AD/DA panel convert the 4-bt data nto an analogue value, therefore, t wa neceary to convert the output gnal length of the extng PLL tructure. Th hortenng dd not nfluence the analy of the tructure performance. The Altera DE board, together wth the Terac AD/DA board, hown n Fg. 5. offet meaured n grd voltage. Smulaton reult proved the valdty of the mathematcally derved value of the twophae generator control loop. The reult of the mplementaton of SRF-PLL tructure on the FPGA board are alo atfactory. Frt, DC-SOGI block of the dcrete SRF-PLL tructure mplemented on FPGA board n order to analyze the tme of DC offet etmaton. A a tet gnal at the nput of the DC- SOGI block, DC offet tep change to 50% of the ampltude grd voltage normalzed to one. Fg. 6 how the tme of DC offet etmaton at the output of DC-SOGI block control loop, where the block mplemented on FPGA board. The experment wa performed for three dfferent value of the k parameter: (0, k opt = 86.54, 500). From Fg. 6 t can be een that for lower value of the k parameter (k =0), the etmaton tme of DC offet at the control loop output about 0.5, whch too low and negatvely affect the dynamc behavor of the entre SRF-PLL tructure. On the other hand, f the value of k parameter large (k =500), there are undered damped ocllaton n the etmated value. For the parameter optmum value k opt =86.54, the tranton proce end n 0., whch n accordance wth the performed analy and wth the control loop mulaton n the contnou and dcrete doman. Fgure 5. Altera DE board wth Terac AD/DA board [8] Expermental reult howng the behavor of a dcrete SRF-PLL tructure wth a DC-SOGI block mplemented on the FPGA board and derved from DA converter output are preented n th paper. Smulaton reult of the dcrete SRF- PLL tructure obtaned n Smulnk and ModelSm envronment [6] howed that the dcrete tructure behave dentcally a the tructure n the contnou doman, and devaton are mnmzed. In thee mulaton, the tructure repone for dfferent value of the k parameter wa teted, n the cae of frequency and ampltude grd voltage tep change, a well a the ablty to etmate the grd parameter f DC 57 Fgure 6. DC offet etmaton at the output of DC-SOGI block control loop, wth DC offet tep change to 50% of grd voltage ampltude normalzed to The followng analy refer to the behavor of the SRF- PLL tructure wth the DC-SOGI block for two cae. In the frt cae, the grd parameter have reached ther tatonary tate and need to be etmated, and n the econd cae, tme for etmaton of grd parameter are analyzed n the cae of nput voltage tep change. The behavor of the SRF-PLL tructure wa teted wth mulaton n Smulnk and ModelSm envronment [6], followed by the mplementaton on the FPGA board. For the grd frequency and ampltude etmaton n a tatonary tate, at the tructure nput brought nu gnal v n(t) = n(ωt), where ampltude normalzed to one, wth a mall and large percentage of the DC offet (5% and 50% of the normed value). The tet were performed for two frequency lmt of 49 Hz and 5 Hz and for two ampltude lmt value: 0.5 and.35 of the normalzed grd voltage value, accordng to defned nternatonal tandard uch a: IEEE 547 and IEC 677. If there DC offet n meaured grd voltage, grd parameter n the tatonary tate have wave f zhere no control loop for DC offet elmnaton. Therefore, n thee cae t mpoble to accurately determne the value of thee parameter. On the other hand, when a control loop appled, t completely elmnate the DC offet and there are no wave n the etmated grd parameter. The reult are hown n Fg.

6 Mlca Rtovć Krtć et al It hould be noted that n Fg. 7-0 and Fg. 5 (frequency etmaton n tatonary tate and frequency tep change) there an offet of 0.5 Hz, whch reult of data converon from an ocllocope nto a form acceptable to MATLAB, a program n whch graphc were drawn. Fgure 7. Etmated grd frequency of 49 Hz wth 5% DC offet n tatonary tate wthout (green lne) and wth (blue lne) control loop for DC offet elmnaton Fgure 8. Etmated grd frequency of 5 Hz wth 5% DC offet n tatonary tate wthout (green lne) and wth (blue lne) control loop for DC offet elmnaton Fgure 9. Etmated grd frequency of 49 Hz wth 50% DC offet n tatonary tate wthout (green lne) and wth (blue lne) control loop for DC offet elmnaton Fgure 0. Etmated grd frequency of 5 Hz wth 50% DC offet n tatonary tate wthout (green lne) and wth (blue lne) control loop for DC offet elmnaton 58

7 Fgure. Etmated grd magntude of 0.5 *V nom wth 5% DC offet n tatonary tate wthout (green lne) and wth (black lne) control loop for DC offet elmnaton Fgure. Etmated grd magntude of.35 *V nom wth 5% DC offet n tatonary tate wthout (green lne) and wth (black lne) control loop for DC offet elmnaton Fgure 3. Etmated grd magntude of 0.5 *V nom wth 50% DC offet n tatonary tate wthout (green lne) and wth (black lne) control loop for DC offet elmnaton Fgure 4. Etmated grd magntude of.35 *V nom wth 50% DC offet n tatonary tate wthout (green lne) and wth (black lne) control loop for DC offet elmnaton 59

8 Mlca Rtovć Krtć et al. Fgure 5. Dnamc of SRF-PLL tructure for tep change of grd frequency from 5 Hz to 49 Hz and vce vera Fgure 6. Dnamc of SRF-PLL tructure for tep change of grd magntude from 0.5 *V nom to.35 *V nom and vce vera VI. CONCLUSION In ngle-phae ytem, generatng two quadrature gnal much more complcated, nce they are derved from a ngle-phae grd voltage. For th purpoe, t neceary to degn a two-phae generator. After analyzng the extng two-phae generator for ngle-phae PLL tructure (SOGI- PLL and Park-PLL), an mproved two-phae generator propoed DC-SOGI block, whch bede generatng quadrature gnal ha the poblty of elmnatng the noe and DC offet from grd voltage f they are meaured. The performed mathematcal analy howed how to adjut the parameter of th two-phae generator o that the repone of the SRF-PLL tructure to the ampltude or frequency jump are optmal. The value of an ntegral gan of control loop whch elmnate DC offet affect both the effcency of elmnaton and the peed of grd parameter etmaton. To mplement SRF-PLL tructure on ome dgtal devce t wa neceary to dcretze tructure. Frt, the mproved two-phae generator wa dcretzed, and then all other block of the SRF-PLL tructure. Mathematcal analy howed that the dcretzaton of a two-phae generator doe not affect the tablty and repone of the tructure, and then mulaton proved th fact. In order for the SRF-PLL tructure to be mplemented on the FPGA crcut, all the gnal of th tructure that are preented n the fxed-pont format. Th converon uually can gnfcantly affect the operaton of the tructure unle the approprate bt length elected for repreentng the broken and nteger part of the number. For the correctly elected length of the broken and nteger part devaton are mnmal. The block of th modfed SRF-PLL tructure are coded ung the Smulnk HDL coder, followed by degnng dgtal 60 SRF-PLL tructure n the Quartu envronment. Smulaton of th tructure are performed n the ModelSm envronment too. Comparng mulaton reult from Smulnk and ModelSm envronment, t concluded that the tructure performance even after the codng proce remaned very good. At the end, tructure mplemented on FPGA board, and performance of the tructure are preented. Concluon the ame. Implementaton once agan confrmed that the tructure performance remaned very good on dgtal devce. In the future tep, the propoed two-phae generator hould be modfed n order to olve problem caued by the appearance of hgher harmonc n the grd voltage, and the ymmetrcal and aymmetrc aturaton (cuttng) of the meaured grd voltage. REFERENCES [] S. Lubura, M. Šoja, S. Lale, M. Ikc,, Sngle-phae phae locked loop wth DC offet and noe rejecton for photovoltac nverter, IET Power Electronc, Vol. 7, No. 9, pp , ISSN , DOI 0.049/et-pel , 04 [] M. Cobotaru, R. Teodorecu, and F. Blaabjerg, A new ngle-phae PLL tructure baed on econd order generalzed ntegrator, n Proc. 37th IEEE PESC, pp. 5 56, Jun [3] P. Rodrguez, A. Luna, M. Cobotaru, R. Teodorecu, and F. Blaabjerg, Advanced Grd Synchronzaton Sytem for Power Converter under Unbalanced and Dtorted Operatng Condton, IEEE Indutral Electronc, IECON 006-3nd Annual Conference on, vol., no., pp , 6-0 Nov [4] M. Cobotaru, R. Teodorecu, and F. Blaabjerg, A New Sngle-Phae PLL Structure Baed on Second Order Generalzed Integrator, Power Electronc Specalt Conference, 006. PESC th IEEE, vol., no., pp. -6, 8- June 006. [5] S. Lale, S. Lubura, M. Šoja, M. Ikć, A Dgtal Degn of Novel Two- Phae Generator a Part of SRF-PLL Structure for PV Inverter INFOTEH-JAHORINA Vol. 3, March 04.

9 [6] M. Rtovć Krtć, Unaprjeđena jednofazna PLL truktura kao do upravljačke trukture PV nvertora, INFOTEH-JAHORINA Vol. 5, March 06. [7] Altera Corporaton: DE Development and Educaton Board, Uer Manual, Veron.4 [8] Terac: THDB ADA Uer Gude, 008 [9] M. Rtovć Krtć, S. Lubura, T. Nkolć, Implementacja unaprjeđene jednofazne PLL trukture a DC-SOGI na FPGA kolu, INFOTEH- Jahorna, Vol. 6, March 07, pp Mlca Rtovć Krtć enor teachng atant at Unverty of Eat Sarajevo, Faculty of Electrcal Engneerng at Department of Automaton and Electronc. Her reearch area nclude Phae Locked Loop, Embedded Sytem, Robotc and Mechatronc and Indutry Automaton. Slobodan Lubura profeor at Unverty of Eat Sarajevo, Faculty of Electrcal Engneerng at Department of Automaton and Electronc. H reearch area nclude Phae Locked Loop, Embedded Sytem, Power Electronc, Robotc and Mechatronc and Indutry Automaton. Tatjana Nkolć profeor at Unverty of Nš, Faculty of Electronc Engneerng at Department of Electronc. Her reearch area nclude SoC degn, Embedded Sytem, Dgtal Sytem Implementaton, Combnatonal Crcut Degn. 6