MOBILITY TM RADEON TM GPUs Graphics Subsystem Layout Guide

Transcription

1 MOBILITY TM RADEON TM GPUs Graphics Subsystem Layout Guide Rev. 1.9 Technical Reference Manual P/N: DSG-216MOBRADEON Advanced Micro Devices Inc.

2 Trademarks AMD, the AMD Arrow logo, Athlon, and combinations thereof, ATI, ATI logo, Radeon, and Mobility are trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Disclaimer The contents of this document are provided in connection with Advanced Micro Devices, Inc. ( AMD ) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights are granted by this publication. Except as set forth in AMD s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. The information contained in this manual has been carefully checked and is believed to be entirely reliable. No responsibility is assumed for inaccuracies. ATI reserves the right to make changes at any time to improve design and supply the best product possible Advanced Micro Devices, Inc. All rights reserved.

3 Table of Contents 1 Introduction About this Manual Conventions General Layout and EMI Considerations Useful References Placement, Vias, and General Routing Critical Nets (High Speed Routing) General Guidelines EMI Shielding Power and Ground Considerations General Guidelines Decoupling and Bulk Capacitors PCI Express Power Guidelines PCI Express Interface Test Points Recommendations Memory Interface General Routing Guidelines (DDR2, DDR3, GDDR3) Trace Skew Guidelines (DDR2, DDR3, GDDR3) Guideline Relaxation for Low Speed and 4 Layer Designs Topology Dual Rank GDDR3 Topology Trace Impedance Guidelines (DDR2, DDR3, GDDR3) Using Single Rank Memory (DDR2, DDR3, GDDR3) Using Dual Rank Memory (GDDR3) Trade-off between Impedance Matching Requirements and Performance Specific Routing Guidelines by Signal Groups (DDR2, DDR3, GDDR3) Data Groups Caution when Using the Rev ID Feature of GDDR Memory Clock Lines Address/Control Lines GDDR5 Memory Routing Guidelines Trace Impedance Requirements Maximum Allowed Signal Skews Cross-Talk Reduction Reference Voltage Dividers DAC1/DAC2 Interfaces General Routing Guidelines DAC Termination (for M7x, M8x and M8x) Advanced Micro Devices, Inc. Table of Contents MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 3

4 7 LVDS and TMDS/DisplayPort Interfaces LVDS/TMDS/DP Layout Guidelines General Skew Requirements MUX and Serial Resistors Power Rails De-Coupling Capacitor Recommendations Board Compatibility Considerations DVP Interface External TMDS Layout Guidelines CrossFire Layout Guidelines Interface (Including Receptacle) Design/Layout Guidelines Cable Design/Layout Guidelines PCB Layout Guidelines Thermal Interface Appendix A: Via Electrical Model Appendix B: Decoupling Capacitor Considerations B.1 Capacitor at High Frequency B.2 Capacitor Placement and Routing Appendix C: Differential Trace Parameters Calculations C.1 Using Equations C.2 Using Numerical Analysis C.3 Sample Trace Parameter Calculation Results Appendix D: Revision History Advanced Micro Devices, Inc. Table of Contents MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 4

5 List of Tables Table 1: Recommended Maximum Memory Trace Skews Table 2: Single Rank Memory Trace Impedance Guidelines Table 3: Dual Rank Memory Trace Impedance Guidelines Table 4: DDR2 Memory Data Groups Swapping Possibilities...18 Table 5: GDDR5 Trace Impedance Requirements Table 6: GDDR5 Maximum Allowed Skews Table 7: Space:Height Requirements for Cross-Talk Reduction and Impedance Matching Table 8: Recommended Maximum Trace Skews (ASIC to Connector, PCB Budget) for Pre-M9x GPUs Table 9: Electrical Parameters of Through-hole Via and Microvia Table 10: Method 1 - Fix Zdiff, feed in s, to calculate Zo and W Table 11: Method 2 - Feed in s and W to calculate Zdiff and Zo Table 12: Example Differential Pair Trace Calculations Advanced Micro Devices, Inc. List of Tables MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 5

6 List of Figures Figure 1: Connect AVSSQ Trace to GND through an Individual Via...10 Figure 2: Split Power Plane Recommendations...11 Figure 3: Example of Staggered Vias to Provide Open Channels...11 Figure 4: Test Points for PCI Express Lanes...13 Figure 5: Dual Rank GDDR3 Topology...16 Figure 6: Memory Clock Pair Shielding...20 Figure 7: DAC Pseudo-Differential Termination...23 Figure 8: DAC Single Termination...23 Figure 9: Using Space to Reduce Cross-Talk...25 Figure 10: Shunt Resistor Placement on Top Layer...25 Figure 11: Shunt Resistor Placement on Bottom Layer...26 Figure 12: TMDS/DP Muxing...27 Figure 13: Flexible Configuration for DP and DVI/HDMI Interfaces...28 Figure 14: Use Centermost DVP Clock for 24-Bit DDR Mode Operation...30 Figure 15: Through-hole Via Geometry and Circuit Model...32 Figure 16: Impedance of Through-hole Via vs. Frequency...33 Figure 17: Capacitor Impedance vs. Frequency...34 Figure 18: An Inefficient Filter Capacitor Layout...35 Figure 19: A More Efficient Filter Capacitor Layout...35 Figure 20: Filter Capacitors Placement Advanced Micro Devices, Inc. List of Figures MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 6

7 1 Introduction 1.1 About this Manual This manual is intended for experienced design engineers. It covers general and specific design guidelines to help integrate a currently available MOBILITY TM RADEON TM GPU (M7x or later) into a PCI Express motherboard-based graphics subsystem or into an add-in module/card. While the guidelines in this manual are strongly recommended for a robust design, it is understood that, in practice, sometimes some of the recommendations cannot be followed exactly. In such cases the designer must decide on the best compromise based on cost and performance considerations. 1.2 Conventions Throughout this document, the term MOBILITY TM RADEON TM GPU applies in general to all members of the family. In cases where a particular feature or recommendation applies to only certain member(s), adequate note will be provided Advanced Micro Devices, Inc. Introduction MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 7

8 2 General Layout and EMI Considerations 2.1 Useful References Printed Circuit Board Design Techniques for EMC Compliance by Mark I. Montrose. 2000; ISBN ; Product No.: PC5816-TBR. EMS/EMC Computational Modeling Handbook by Bruce Archambeault, Colin Brench, Omar Ramahi. Kluwer International Series in Engineering and Computer Science. 2001; ISBN High Speed Digital Design by Howard Johnson and Martin Graham. 1993; ISBN: ; Prentice Hall. 2.2 Placement, Vias, and General Routing For optimal performance and system reliability, the board requires low-impedance power and ground return paths. See Section 3 Power and Ground Considerations for detailed discussion. Keep digital signals and components away from analog sections. Provide separate filtered power supplies for analog functions. In general, use vias with 8:1 aspect ratio. The aspect ratio (length:diameter) of a via is a measure commonly used to define the required diameter of a via for a given thickness of a multi-layered PCB. The leading-edge drills which have a diameter of 8 mil, can create a via with an aspect ratio of 12 (or 12:1); however an aspect ratio of 8 (or 8:1) or less is more costeffective. In general for a PCB thickness of 62 mils, 10 mil drills are a good choice. Use bigger via holes where possible. Minimize the number of vias on any signal. Trace length matching should be used as the starting point for the layout. Substrate trace lengths must be taken into account. Trace lengths include pin-to-trace breakout and trace-to-connector fan-in/-out. This applies to the combined trace lengths of the package and board signals. 2.3 Critical Nets (High Speed Routing) General Guidelines Keep noise sensitive nets short by placing components close to the ASIC. Do not run critical nets close to I/O nets, e.g., S-video, audio, etc. Do not run high speed critical nets over splits in planes. If discontinuities must occur, i.e., crossing plane splits, place bypass capacitors as close to the transition points as possible to give the return currents a low-impedance path. It must be remembered that since the capacitor inductance as well as the via inductance increase as frequency goes up, the efficiency of the bypass is very limited. If traces change reference planes, then stitching vias or sticking caps are required to join the two reference planes, e.g. GND and PWR, within 0.5 inch of the vias. If the planes are at the 2009 Advanced Micro Devices, Inc. General Layout and EMI Considerations MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 8

9 same potential, then a via should be used; otherwise, if the planes are at different potentials, then a cap should be used between the planes. The high frequency return current chooses the lowest inductance path, i.e., the path with minimum loop area. The distribution of these chosen return paths is difficult to predict. The rule of thumb is to allow high-frequency return paths to go back to their source with minimum loop; hence a solid reference with no splits under the high-speed signal is a must. Avoid 90-degree bends use two 45-degree bends instead. Keep the total number of turns on a trace to less than 15. Digital GND plane should be the reference plane; the ASIC should always be placed over the digital GND. Put digital GND guard traces on either side of critical nets; these should be via'd every inch to the digital GND at the beginning, in between, and at the end. High speed traces should always be referenced to a ground (preferred), or to a relevant power reference plane (like memory I/O power (VDDR1) plane for memory signals). Traces should be kept away from PCB edges by inch. Due to the inductance of the trace and the skin-depth effect, trace widths should be as wide as possible while maintaining the required impedance. For TMDS and RGB signals, routing on inner layers for noisy immunity is recommended. If the traces are relatively short, these signals can be routed on outer layers to avoid the use of vias. For more details on routing for memory, TMDS, and RGB signals, refer to their respective sections further on. Decoupling is important. For decoupling recommendations, see section EMI Shielding Increasing the distance between signals when laying out the board and shielding the signals with ground planes can reduce cross-talk. Increasing the ratio of the thickness of the prepreg to trace spacing can also reduce cross-talk. Ground guarded configurations must have at least two stitches to the ground plane (at the beginning and at the end of the guard trace). The rule of thumb is one stitch per 0.5 inch. Ground guards longer than 1.25 (31.75mm) must have at least 3 stitches. PCB edges should guarded by a "GND ring" of inch on all signal layers and the "GND ring" should be via'd to the GND plane at every 0.25 inch Advanced Micro Devices, Inc. General Layout and EMI Considerations MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 9

10 3 Power and Ground Considerations 3.1 General Guidelines Work out the power budget based on the estimated power requirements for the different power rails (see Databook), and then decide on what type of regulators to use. Linear regulators are simple and cost effective; however, they may not meet the current budget. In that case switching regulators must be used. When using switching regulators, switching noise and EMI must be considered. Keep all power supplies for the analog circuits separate from the PLL power supplies (LPVDD, PVDD, TPVDD, MPVDD, DPA_PVDD, DPB_PVDD). Use a separate analog power trace. If possible, connect dedicated ground traces (e.g. AVSSN, AVSSQ, A2VSSQ and A2VSSN) to the GND plane through an individual via. AVDD AVSSQ Decoupling Capacitor VIA to GND Plane Figure 1: Connect AVSSQ Trace to GND through an Individual Via Always provide power and grounding for the integrated TMDS and LVDS (regardless of whether the interfaces are used or not). For power supplies related to the analog circuits and the power supply related to the PLL circuits, ensure that the width of the traces is greater than 15mils. These traces are routed from the regulator, or ferrite bead, to the power pins on the GPU. The length of these traces should be less than 2.5 inches. For optimum return path continuity, the analog grounds must be routed back to where their associated powers are regulated (see Reference Schematics). Connect AVDD and A2VDD directly to the AVDD and A2VDD regulators respectively via a ferrite bead. A2VDDQ may share the same (1.8V) regulator as AVDD. Keep toggling signals away from these pins. Do not tie AVSSQ/A2VSSQ to AVSSN/A2VSSN. If necessary, use power islands instead of power traces to help reduce impedance. A solid ground plane and a solid power plane will have the lowest possible impedance at high frequencies Advanced Micro Devices, Inc. Power and Ground Considerations MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 10

11 > 3 Power VIAs FROM REGULATOR > 200 MILS POWER ISLAND Figure 2: Split Power Plane Recommendations Reduce power delivery inductance by flooding/fingering on a signal plane over the ground plane (or vice versa). Use at least three power vias to connect power trace to the power plane or island. Try to use at least one via for each power pin, and one via for each ground pin. Due to space limitations, two pins per via may be necessary, and is acceptable. This means that, wherever possible, try to have the same type of power vias shorted together on the component or solder side where the device is mounted. Certain isolation might be required, especially for ground vias, to avoid interference. See Apendix A for more discussions on vias. Keep the length of the trace between any via and the associated power or ground pin as short and wide as possible to reduce impedance to the power plane connection. As a rule of thumb, power traces should be at least 60 mils wide for each Ampere that they conduct. Use staggered vias to avoid narrowing and blocking of power and ground paths. This is important for the ASIC and memory with a high concentration of vias. Figure 3: Example of Staggered Vias to Provide Open Channels After routing is complete, fill all open areas with GND or power. Use power area fills on the top layer and GND area fills on the bottom layer in case of signal1 GND VCC signal2 stack-up. The area fills should be connected to internal planes with one via for every 0.5 inch Advanced Micro Devices, Inc. Power and Ground Considerations MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 11

12 All ground islands should be stitched by vias to digital GND at multiple and evenly spaced points. To comply with EMC standards, the system ground must be separated from the chassis ground in the layout, and then linked together using 6 to 8 resistors footprints. Half of these should be placed on the component side, and the other half on the solder side. Heat sinks should be grounded to digital GND Decoupling and Bulk Capacitors Note: The following statements apply to the GPU, memory, and all the other logic components. Remember that the inductance and resistance of the bypass capacitor as well as the inductance of the trace connecting the capacitor to its respective power and ground limit the effectiveness of any bypass capacitance. Place all decoupling capacitors as close as possible to the GPU. Place these groups of capacitors as close to the appropriate power pads as possible. Use several groups of decoupling capacitor pairs (1µF, 100nF and 10nF) for each ASIC power supply, especially for VDDC, VDDCI (core powers), PCIE_VDDR12, PCIE_PVDD12, PCIE_PVDD18, VDDR (I/O powers), and VDD15 or VDDC18 (I/O level shift power, also designated as VDD_CT). Install at least one bulk 22µF or 47µF ceramic capacitor on each of the following ASIC power supplies: VDDP, VDDR1, VDDR3, VDDR4, VDDR5, VDDRH0-VDDRH1, VDDM, VDDQM, VDDC, VDD15 or VDDC18 (also designated as VDD_CT), PCIE_VDDR12, PCIE_PVDD12, and PCIE_PVDD18. All S-video IN and OUT, composite IN and OUT, audio IN and OUT, and SPDIF lines should be provisioned for ferrite beads next to their connectors. Capacitors to the digital GND should be placed next to the connector pins. Power lines that leave a connector (e.g., +5V connections) should have individual decoupling capacitors placed immediately next to the connector pins. 3.2 PCI Express Power Guidelines PCIE_VDDR_12 must not share the same power source with VDDC for the following reasons: PCI-E rails are not tolerant of the potential noise from the VDDC rail. VDDC switches to lower voltage for power saving modes. If PCIE_VDDR_12 and VDDC power islands are on adjacent power planes, they must not overlap to avoid interference Advanced Micro Devices, Inc. Power and Ground Considerations MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 12

13 4 PCI Express Interface Component layout and routing of the PCI Express interface signals must be carefully done to meet the timing and signal quality requirements of the PCI Express specifications. For more information, refer to the following publications: PCI Express Specification 1.0a, PCI Express Base 2.0 Specification and PCI Express Board Design Guidelines. 4.1 Test Points Recommendations For initial prototypes, the following are recommended: Provide a PCI Express mid-bus probing footprint. Without this connector, a logic analyzer cannot be connected to the bus for debugging. Provide test points on all the receiver signals for checking signal integrity. These test points must be placed not more than 250 mils from the ASIC balls. The distance from the ball to the test point on the positive and negative signals of a differential pair must be the same. These test points can be achieved with the provision of openings in the solder mask on the bottom layer to access the fan-out vias. Do not add trace stubs when creating test points. Figure 4: Test Points for PCI Express Lanes If test points cannot be added to all receiver signals, then as a minimum, have test points on: o PCIE_RX0N, PCIE_RX0P o PCIE_RX7N, PCIE_RX7P o PCIE_RX15N, PCIE_RX15P 2009 Advanced Micro Devices, Inc. PCI Express Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 13

14 5 Memory Interface The Mobility Radeon GPUs support a variety of memory configurations. See the databook for a particular GPU of interest. The Mobility Radeon GPUs have signal driver strength control registers for memory address, control, data, mask, strobe and clocks, that can adjust impedances going to the memory. The following layout guidelines are for configurations that use external memory. Notes: Sections 5.1 to 5.5 apply to DDR2/DDR3/GDDR3 memories only. For GDDR5 memory, please refer to section 5.6 GDDR5 Memory Routing Guidelines. 5.1 General Routing Guidelines (DDR2, DDR3, GDDR3) See also section 2.3 Critical Nets (High Speed Routing). See section 3 for power and ground guidelines. If any signal is connected to more than one load, use T topology routing (see section 5.3). It is preferable to have 5:2 space:height (space between two traces to distance from the signal layer to the reference place) ratio after breakout (note: this is stack-up dependent). If not achievable, then: o Parallel run lengths of 2:1 ratio must be < 0.5 o Parallel run lengths of 1:1 ratio must be < 0.25 Ground guarded configurations must have at least 2 stitches to the GND plane, at the beginning and at the end of the guard trace. Ground guards > 1.25 must have at least 3 stitches. In all cases, the space between 2 stitches must be less than 1. If a line transitions more than 2 layers (greater than a layer1 to layer3 transition and changes its reference plane), then a ground transition via, connecting the Ground 1 reference plane to Ground 2, should be placed as close to the transition via as possible, especially for QS lines. Resistor packs used for termination must not be shared between different signal groups. Route data lines away from the rest of the memory interface signals. Cross talk from read data changing in memory command during setup time can cause command or address misinterpretation by the memory. Take special care to route memory clocks (CLK/CLK#) and data strobes (QS). They must be adjacent to a ground or power layer. Avoid routing memory clocks and strobes in parallel directions with traces on adjacent layers. Trace impedance must be maintained constant through layers - if the same trace width is used for routing through all layers, board stack-up must be chosen in a way that preserves constant trace impedance Advanced Micro Devices, Inc. Memory Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 14

15 5.2 Trace Skew Guidelines (DDR2, DDR3, GDDR3) To design a board that can accommodate multiple pin-compatible GPUs, it is convenient to separate delay times (or skews) into two budgets, one for the GPU substrate (covering all ASICs in the same family) and the other for the PCB. Then for such a design, the skews from the substrate can be ignored. The table below shows the recommended maximum allowed skews amongst the memory signal traces on the PCB. For reader s convenience, delay times have been converted to equivalent lengths using conversions factors of 0.18ps/mil and 0.165ps/mil for inner and outer traces respectively. Table 1: Recommended Maximum Memory Trace Skews Memory Trace Skews (DDR2/DDR3/GDDR3) Delay (ps) Equivalent Length (mil) (Inner Layer) Equivalent Length (mil) (Outer Layer) For each 32 bit Clk+ to Clk- (Intra-pair) Clk+ to Cntl/Address/ODT (CLK+ centered within its Cntl/Address/ODT group) CLK+ to RDQS (or QS) (CLK+ centered within its RDQS (or QS) group) RDQS to WDQS (or QS to QSb) RDQS (or QS) to DQ or DQM For each channel (64 bit) CLK0+/0- to CLK1+/1- (Inter-pair) Guideline Relaxation for Low Speed and 4 Layer Designs While the guidelines set out above are recommended for a robust design, they can be relaxed to accommodate cost or PCB space constraints. For 400MHz and lower designs, the length mismatch tolerances can be doubled. Note however that the frequency versus tolerance relaxation relationship is not linear and therefore any tolerance relaxation should be accompanied by a timing budget study. For DDR2, 55~60 Ohm parallel termination may be required on clock and control signals, but for low speed designs, these can be dispensed with. QS and QSb can be connected to Vtt to make them pseudo differential Advanced Micro Devices, Inc. Memory Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 15

16 5.3 Topology Dual Rank GDDR3 Topology Use clamshell configuration for shortest data branches (< 100 mils). Do not share power vias to isolate noise between clamshell devices. Figure 5: Dual Rank GDDR3 Topology 2009 Advanced Micro Devices, Inc. Memory Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 16

17 5.4 Trace Impedance Guidelines (DDR2, DDR3, GDDR3) The memory signals trace impedance requirements for different generations of GPUs vary according to the memory types and speeds supported. The tables below specify the impedance requirements for the memory signal traces for the different GPUs. The tables are organized such that GPUs in the same table are pin compatible and can use the same motherboard design. For optimal compromise, it is recommended that the motherboard design favor the highest performing GPU of the group, even if this may cause a small but acceptable disadvantage to the others. (Note: see also section for Tradeoff between Impedance Matching Requirements and Performance) Using Single Rank Memory (DDR2, DDR3, GDDR3) Note: All differential clocks must have a 56:56 ohm plus center cap termination, except when noted with (*) below. Table 2: Single Rank Memory Trace Impedance Guidelines GPU M72M/S M76M GPU M8x, M9x Memory Type Address (MA) Control Data Group Diff Clock Pairs (CLK) Main Trunk Branches (WE/CAS/RAS/CS/CKE) (DQ/DQM/DQS) Single Ended DDR GDDR * Memory Type Address (MA) Control Data Group Diff Clock Pairs (CLK) Main Trunk Branches (WE/CAS/RAS/CS/CKE) (DQ/DQM/DQS) Single Ended DDR DDR GDDR * GPU M9x, Manhattan Memory Type Address (MA) Control Data Group Diff Clock Pairs (CLK) Main Trunk Branches (WE/CAS/RAS/CS/CKE) (DQ/DQM/DQS) Single Ended DDR GDDR * * Use 60 ohm pull-up to VDDQ on memory side instead of 56:56 ohm plus center cap termination. Pin DQSb is grounded and ODT function is disabled in EMRS. Add 120 ohm pull-up to VDDQ on memory side. Optional and speed dependent (> 400MHz): May need to add 55 ohm pull-up to VTT (50% of VDDQ) on the junction of trunk and branches. Manhattan compatible designs only Using Dual Rank Memory (GDDR3) Table 3: Dual Rank Memory Trace Impedance Guidelines GPU M7x (not M71), M8x, M9x Memory type Address (MA) Control (WE/CAS/RAS/CS/CKE) Data Group Diff Clock Pairs (CLK) Main Trunk Branches Main Trunk Branches (DQ/DQM/DQS) Single Ended GDDR ** * GPU Memory type Address (MA) Control (WE/CAS/RAS/CS/CKE) Main Trunk Branches Main Trunk Branches Data Group (DQ/DQM/DQS) Diff Clock Pairs (CLK) Single Ended M9x, Manhattan GDDR ** * * Use 60 ohm pull-up to VDDQ on memory side. ** Add 120 ohm pull-up to VDDQ at the junction of main trunk and branches (see Figure 5 below). It must be close to the memory side. Manhattan compatible designs only Advanced Micro Devices, Inc. Memory Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 17

18 5.4.3 Trade-off between Impedance Matching Requirements and Performance With particular emphasis on GDDR3 memory, although the 35ohm and 40ohm trace impedance requirements (for address and data/clock lines respectively) indicated above are ideal to achieve memory clock speeds greater than 600MHz, designers may choose to trade-off memory speed for a simpler PCB layout. For example, for speeds of 400MHz or lower and a 4-layer design, 50~60 ohm trace impedance is acceptable, as long as other high speed design rules are observed. For branched signals, trunk impedance should be smaller than branch impedance with the ideal ratio of 1 to Specific Routing Guidelines by Signal Groups (DDR2, DDR3, GDDR3) Data Groups For DDR2 memory, a data group consists of 8 data lines (MD), 1 data mask line (DQM), and 1 data strobe line (QS). For DDR3 memory, each data group consists of 8 data lines, 1 DQM line and 2 QS lines. Route MD/QS/DQM/DIM signals into groups of 10 traces (1 memory macro) as follows: DATA0, DATA1, DATA2, DATA3, DQM, QS, DATA4, DATA5, DATA6, DATA7 (note that QS occupies the center position). These groups should be kept on the same layer if possible. Data groups can be swapped (see Table 4 below) within the groups that have the same clocks. NOTE: Some restrictions apply (see section ). Bits within the same byte can be swapped. Table 4: DDR2 Memory Data Groups Swapping Possibilities Associated Clocks CLK0, CLK0b CLK1, CLK1b Data Mask Strobe MD(7:0) DQM0 QS0 MD(15:8) DQM1 QS1 MD23:16) DQM2 QS2 MD(31:24) DQM3 QS3 MD(39:32) DQM4 QS4 MD(47:40) DQM5 QS5 MD(55:48) DQM6 QS6 MD(63:56) DQM7 QS7 Can be swapped Can be swapped Data groups (MD, DQM, QS, DIM) should be kept under 4.0. Any signal that exceeds this limit should be flagged for further evaluation. QS routing must follow the ground-guarded configuration for as long as possible. Spacing for ground guarding can be reduced to a 1:1 ratio. For example, a ground-guarded QS line would have a 1:1 ratio between: GND-QS-QS#-GND (note this ground-guarding configuration is for DDR2; for DDR3 it is GND-WQS-GND-RDQS-GND). If ground guarding is not possible, use 3:1 ratio. Stitch to ground plane every Advanced Micro Devices, Inc. Memory Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 18

19 Caution when Using the Rev ID Feature of GDDR3 Mobile designs can identify memory types either through straps on GPIOs or through a new feature of GDDR3. GDDR3 memory has the capability of providing such information through the DQ[7:0] pins, and all newer generation ATI GPUs (from M26 on) support this feature; however, for the following listed GPUs - M26, M28, M52, M54, M64, M62, and M71 - a restriction applies, in that the DQ[7:0] memory pins must be connected to the GPU s DQA[15:0] pins in order for the information to be read. This implies the following: Memory pins DQ[7:0] must be connected to either DQA[7:0] or DQA[15:8]. (Bits within the byte can still be swapped.) Single channel designs must use channel A since this memory id function is not supported on memory channel B. For all other non-listed GPUs, the DQ[7:0] pins can be connected to any byte. Note: Any swapping must be identified when requesting a VBIOS Memory Clock Lines These comprise the following clocks: CLKx0, CLKx0#, CLKx1, and CLKx1# (x denotes different memory channels, can be A or B). It is important to have a clean signal at both the driver side pin and at the receiver side, since this signal is sensed and fed back internally. It is critical that this signal transitions smoothly through the threshold region ( V for LVTTL devices) and is glitch free. The following are recommendations for laying out the memory clocks: Differential clock pairs, e.g., CLKA0 and CLKA0#, must be routed following the same rules for routing differential signals (see section 7: LVDS and TMDS/DisplayPort Interface). Route the clock signals away from other signals. Route the clocks in a modified star configuration (i.e., one trace should go to a position in the middle of all the memory chips, and equal length branches should proceed from the single point to each memory chip). The primary termination scheme for the differential clocks should be an AC-termination at the memory side (applicable to DDR2 and DDR3, but not to GDDR3, which does not require this termination). This configuration has a 60Ω resistor from each clock line to a 10nF capacitor that then connects to ground. The ground side of the capacitor should have a minimum of 2 vias. The traces from the resistors to the signal side of the capacitor and the traces from the ground side of the capacitor to the vias should be as short and as wide as possible (<0.025 long, >0.01 wide, this gives Z L = 1 mω approximately) Advanced Micro Devices, Inc. Memory Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 19

20 Provide ground guards for the clocks. Spacing for ground guarding can be reduced to a 1:1 ratio. The ground traces should run the full length of both sides of the clocks (stitch to ground plane every 1 ). Figure 6: Memory Clock Pair Shielding Address/Control Lines Each bank has the following address/control lines: 13 address lines (A), 1 chip select (CS), 1 row strobe (RAS), 1 column strobe (CAS), 1 write enable (WE) and 1 clock enable (CKE). The following rules apply when Address/Control lines need to be branched: To improve signal integrity and reduce skew caused by the settling time, it is highly recommended that equal lengths (within 0.2 tolerance) be maintained on all traces that branch out. The trunk length (length from the ASIC to the branch-point) should be less than or equal to 3.0. Any lines that exceed this limit should be flagged for further evaluation. The branch length should be less than or equal to 1. The tolerance for branch length mismatch is 0.1 or less. 5.6 GDDR5 Memory Routing Guidelines GDDR5 is the latest and fastest memory available, and as such, its signal routing requirements are more stringent. These are shown below Trace Impedance Requirements Table 5: GDDR5 Trace Impedance Requirements Signal MA Control CLK DQ EDC DBI WCK Impedance 45/50 Ω 45/50 Ω 80 Ω 45 Ω 45 Ω 45 Ω 80 Ω (Trunk/Branch) (Trunk/Branch) (Differential) (Differential) 2009 Advanced Micro Devices, Inc. Memory Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 20

21 5.6.2 Maximum Allowed Signal Skews Note: In the table below, the skew for each signal in a particular signal group is measured with respect to the signal identified with X in the Skew column. Table 6: GDDR5 Maximum Allowed Skews Signal Group Signal Skew (ps) CLK Group 1 CLK - X MA / Control 20 WCK + / - 50 WCK Group 2 WCK - X EDC 50 EDC X Group 3 DBI 5 DQ Cross-Talk Reduction To reduce cross-talk, while simultaneously satisfying the impedance requirements indicated in Table 5: GDDR5 Trace Impedance Requirements, the recommended minimum space to height ratios for the DDR5 signals are shown below. The values in a way are dependent on the copper thickness, which in turn determines the impedance. Table 7: Space:Height Requirements for Cross-Talk Reduction and Impedance Matching Signal MA Control CLK DQ EDC DBI WCK Space:Height 2:1 2:1 5:1 3:1 7:1 3:1 5:3 5.7 Reference Voltage Dividers Keep the MVREF, MVREFS, MVREFD divider resistors and the decoupling capacitors as close to the ASIC balls as possible, with the capacitors the closest - less than 500mils. If possible, isolate the MVREF, MVREFS, MVREFD nets from other close-by traces using ground shields and double spacing. Voltage reference circuits should not be shared. The decoupling capacitor for MVREF (D, S, A, M) should be place on the same layer as the ASIC (to avoid using a via) and as close as possible to the ASIC ball Advanced Micro Devices, Inc. Memory Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 21

22 6 DAC1/DAC2 Interfaces 6.1 General Routing Guidelines See also section 2.3 Critical Nets (High Speed Routing) and 3 Power and Ground Considerations. Analog DAC outputs (R, G, and B) can drive a 37.5Ω equivalent load. To match the 75Ω impedance of the CRT, connect 75Ω pull-down resistors to AVSSN (in parallel with the CRT) on these lines. It is important to keep the impedance of the RGB lines as close as possible to the ideal 75Ω. Impedance mismatch between the RGB lines and the CRT may result in excessive reflections on these lines. If the amplitude of the reflections is too large, it will cause image ghosting. Route R, G, and B traces 5 mils wide from the 75Ω resistor to the VGA connector. Use 10 mils wide GND guard traces and 5-mil spacing around R, G, and B traces. Use the same number of vias on each R, G, and B trace. Match R, G, and B traces to within 500 mils. Keep R, G, and B traces at least 15 mils from other traces. RGB, data, address or clock lines that cross splits in planes should have caps bridging the splits and within 0.25 inch of crossing; 2 capacitors per set of lines crossing split (one capacitor on each side). The VGA filter, along with the on-board 75Ω termination resistors should be placed as close to the connector as possible, with minimum inter-component routing trace lengths. The PCB traces themselves should be routes as stripline on the inner layers, while avoiding frequent changes of PCB layer along its path. For the ideal case, the longest section of the PCB trace would be routed on a single inner layer from the ASIC to the termination resistors close to the connector, followed by the VGA filter. [Note: routing the RGB PCB traces as microstrip on the outer layer may increase EMI emission if the VGA filter is placed close to the connector. For this scenario, the VGA filter might have to be placed close to the ASIC along with the 75Ω termination resistor to filter out high frequency components of the signal prior to sending it through the microstrip traces.] Each RGB line should have a capacitor placed next to the connector. To set the full-scale DAC1 and DAC2 currents, connect a high-precision (i.e., 1% tolerance) resistor between the RSET/R2SET pin and AVSSQ/A2VSSQ planes respectively. Keep toggling signals away from RSET/R2SET resistor and trace. Keep RSET and R2SET close to the ASIC Advanced Micro Devices, Inc. DAC1/DAC2 Interfaces MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 22

23 6.2 DAC Termination (for M7x, M8x and M8x) The DAC design for M7x, M8x and M9x provides individual ground returns for each DAC output (e.g.: RB, GB, BB for DAC1 and R2B, G2B, B2B for DAC2) instead of a common ground known as AVSSN. For high pixel clock frequencies such as CRT output or Component output, the optimal PCB design involves routing the DAC output and ground return together like differential outputs to the output connector with termination near the connector as shown in Figure 7. If the differential portion is less than 30% of the total trace length (from the GPU to the connector), or if the ground cannot be routed, then the ground returns can be connected to ground near the GPU as shown in Figure 8. Note that these ground returns MUST NOT be connected to the quiet DAC ground (i.e. AVSSQ). R2B, G2B and B2B are the ground return signals for both Y, C, Comp and R2, G2, B2. For standard TV out (i.e., S-video or Composite video) R2B, G2B and B2B should be connected directly to ground at the GPU (i.e., pseudo-differential termination is not required). Figure 7: DAC Pseudo-Differential Termination Figure 8: DAC Single Termination 2009 Advanced Micro Devices, Inc. DAC1/DAC2 Interfaces MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 23

24 7 LVDS and TMDS/DisplayPort Interfaces The MOBILITY RADEON GPU provides digital flat panel support through an integrated LVDS transmitter and an integrated TMDS transmitter. The TMDS transmitter in the latest generation of GPUs (M8x) has been enhanced to support a new interconnect standard DisplayPort (DP) in addition to the previous DVI/HDMI standards. The guidelines below apply to both LVDS and TMDS/DP signaling, unless otherwise specified. For more information on differential signaling, refer to the following documents: Digital Visual Interface, Rev 1.0 from DDWG (Digital Display Working Group). Electrical Characteristics of Low Voltage Differential Signaling (LVDS), ANSI/TIA/EIA- 644, March 1996, from Telecommunications Industry Association. HDMI Specification, ver 1.3 from HDMI Licencing, LLC DisplayPort Interface Standard, Rev. 1.1 from VESA. 7.1 LVDS/TMDS/DP Layout Guidelines General See also section 2.3 Critical Nets (High Speed Routing). Impedance matching is very important even for short runs in LVDS/TMDS/DP designs. Ensure proper impedance matching of PCB traces to avoid reflections. The recommended impedance is 100Ω with +/- 10% tolerance. See Appendix C for impedance calculating techniques. Signal reference plane should be solid plane but GND is preferred. There should be no plane breaks under or over the routing. Check the stack-up in order to make sure that the solid reference plane is the closet plan to the signal plane. Signal traces must not be run near the edge of a board must be kept to at least 0.2 inch from the edge in the case of the top/bottom layer and inner layers. (Note that the 0.2 inch requirement does not apply to the edge where the connecter is attached.) Traces routed at the edge of a GND plane should have at least a 50 mil distance to the plane edge. The perimeter of the PCB should have a GND via picket fence. The differential trace length from the transmitter to the connector must be kept as short and as equal as possible to minimize loss in the channel. When longer traces are unavoidable, attention must be paid to the increased possibility of cross-talk from adjacent signal pairs and from non-lvds/tmds/dp digital switching activities Advanced Micro Devices, Inc. LVDS and TMDS/DisplayPort Interfaces MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 24

25 To reduce cross-talk between adjacent pairs, keep the distance between adjacent pairs to 4 times the height (H) of the layer as shown below (note: for 1080-prepreg boards where H is small, use 3S instead of 4H for pair to pair spacing). Figure 9: Using Space to Reduce Cross-Talk To reduce skew within a pair, avoid unbalanced layer changes and unbalanced pair spacing (see Appendix C for intra-pair spacing and trace width calculations). It is preferred to route all differential signals on inner layers for noise immunity. If the traces are relatively short, they can be routed on the same side as the transmitter and connector to avoid the use of vias. It is important to minimize the number of via transitions in signal routing, since vias introduce parasitic inductance as well as capacitance, and degrade signal integrity. The maximum number of via transitions is two. If more than 2 vias are required, simulation should be performed by the customer to ensure signal integrity. To further improve signal integrity, select via type to minimize capacitance, and add ground via(s) close to the transition vias. Separate the TTL/CMOS signals from differential signals to avoid cross-talk. To increase distance, run a ground trace, or use a differential plane between TTL/CMOS and differential signals. Shunt resistors: Use shunt resistors for DVI/HDMI configurations only, do not use for DisplayPort configuration (see also Section 7.4 Board Compatibility Considerations). Shunt resistor values differ according to system configurations (refer to reference schematics for recommended values). The shunt resistor should be placed on each differential pair of data and clock signal and populated as close to the ASIC as possible. The maximum distance away should be no more than 8mm and 3mm for top layer and bottom layer respectively (see Figure 10 and Figure 11). Do not place the shunt resistor near the DVI/HDMI connector. Make sure the board layout has the shunt resistors on the same layer, as measurements from previous boards have shown best results when the shunt resistors were on the same layer as the breakout traces. Figure 10: Shunt Resistor Placement on Top Layer 2009 Advanced Micro Devices, Inc. LVDS and TMDS/DisplayPort Interfaces MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 25

26 Figure 11: Shunt Resistor Placement on Bottom Layer Place the clock source (OSC or XTAL) as far away as possible from the TMDS/DP transmitter. AC-coupling for TXOUT and TXCLK is optional; however, if ac-coupling is used, place the coupling components as close as possible to the DFP connector Skew Requirements To design a board that can accommodate multiple pin-compatible GPUs, it is convenient to separate delay times (or skews) into two budgets, one for the GPU package (covering all ASICs in the same family) and the other for the PCB. How the two budgets are used to derive skew requirements differ for Pre-M9x GPUs and M9x GPUs. Pre-M9x GPUs For board designs using pre-m9x GPUs, the skews from the package can be ignored. The table below shows the recommended maximum allowed skews for the LVDS/TMDS/DP differential traces on the PCB only. For the reader s convenience, delay times have been converted to lengths using conversion factors of 0.170ps/mil and 0.155ps/mil for inner and outer traces respectively; however, note that these values may vary slightly depending on the material of the PCB. Table 8: Recommended Maximum Trace Skews (ASIC to Connector, PCB Budget) for Pre- M9x GPUs Interface Time (ps) PCB only Intra-Pair Skew Length (mil) Time (ps) Inner layer Outer layer Inter-Pair Skew Length (mil) Inner layer Outer layer LVDS * DVI/HDMI Advanced Micro Devices, Inc. LVDS and TMDS/DisplayPort Interfaces MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 26

27 DisplayPort 7.5* * Preliminary value Notes: - Serpentine signal routing for skew reduction purpose is not recommended. If it is deemed necessary, discuss with AMD design engineers. - Inter-pair skew is more critical among data channels than between clock and data. M9x GPUs For M9x and forward compatible GPUs, a set of substrate lengths optimized for the M2 or S2 package will be provided. These package lengths should be included in the layout analysis of signal lengths. These optimized substrate lengths will apply to all GPUs in the forward compatible family of GPUs. Please see the OEM Resource Center for the M2 or S2 optimized substrate lengths. 7.2 MUX and Serial Resistors In some circumstances, a MUX may be necessary for muxing TMDS/DP links from a North Bridge graphics controller (IGP) and from a discrete graphics controller (GPU). This type of topology can be found on boards where the lower-end version of the board uses the IGP TMDS/DP links while the high-end version of the board uses the GPU TMDS/DP links. The recommended MUX implementation is to use an active MUX device; the second choice is through populating 0-ohm serial resistors. The use of a passive MUX device is not recommended. In mobile designs, the MUX can be implemented on the motherboard or on the docking PCB. If 0-ohm serial resistors are used, make sure the trace stubs are kept as short as possible as shown in Figure 12 below. Do not add serial resistors, capacitors or common-mode chokes on signal traces for EMI purpose, as they may adversely affect signal integrity; instead use better case shielding or place traces on the inner layer to improve EMI immunity. Figure 12: TMDS/DP Muxing 7.3 Power Rails De-Coupling Capacitor Recommendations De-coupling capacitors should be populated according to noise level on board. For TPVDD (or DPA_PVDD), T2PVDD (or DPB_PVDD), TXVDDR (or DPA_VDDR), and T2XVDDR (or DPB_VDDR), 0.1uF, 1uF and 10uF are recommended for noise filtering Advanced Micro Devices, Inc. LVDS and TMDS/DisplayPort Interfaces MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 27

28 7.4 Board Compatibility Considerations For a universal board designed to support both pre-m8x (DVI/HDMI) and M8x/M9x (DP) GPUs, additional pads must be provided to allow for different video interface choices (see Figure 15 below). With M8x/M9x parts, the coupling capacitors should be placed as close to the connector as possible. They should be of size 0402 and have a value of 100nF. They should not be staggered within the pair, but be staggered by at least 20mils (0.5mm) between pairs to eliminate the possibility of crosstalk between the lanes. No shunt resistors should be used. With M7x parts, the capacitors should be replaced by 0 ohm resistors, and the shunt resistors added in. Refer to applicable AMD reference schematics (e.g.: ref 133-4) for further details regarding use and non-use of certain components (shunt resistors, pull-down resistors, MOSFETs, etc.) for different configurations. Figure 13: Flexible Configuration for DP and DVI/HDMI Interfaces 2009 Advanced Micro Devices, Inc. LVDS and TMDS/DisplayPort Interfaces MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 28

29 8 DVP Interface 8.1 External TMDS Layout Guidelines If the DVP interface is used as an external TMDS interface, follow design rules and recommendations provided by the TMDS transmitter manufacturer. Follow the same rules in Section 7 above when routing traces from the output of external TMDS transmitter to the second DVI connector. Place discrete components as close as possible to the associated GPU pins. Avoid using vias as much as possible. A common digital and analog ground plane is recommended. Separate digital and analog power plane is recommended. Connect these two lanes at a single point through a ferrite bead. Isolate the digital outputs from the GPU as much as possible from the analog outputs and other analog circuitry. These output signals should not overlay the analog power plane or analog output signals. Keep in mind that digital interface signals are running up to 165MHz frequency in case of 1600x1200 panel resolution. All digital interface signals to the external TMDS transmitter (except pixel clock) are latched inside the output buffer, which provides minimum skew between signals at the output of the controller. From the DVP interface to the external TMDS transmitter: keep the length of all DVPDATA and control signals equal to the length of DVPCLK +/- 250mils. 8.2 CrossFire Layout Guidelines If the DVP interface is used for CrossFire purpose, follow the guidelines below. NOTE: The guidelines are based on tests conducted using 24-bit DDR interface and AMD designated cable and connector. Each cable and connector design requires thorough analysis and verification. IBIS models for simulations are available upon request Interface (Including Receptacle) Design/Layout Guidelines Frequency capability: 250 MHz, for all lines (assuming 24-bit DDR interface). Signal impedance: 50 ohms. Cross-talk reduction: Use proper measures to reduce cross-talk (e.g. distance and/or ground guarding). For the more critical clock line, use gnd/signal/gnd shielding arrangement; for other lines, it may be enough to simply rely on the shielding effect of the ground plane under them. RoHS compliant Cable Design/Layout Guidelines Two-layer cable: signals on top layer and solid ground plane as bottom layer. Use the same cross-talk shielding arrangement as the receptacle s. The GND shielding traces should be connected to the GND plane using one via per inch. Trace impedance: 50 ohms Advanced Micro Devices, Inc. DVP Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 29

30 Trace space to dielectric layer thickness ratio: 2 to 1. All signals must be length matched to within 5 mils PCB Layout Guidelines Trace impedance: 50 ohms Length matching: all DVPDATA, DVPCNTL, DVPCLK and DVP_MVP signal trace lengths must be within 50 mils of each other. Clock selection: Only one of the two clocks (DVPCLK and DVPCNTL_MVP_1) is used for 24-bit DDR mode operation. Choose the one that is centermost in the layout, as shown below. Group 1 12 data + control lines Group 2 12 data + control lines Group1 Clock line Group 2 Clock line Centermost clock Figure 14: Use Centermost DVP Clock for 24-Bit DDR Mode Operation Traces must be as direct as possible from the GPU to the receptacle. No stubs are allowed. Layer switching should be avoided or at least minimized. There must be a solid reference GND plane directly under the traces. Ratio of trace space to distance to the reference GND plane: Outer layer: 2 to 1 minimum Inner layers : 1.5 to 1 minimum If signals switch layers and are referenced to a new GND plane, then GND vias are required between the GND reference planes. These GND vias should be centered amongst the trace vias Advanced Micro Devices, Inc. DVP Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 30

31 9 Thermal Interface The DPLUS and DMINUS circuit forms a critical net together with the temperature monitor chip. Refer to section 2.3 Critical Nets (High Speed Routing) and to your temperature monitor vendor for routing guidelines Advanced Micro Devices, Inc. Thermal Interface MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 31

32 Appendix A: Via Electrical Model The electrical model of a via must include parasitic series inductance and shunt capacitance. The parasitic capacitance for a via is given by: C 1.41ε = rtd D D where: C is the parasitic via capacitance in pf ε r is the dielectric constant of material T is the overall thickness of PCB in inches D 1 is the diameter of pad surrounding via in inches D is the diameter of the clearance hole in ground plane(s) in inches 2 The above formula shows that by increasing the clearance of a via in ground plane(s), the capacitance is reduced. However, the value of the parasitic capacitance is usually less than onetenth of pf, which can be ignored in many practical situations. In contract, the inductance of a via, given by the formula below, is more significant. 4H L = 5.08H ln + 1 D Where: L is the parasitic via inductance in nh H is the length of via in inches D is the diameter of via in inches The geometry and the worst-case circuit model of a via (assuming a ground plane in every layer), based on the recommended 6-layer stack-up, is shown below. Figure 15: Through-hole Via Geometry and Circuit Model The figure below shows that a through-hole via can be approximated by a 0.7nH inductance (13.5-mil diameter x 62-mil depth). Note that increasing the via diameter reduces inductance (50-mil diameter x 62-mil depth), also note that a microvia (13-mil diameter x 2.8-mil depth) has much less inductance ATI Technologies Inc. Appendix A: Via Electrical Model MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 32

33 Figure 16: Impedance of Through-hole Via vs. Frequency Table 9: Electrical Parameters of Through-hole Via and Microvia Electrical Parameter Through-hole Via (0.062 deep) Microvia (0.002 deep) Typical Inductance 0.7nH 0.1nH Typical Capacitance 0.3pF 0.03pF Typical Delay 13ps 1.8ps Typical Impedance 350MHz 1GHz 350MHz 1GHz A quick calculation of X L = 2лfL can show that a through-hole via at the frequency of 1GHz is approximately 4.4Ω. This must be added in series to any passive element including decoupling capacitors when connected through a via ATI Technologies Inc. Appendix A: Via Electrical Model MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 33

34 Appendix B: Decoupling Capacitor Considerations B.1 Capacitor at High Frequency Because of the series inductance, the impedance of a real capacitor does not always decrease as the frequency goes up. An example of the measured impedance of a 10nF capacitor and a 22pF capacitor are shown in the figure below. Above 100MHz, increase in frequency increases the impedance of the 10nF capacitor; for the 22pF capacitor, the turning point is at 1GHz. Figure 17: Capacitor Impedance vs. Frequency B.2 Capacitor Placement and Routing Figure 17 above shows that a 10nF with a 22pF capacitor in parallel reduces impedance at high frequencies. This shows that using a bypassing capacitor for return path splitting does not work for high frequencies. Note that the graph only considers the capacitor s characteristics without considering board traces and vias. A practical design rule is to distribute equally the largest value of capacitor in the selected surface mount package. It must be kept in mind that placement of capacitors requires traces and possibly vias, which further increases the impedance. This increase in impedance due to traces and vias is critical at high frequencies and therefore greatly reduces the efficiency of the capacitor at high frequencies. The figures below compare an inefficient filter capacitor placement and layout with an efficient one ATI Technologies Inc. Appendix B: Decoupling Capacitor Considerations MOBILITY RADEON GPUs Graphics Subsystem Layout Guide Page 34