LatticeECP3 I/O Protocol Board to Texas Instruments ADC/DAC Adapter Board User Guide

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1 LatticeECP I/O Protocol Board to Texas Instruments ADC/DAC Adapter Board User Guide November 0 EB_.

2 Introduction LatticeECP I/O Protocol Board to Texas Instruments The LatticeECP I/O Protocol Board to TI ADC/DAC Adapter provides a convenient platform to evaluate, test and debug user designs and IP cores targeted for the LatticeECP-0 FPGA on the LatticeECP I/O Protocol Board, that are designed to interface directly with the Texas Instruments (TI) ADS6 and DAC68Z EVM boards. Other TI EVM boards may also be compatible with the LatticeECP I/O Protocol Board to TI ADC/DAC Adapter board. See Table 6 for a list of other compatible TI EVMs. When connected, the Lattice and TI evaluation boards lay out flat on the desktop in a mechanically stable test configuration. Important: This document (including the schematic and mechanical drawings in Appendix A) describes the LatticeECP I/O Protocol Board to TI ADC/DAC Adapter marked as Revision A. This marking can be seen on the silkscreen of the printed circuit board, under the Lattice Semiconductor logo. The LatticeECP is a third-generation device utilizing reconfigurable SRAM logic technology optimized to deliver high-performance features such as an enhanced DSP architecture, high-speed SERDES and high-speed source synchronous interfaces in an economical FPGA fabric. The LatticeECP devices also provide popular building blocks such as LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), and advanced configuration support, including encryption, multi-boot capabilities and TransFR field upgrade features. The LatticeECP SERDES-dedicated PCS functions, high jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII), SATA I/II, OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media. For a full description of the LatticeECP FPGA, see the Lattice web site for the LatticeECP Family Data Sheet, technical notes and more: For a full description of the LatticeECP I/O Protocol Board, see the LatticeECP I/O Protocol Board User s Guide. The ADS6 ADC device from Texas Instruments is a high-speed, multi-channel, low power, - and -bit pin compatible Analog-to-Digital Converter (ADC) which can be evaluated using the TI ADS6EVM board. The DAC68Z DAC device from Texas Instruments is a 6-bit,.0 GSPS x-x Interpolating Dual Channel Digital-to- Analog Converter (DAC) which can be evaluated using the TI DAC68ZEVM board. Both the ADS6EVM and DAC68ZEVM evaluation boards can interface with the LatticeECP I/O Protocol Board simultaneously through the LatticeECP I/O Protocol Board to TI ADC/DAC Adapter as shown in Figure.

3 LatticeECP I/O Protocol Board to Texas Instruments Figure. LatticeECP I/O Protocol Board Connected to TI ADC and DAC EVMs

4 General Description Figure. LatticeECP I/O Protocol Board to TI ADC/DAC Adapter Board LatticeECP I/O Protocol Board to Texas Instruments The LatticeECP I/O Protocol Board to TI ADC/DAC Adapter Board easily connects the high-speed signals available at the LatticeECP I/O Protocol Board s HMZD connector at J6, to the high-speed connectors used by the TI ADS6EVM at J0, and the DAC68ZEVM at J8. The Adapter Board also provides several other remaining differential HMZD connected signals at SMA connectors J, J, J, J, J7 and J9. Other slow-speed signals used by the TI ADC at J0 are brought out to connector J. The Adapter Board contains no active devices. Please observe proper ESD procedures when handling the boards connected to this Adapter Board.

5 LatticeECP I/O Protocol Board to Texas Instruments Additional resources for the LatticeECP I/O Protocol Board to TI ADC/DAC Adapter board, such as updates to this document, sample programs and links to demos can be found on the Lattice web site. Electrical, Mechanical, and Environmental Specifications The nominal board dimensions are. inches by. inches. Three 0. diameter plated through holes are provided to allow installation of plastic or metal spacers used to lift the board off the desktop to a uniform height. See the mechanical drawing in Appendix A for locations of the through holes. The environmental specifications are as follows: Operating temperature: 0 C to C Storage temperature: 0 C to 7 C Humidity: <9% without condensation HMZD Connector J6 is a high-speed HMZD header with 80 differential signal connections for interfacing the LatticeECP I/O Protocol Board to external application PCBs such as the TI ADC/DAC EVMs. The LatticeECP I/O Protocol Board has been verified to operate in a loop-through mode over the HMZD connector at up to 00 MT/s. The connections for J6 are listed in Table. Table. J6 HMZD Connections J8 Pin LatticeECP I/O Polarity sysio Bank I/O Description A AA P PR6A/PR8A B AA0 N PR6A/PR8B A AD P NC/PR97A B AD N NC/PR97B A AE0 P PR7A/PR0A B AE9 N PR7B/PR0B A AD6 P NC/PR06A B AD N NC/PR06B A AP P PR8A/PR0A B AP N PR8B/PR0B A6 K P NC/PRA B6 K N NC/PRB A7 T P PRA/PRA B7 T N PRB/PRB A8 R8 P PR8A /PR6A B8 R7 N PR8B /PR6B A9 R P PR9A/PR7A B9 R0 N PR9B/PR7B A0 N P PR0A/PR8A B0 N N PR0B/PR8B C W7 P PRA /PR7A D W6 N PRB /PR7B C Y6 P PR6A /PR79A D Y N PR6B /PR79B C AE P NC/PR9A D AE N NC/PR9B C AL0 P PR9A /PR8A

6 LatticeECP I/O Protocol Board to Texas Instruments Table. J6 HMZD Connections (Continued) J8 Pin LatticeECP I/O Polarity sysio Bank I/O Description D AM0 N PR9B /PR8B C AJ P PR88A /PRA D AK N PR88B /PRB C6 V9 P PRA /PR70A /VREF_ D6 W8 N PRB /PR70B /VREF_ C7 U P PRA/PR9A D7 U N PRB/PR9B C8 W P PR7A/PR6A D8 W N PR7B/PR6B C9 L0 N NC/PRB D9 M9 P NC/PRA C0 N6 P PR9A /PR7A D0 P6 N PR9B/PR7B E AA P PR6A /PR8A F AA6 N PR6B /PR8B E AA8 P PR70A /PR88A F AA7 N PR70B /PR88B E AD P NC/PR9A F AD0 N NC/PR9B E AC8 P NC/PR00A F AB7 N NC/PR00B E AM9 P PR97A /PRA F AN9 N PR97B /PRB E6 U8 P PR6A /PR6A /PCLKT_0 F6 V8 N PR6B /PR6B /PCLKC_0 E7 V P PRA/PR6A F7 V0 N PRB/PR6B E8 P8 P PRA /PRA F8 P7 N PRB /PRB E9 T9 P PRA /PRA /VREF_ F9 T8 N PRB /PRB /VREF_ E0 N P PRA/PRA F0 N N PRB/PRB G U N PRE_B/PR6E_B/RUM0_GPLLT_FB_B H U P PRE_A/PR6E_A/RUM0/GPLLT_FB_A G Y P PR6A/PR7A H Y N PR6B/PR7B G U6 P PRA /PR6A /PCLKT_0 H U7 N PRA /PR6B /PCLKC_0 G AH P PR8A /PR09A H AJ N PR8B /PR09B G AP P PR9A/PR9A H AN N PR9B/PR9B G6 W P PR0A/PR68A 6

7 LatticeECP I/O Protocol Board to Texas Instruments Table. J6 HMZD Connections (Continued) J8 Pin LatticeECP I/O Polarity sysio Bank I/O Description H6 W N PR0B/PR68B G7 R P PRA/PR0A H7 R N PRB/PR0B G8 T6 P PR7A /PRA /RUM0_GDLLT_IN_A H8 T7 N PR7B /PRB /RUM0_GDLLT_IN_B G9 N0 P PR7A/PRA H9 N9 N PR7B/PRB G0 P P PR6A/PRA H0 P N PR6B/PRB. I/O with true LVDS output capability.. I/O description lists both LatticeECP 9/ 0 density devices. SMA Signal Connectors There are three pairs of SMA connectors that provide general purpose high-speed differential signal paths to the LatticeECP through the HMZD connector J6. The SMA connectors are provided for general purpose user-definable signals. Table details to which I/O pin each SMA connector is wired. Table. SMA Connectors to the LatticeECP-0 Device, Location LatticeECP I/O Polarity sysio Bank I/O Description J7 U N PRE_B/PR6E_B/RUM0_GPLLT_FB_B J9 U P PRE_B/PR6E_B/RUM0_GPLLT_FB_A J K P NC/PRA J K N NC/PRB J L0 N NC/PRB J M9 P NC/PRA. The LatticeECP I/O pin numbers shown at the SMA connectors printed on the Adapater Board silk layer, are no longer valid.. J, J, J7 and J9 polarity indicators (P and N) printed on the Adapter Board silk layer, are swapped.. I/O with true LVDS output capability. TI ADC EVM Connector J0 J0 is a high-speed header with 6 differential signal connections for interfacing the LatticeECP I/O Protocol Board to a TI ADS6 EVM. Not all J0 pins are used by the TI ADS6 EVM, but other boards may use those unused pins. The connections for J0 are listed in Table. Table. TI ADC EVM Connections at J0 J0 Pin ADS6 Signal LatticeECP Pin Polarity sysio Bank I/O Description J6 Pin 8 N9 N PR7B/PRB H9 0 N0 P PR7A/PRB G9 P6 N PR9B /PR7B D0 6 N6 P PR9A /PR7A C0 0 N N PR0B/PR8B B0 N P PR0A/PR8A A0 6 N N PRB/PRB F0 8 N P PRA/PRA E0 DA0_M P7 N PRB /PRB F8 DA0_P P8 P PRA /PRA E8 7

8 LatticeECP I/O Protocol Board to Texas Instruments Table. TI ADC EVM Connections at J0 (Continued) ADS6 LatticeECP J0 Pin Signal Pin Polarity sysio Bank I/O Description J6 Pin 8 DA_M P N PR6B/PRB H0 0 DA_P P P PR6A/PRA G0 DB0_M R7 N PR8B /PR6B B8 6 DB0_P R8 P PR8A /PR6A A8 0 DB_M R0 N PR9B/PR7B B9 DB_P R P PR9A/PR7A A9 6 DCLK_M U7 N PRB /PR6B /PCLKC_0 H 8 DCLK_P U6 P PRA /PR6B /PCLKT_0 G 6 FCLK_M T7 N PR7B /PRB /RUM0_GDLLT_IN_B H8 66 FCLK_P T6 P PR7A /PRA /RUM0_GDLLT_IN_A G8 70 DC0_M R N PRB/PR0B H7 7 DC0_P R P PRA/PR0A G7 76 DC_M T8 N PRB /PRB /VREF_ F9 78 DC_P T9 P PRA /PRA /VREF_ E9 8 DD0_M T N PRB/PRB B7 8 DD0_P T P PRA/PRA A7 88 DD_M U N PRB/PR9B D7 90 DD_P U P PRA/PR9A C7 9 V0 N PRB/PR6B F7 96 V P PRA/PR6A E7 00 V8 N PR6B /PR6B F6 0 U8 P PR6A /PR6A E6 06 W N PR7B/PR6B D8 08 W P PR7A/PR6A C8 W N PR0B/PR68B H6 W P PR0A/PR68A G6. I/O with true LVDS output capability.. I/O description lists both LatticeECP 9/ 0 density devices. TI DAC EVM Connector J8 J8 is a high-speed header with 8 differential signal connections for interfacing the LatticeECP I/O Protocol Board to a TI DAC68Z EVM. The connections for J8 are listed in Table. Table. TI DAC EVM Connections at J8 J8 Pin DAC68Z Signal LatticeECP Pin Polarity sysio Bank I/O Description J6 Pin 7 DP AP P PR9A/PR9A G 9 DN AN N PR9B/PR9B H DP AL0 P PR9A /PR8A C DN AM0 N PR9B /PR8B D 9 DP AJ P PR88A /PRA C 6 DN AK N PR88B /PRB D 6 DP AP P PR8A/PR0A A 67 DN AP N PR8B/PR0B B 8

9 LatticeECP I/O Protocol Board to Texas Instruments Table. TI DAC EVM Connections at J8 (Continued) DAC68Z J8 Pin Signal LatticeECP Pin Polarity sysio Bank I/O Description J6 Pin 7 DP AH P PR8A /PR09A G 7 DN AJ N PR8B /PR09B H 77 D0P AD6 P NC/PR06A A 79 D0N AD N NC/PR06B B 8 D9P AE0 P PR7A/PR0A A 8 D9N AE9 N PR7B/PR0B B 89 D8P AC8 P NC/PR00A E 9 D8N AB7 N NC/PR00B F 9 DCLKP AM9 P PR97A /PRA E 97 DCLKN AN9 N PR97B /PRB F 96 CLKOUTP V9 P PRA /PR70A /VREF_ C6 98 CLKOUTN W8 N PRB /PR70B /VREF_ D6 0 D7P AE P NC/PR9A C 0 D7N AE N NC/PR9B D 07 D6P AD P NC/PR9A E 09 D6N AD0 N NC/PR9B F DP AA8 P PR70A /PR88A E DN AA7 N PR70B /PR88B F 9 DP AA P PR6A/PR8A A DN AA0 N PR6B/PR8B B DP AA P PR6A /PR8A E 7 DN AA6 N PR6B /PR8B F DP Y6 P PR6A /PR79A C DN Y N PR6B /PR79B D 7 DP Y P PR6A/PR7A G 9 DN Y N PR6B/PR7B H D0P W7 P PRA /PR7A C D0N W6 N PRB /PR7B D SYNCP AD P NC/PR97A A 7 SYNCN AD N NC/PR97B B. I/O with true LVDS output capability.. I/O description lists both LatticeECP 9/ 0 density devices. 9

10 ADC Control Signals Connector J LatticeECP I/O Protocol Board to Texas Instruments There are five additional J0 signals with GND brought over to the ADC control signals header J, as shown in Table. Table. ADC Control Signals at J J Pin Signal Name J0 Pin Description RST ADC reset when low PDN ADC power down when high SEN ADC serial interface enable SDATA 7 ADC serial interface data SCLK 9 ADC serial interface clock 6 GND GND GND. Other TI ADC EVM boards may or may not use the same signal locations on J0. Compatible TI ADC/DAC EVMs Table 6 lists the TI EVM boards currently known to be compatible with the adapter board, likely to be compatible, and those that are not compatible due to data path connector mismatch or some other reason. The table is provided as supplemental information only and is at this time thought to be accurate. Please refer to the TI web site and TI EVM user's guides for the most accurate up to date information about any TI EVM you might be considering for use with this adapter. Table 6. Compatible TI ADC/DAC EVMs Technical Support Assistance techsupport@latticesemi.com Internet: TI EVM Type Compatible ADS6XX ADC Yes ADS6XX ADC Yes DAC68/8z/8z DAC Yes ADS6PXX ADC Likely ADS6X9/XX ADC Likely ADS8X ADC Likely ADS0//6/7 ADC Likely DAC686/88/89 DAC No DAC687 DAC No THS6XX DAC No DEM-DAC90x DAC No DAC67/7 DAC No DAC90x DAC No DAC67/6/ DAC No 0

11 LatticeECP I/O Protocol Board to Texas Instruments Revision History Date Version Change Summary November 0. Corrected descriptions for J0 pin 9- in Table, TI ADC EVM Connections at J0. Corrected descriptions for J8 pins,,77,79,, in Table, TI DAC EVM Connections at J8. Updated corporate logo. Updated Technical Support Assistance section. May Added new figure - LatticeECP I/O Protocol Board Connected to TI ADC DAC EVMs. April Added Compatible TI ADC/DAC EVMs text section and table. March Initial release. 0 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

12 Appendix A. Schematic Figure. LatticeECP I/O Protocol Board to TI ADC/DAC Adapter Board LatticeECP I/O Protocol Board to Texas Instruments ECP IO Protocol Evaluation Board TI DAC EVM ECP IOP to TI ADC/DAC Adapter J6 RDAT_P SPI_TDAT_P J8 A A RDCLK_P SPI_TDCLK_P A A RDAT_P9 SPI_TDAT_P9 A A RDAT_P0 SPI_TDAT_P0 A A RDAT_P SPI_TDAT_P A A 0 TSCLK SPI_RSCLK A6 A6 TDAT_P0 SPI_RDAT_P0 P (AJ) A7 A7 TDAT_P6 SPI_RDAT_P6 TI ADC EVM J7 D A8 A8 6 TDAT_P7 SPI_RDAT_P7 D 7 8 J0 A9 A9 TDAT_P SPI_RDAT_P SMA A0 A0 9 0 BG RDAT_N SPI_TDAT_N SPI_TSTAT GND_B B B RDCLK_N SPI_TDCLK_N SPI_RDAT_N0 D0_MS SPI_TSTAT0 PLL in BG GND_B B B 6 BG RDAT_N9 SPI_TDAT_N9 SPI_RDAT_P0 D0_PS GND_B B B BG RDAT_N0 SPI_TDAT_N0 GND_B B B 9 0 BG RDAT_N SPI_TDAT_N SPI_RDAT_N D_MS GND_B B B NC SPI_RSCLK_NC SPI_RDAT_P D_PS N (AK) BG6 GND_B6 B6 B6 6 BG7 TDAT_N0 SPI_RDAT_N0 B7 B J9 GND_B7 BG8 TDAT_N6 SPI_RDAT_N6 SPI_RDAT_N D_MS GND_B8 B8 B TDAT_N7 SPI_RDAT_N7 J6 (HMZD) BG9 SPI_RDAT_P D_PS B9 B9 9 0 SMA GND_B9 BG0 TDAT_N SPI_RDAT_N GND_B0 B0 B0 SPI_RDAT_N D_MS 6 RDAT_P0 SPI_TDAT_P0 SPI_RDAT_P D_PS C C RDAT_P SPI_TDAT_P SPI_TDAT_P DP C C RDAT_P7 SPI_TDAT_P7 SPI_TDAT_N DN SPI_RDAT_N DA0_MS C C 9 0 RDAT_P SPI_TDAT_P SPI_RDAT_P DA0_PS C C RDAT_P SPI_TDAT_P SPI_TDAT_P DP P (N6) C C 6 TCTL_P SPI_RCTL_P SPI_TDAT_N DN SPI_RDAT_N DA_MS C6 C J DG TDAT_P SPI_RDAT_P SPI_RDAT_P DA_PS GND_D C7 C DG TDAT_P SPI_RDAT_P SPI_TDAT_P DP C8 C SMA GND_D DG TSTAT SPI_RSTAT SPI_TDAT_N DN ECP SPI_RDAT_N6 DB0_MS GND_D C9 C9 6 6 TDAT_P SPI_RDAT_P SPI_RDAT_P6 DB0_PS C DG LVDS SPI_RSCLK GND_D C0 C C SPI_TDAT_P DP in SPI_RSCLK_NC HS IO DG GND_D DG6 RDAT_N0 SPI_TDAT_N0 SPI_TDAT_N DN SPI_RDAT_N7 DB_MS GND_D6 D D DG7 RDAT_N SPI_TDAT_N SPI_RDAT_P7 DB_PS GND_D7 D D DG8 RDAT_N7 SPI_TDAT_N7 SPI_TDAT_P DP GND_D8 D D 7 7 RDAT_N SPI_TDAT_N SPI_TDAT_N DN (PLL) SPI_TSCLK_NC DCLK_MS N (P6) DG9 GND_D9 D D DG0 RDAT_N SPI_TDAT_N 7 76 SPI_TSCLK DCLK_PS 8 7 J GND_D0 D D TCTL_N SPI_RCTL_N SPI_TDAT_P0 D0P D6 D TDAT_N SPI_RDAT_N SPI_TDAT_N0 D0N SMA D7 D7 TDAT_N SPI_RDAT_N (DLL) SPI_RDCLK_N FCLK_MS D8 D TSTAT0 SPI_RSTAT0 SPI_TDAT_P9 D9P SPI_RDCLK_P FCLK_PS D9 D TDAT_N SPI_RDAT_N SPI_TDAT_N9 D9N D0 D SPI_RDAT_N8 DC0_MS RDAT_P SPI_TDAT_P SPI_TDAT_P8 D8P ECP LVPECL in SPI_RDAT_P8 DC0_PS E E RDAT_P SPI_TDAT_P SPI_TDAT_N8 D8N (PLL) E E RDAT_P6 SPI_TDAT_P6 SPI_RDAT_N9 DC_MS P (N7) E E FG RDAT_P8 SPI_TDAT_P8 SPI_TCTL_P DCLKP 9 96 CLKOUTP SPI_RCTL_P SPI_RDAT_P9 DC_PS J GND_F E E FG RCTL_P SPI_TCTL_P ECP SPI_TCTL_N DCLKN CLKOUTN SPI_RCTL_N GND_F E E FG TDAT_P SPI_RDAT_P LVDS SPI_RDAT_N0 DD0_MS 8 8 SMA GND_F E6 E6 FG TDAT_P SPI_RDAT_P out SPI_TDAT_P7 D7P 0 SPI_RDAT_P0 DD0_PS GND_F E7 E FG TDAT_P SPI_RDAT_P SPI_TDAT_N7 D7N 0 SPI_RSTAT GND_F E8 E TDAT_P9 SPI_RDAT_P9 SPI_RDAT_N DD_MS SPI_RSTAT0 HS IO FG6 GND_F6 E9 E FG7 TDAT_P SPI_RDAT_P SPI_TDAT_P6 D6P 07 SPI_RDAT_P DD_PS GND_F7 E0 E FG8 SPI_TDAT_N6 D6N GND_F B FG9 RDAT_N SPI_TDAT_N SPI_RDAT_N D_MS B GND_F9 F F 9 9 RDAT_N SPI_TDAT_N SPI_TDAT_P DP SPI_RDAT_P D_PS N (N8) FG0 GND_F0 F F 96 9 RDAT_N6 SPI_TDAT_N6 SPI_TDAT_N DN F F J RDAT_N8 SPI_TDAT_N8 7 8 SPI_RDAT_N D_MS F F RCTL_N SPI_TCTL_N SPI_TDAT_P DP 9 0 SPI_RDAT_P D_PS F F 0 0 SMA TDAT_N SPI_RDAT_N SPI_TDAT_N DN F6 F6 0 0 TDAT_N SPI_RDAT_N SPI_RDAT_N D6_MS F7 F TDAT_N SPI_RDAT_N SPI_TDAT_P DP 6 SPI_RDAT_P D6_PS J F8 F8 TDAT_N9 SPI_RDAT_N9 SPI_TDAT_N DN F9 F TDAT_N SPI_RDAT_N 9 0 SPI_RDAT_N D7_MS ADC_RST F0 F0 SPI_TDAT_P DP SPI_RDAT_P D7_PS FPGA_PDN HG RSTAT SPI_TSTAT SPI_TDAT_N DN 6 FPGA_SEN GND_H G G HG RDAT_P SPI_TDAT_P 6 8 FPGA_SDATA GND_H G G 7 HG RSCLK SPI_TSCLK SPI_TDAT_P DP FPGA_SCLK GND_H G G HG RDAT_P SPI_TDAT_P SPI_TDAT_N DN GND_H G G 9 0 HG RDAT_P SPI_TDAT_P GND_H G G HG6 TDAT_P SPI_RDAT_P SPI_TDAT_P0 D0P GND_H6 G6 G6 HG7 TDAT_P8 SPI_RDAT_P8 SPI_TDAT_N0 D0N GND_H7 G7 G7 6 HG8 TDCLK_P SPI_RDCLK_P HEADER 6 GND_H8 G8 G8 HG9 TDAT_P0 SPI_RDAT_P0 GND_H9 G9 G HG0 TDAT_P SPI_RDAT_P GND_H0 G0 G0 QSH F-D-A RSTAT0 SPI_TSTAT0 SPI_TDCLK_P SYNCP H H 6 RDAT_N SPI_TDAT_N SPI_TDCLK_N SYNCN H H 7 8 A NC SPI_TSCLK_NC 9 60 Lattice Semiconductor Corporation A H H RDAT_N SPI_TDAT_N H H N.E. Moore Court RDAT_N SPI_TDAT_N H H TDAT_N SPI_RDAT_N Hillsboro, Oregon. 97 H6 H6 6 6 TDAT_N8 SPI_RDAT_N8 H7 H7 6 6 TDCLK_N SPI_RDCLK_N 6 66 Title H8 H8 TDAT_N0 SPI_RDAT_N0 H9 H TDAT_N SPI_RDAT_N ECP IOP to TI ADC/DAC Adapter H0 H Size Project Rev All high speed signals use 0 ohm traces TYCO HMZD Receptacle (Header version is TYCO HMZD 6908-) B ECP IOP TI ADC/DAC Adapter Schematic A ASP-9-0 Date: Friday, July 0, 009 Sheet of

13 LatticeECP I/O Protocol Board to Texas Instruments Figure. Mechanical Drawing Mechanical Drawing D D C C B B A Lattice Semiconductor Corporation A N.E. Moore Court Hillsboro, Oregon. 97 Title Mechanical Drawing Size Project Rev ECP IOP TI ADC/DAC Adapter Schematic A B Friday, July 0, 009 Date: Sheet of

14 LatticeECP I/O Protocol Board to Texas Instruments Figure. Mechanical Drawing Connected D D C C B B A Lattice Semiconductor Corporation A N.E. Moore Court Hillsboro, Oregon. 97 Title Mechanical Drawing Size Project Rev ECP IOP TI ADC/DAC Adapter Schematic A B Friday, July 0, 009 Date: Sheet of

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